Those sorts of accesses are split up and translated in parts in the simple CPU because they cross the boundaries of blocks in the peer connected to the CPU's dcache port. The other models will need to do that too in order to support unaligned accesses in the future. There are other cases where the size matters, though, like alignment checks for ISAs that care and segmentation checks for X86.
Gabe Ali Saidi wrote: > Umm... no the size is actually important. Imagine if you have an > unaligned 8 byte load that crosses a page boundary. > > Ali > > On Apr 10, 2009, at 8:02 PM, Korey Sewell wrote: > > >> Well, >> I dont think pretending to do the access would work for the TLB >> necessarily. >> >> I can see that the actual size of the access is irrelevant for the >> TLB translation (right?). Maybe we can work around that. >> >> But what about the type of access? That comes from the memory access >> flags and the only object that knows those flags is the actual >> instruction object. So that seems to be the big problem there. >> >> On Fri, Apr 10, 2009 at 5:23 PM, nathan binkert <[email protected]> >> wrote: >> >>> That's a legitimate problem. Would it work to pretend to do the >>> >> access >> >>> and save the request object for later? >>> >> I think we should strive to do this. >> >> Nate >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> >> >> -- >> ---------- >> Korey L Sewell >> Graduate Student - PhD Candidate >> Computer Science & Engineering >> University of Michigan >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
