OK, I took a week off from the InOrder stuff to fix MIPS-O3, so I'm getting back to this...BTW, I got the gzip regression to pass earlier today w/Inorder so we're on our way hopefully from that standpoint...
To refresh our memory, we were discussing how to get the size of a memory access and the flags for the memory access available to the CPU so that it can create a request for the TLB translation and then eventually use that request for the cache access. If it's not too much too ask, check the above thread for more specifics on the problem... So Nate, I'll try to answer your question below: On Tue, Apr 14, 2009 at 2:42 PM, nathan binkert <[email protected]> wrote: > I'll admit that I'm not following this thread very closely, but the > biggest question I have is: is it necessary to actually do the > translation in the translation pipe stage? Can't it just be there to > burn a cycle while you do the actual translation when executing the > read? Sure, there's no reason that a pipe stage has to be dedicated to only translating or only doing a cache access. You can do initiate a data access on a cycle by translating the address and then doing the access on the same cycle if you want. The big reason that I split the TLB and the Cache into separate resources to access is because I thought there might be situations where you would want to bypass the TLB altogether (simple embedded app?) or you had some type of system where your queuing memory accesses dependent on some load. You may want to take advantage of TLB translation bandwidth there instead of being restricted to always doing the translation and access on the same cycle. -- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan
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