>> I'll admit that I'm not following this thread very closely, but the >> biggest question I have is: is it necessary to actually do the >> translation in the translation pipe stage? >> >> Can't it just be there to >> burn a cycle while you do the actual translation when executing the >> read? > > Sure, there's no reason that a pipe stage has to be dedicated to only > translating or only doing a cache access. You can do initiate a data access > on a cycle by translating the address and then doing the access on the same > cycle if you want. > > The big reason that I split the TLB and the Cache into separate resources to > access is because I thought there might be situations where you would want > to bypass the TLB altogether (simple embedded app?) or you had some type of > system where your queuing memory accesses dependent on some load. You may > want to take advantage of TLB translation bandwidth there instead of being > restricted to always doing the translation and access on the same cycle.
That's not what I mean. What I'm saying is, simulate the timing of a TLB stage, but do the functional access with the memory stage. I.e. split it for timing purposes, but leave it together for functional reasons. I'd be surprised if this does not work since the timing of TLB accesses at that granularity shouldn't have much of an impact on the program. I think Steve agreed with me on this one. (right Steve?) Nate _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
