Gabe,
in your example, you're assuming that the instruction has called read. The
big problem is that the instruction *hasnt* called read (or write) and
currently that's the only mechanism for a M5 CPU model to figure out the
access size and flags for an instruction object.

On Fri, Apr 10, 2009 at 9:04 PM, Gabe Black <[email protected]> wrote:

> It could work like this:
>
> 1. Instruction calls read with flags.
> 2. Build a request with the flags and the right size, translate it, and
> stick it in the dynInst.
> 3. Actually do the read with the translated request.
>
> Or if you want to break it up more:
>
> 1. Instruction calls read with flags.
> 2. Build a request with the flags and the right size, and stick it in
> the dynInst.
> 3. Pull out the request, translate it, and stick it back in the dynInst.
> 4. Actually do the read with the translated request.
>
> Korey Sewell wrote:
> > Well,
> > I dont think pretending to do the access would work for the TLB
> > necessarily.
> >
> > I can see that the actual size of the access is irrelevant for the TLB
> > translation (right?). Maybe we can work around that.
> >
> > But what about the type of access? That comes from the memory access
> > flags and the only object that knows those flags is the actual
> > instruction object. So that seems to be the big problem there.
> >
> > On Fri, Apr 10, 2009 at 5:23 PM, nathan binkert <[email protected]
> > <mailto:[email protected]>> wrote:
> >
> >     > That's a legitimate problem. Would it work to pretend to do the
> >     access
> >     > and save the request object for later?
> >
> >     I think we should strive to do this.
> >
> >      Nate
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> >
> >
> >
> >
> > --
> > ----------
> > Korey L Sewell
> > Graduate Student - PhD Candidate
> > Computer Science & Engineering
> > University of Michigan
> > ------------------------------------------------------------------------
> >
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> >
>
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-- 
----------
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science & Engineering
University of Michigan
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