On Tue, 15 May 2018 08:33:13 -0700, Charles Mills <charl...@mcn.org> wrote:
>I should know better than to poke this thing again but I just do not see how >it makes sense. > >- If the code runs AM=31 then 32-bit addresses will not work. Doing a GETMAIN LOC=32 will still work if AM31 because GETMAIN is smart enough to check the current AMODE and if it is 24 you will only get LOC=24 storage and if it is 31 you will only get LOC=31 storage. >- If the code runs AM=64 then the high words of the > registers are significant. One cannot count on them > being zero -- trust me on this, been there and got > the S0C4 tee shirt* -- There are multiple ways of guaranteeing 0. The best is IBM guaranteeing it on entry to a program, as another RFE. In the single test that I requested, the high bits seem to be 0 already. I just want to formalize that. > so you now have to at least be cognizant of high > halves of registers, which defeats the OP's idea > of pretending that bits 0-31 don't exist. You have > to save those high halves (if you want to be > well-behaved) If IBM won't guarantee it, then startup code can conditionally check if it was invoked in AM64 and do a single F5SA save area, and from then on the normal 32-bit code can be run. > and you have to zero or LLGF into them. And by > running AM=64 aren't you getting away from this > (silly IMHO) concept of portability back to s/370? No. AM64 would be done on z/OS only. The code should be trimodal (24/31/64) and thus run happily in AM24 on S/370. The LOC=32 flags will be ignored on S/370. >Does that not make the case for this fall apart? I don't think so. > Follow @Jim's suggestion of requesting that STORAGE > support asking for storage in the 2GB to 4GB range. > That is your entire solution, right? I would prefer to have a GETMAIN LOC=32 that called IARV64 under the covers rather than my application needing to do that. >*In fact at the last SHARE I learned a cool testing > technique from @Ray Mullins. When testing an > AM=64 subroutine, on entry do a LHM 0,15,=16F'-1'. > That way you will pick up in testing any failures to > properly initialize high register halves. Otherwise > it will bite you now and then down the road. And a similar load (LMH) with F'0' will do the required initialization of everything. BFN. Paul. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
