> Subject: [PATCH v3 19/31] drm/i915/bios: parse Snps's VS/PE-O tables
>
> Snps's VS/PE-O tables' layout match with dg2_snps_phy_buf_trans layout.
> However VBT-based values are u32 while dg2_snps_phy_buf_trans uses u8.
> This width mismatch prevents from casting block->tables to point at
> dg2_snps_phy_buf_trans and parsing it trivially.
>
> We will temporarily increase dg2_snps_buf_trans size but eventually we will
> get
> rid of it later. Thus stick to the approach used for LT's VS/PE-O parsing.
>
> Parse each entry from every table into kzalloc'd buffers' matrix. Read number
> of
> tables and number of columns from the block. Assume that each table contains
> 16 rows.
>
> Inflate dg2_snps_phy_buf_trans since each VBT-based value is stored on u32.
> Reducing the size will be done in separate commit.
>
> Add Snps to workaround for availability of VS/PE-O parsing.
>
> v2->v3
> - remove unnecessary braces from if blocks
>
> Signed-off-by: Michał Grzelak <[email protected]>
Same thing here squash patches 19, 20
Regards,
Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 36 +++++++++++++++++--
> .../drm/i915/display/intel_ddi_buf_trans.h | 6 ++--
> 2 files changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 1b14cffe641ae..2d556889316f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2187,6 +2187,30 @@ parse_compression_parameters(struct intel_display
> *display)
> }
> }
>
> +static void
> +parse_vswing_preemph_snps(union intel_ddi_buf_trans_entry **bufs_mtrx,
> + const struct bdb_vswing_preemph *block) {
> + union intel_ddi_buf_trans_entry *entry;
> + const u32 *tables = block->tables;
> + u8 num_rows = 16;
> + size_t offset = 0;
> + const u32 *vals;
> +
> + for (int idx = 0; idx < block->num_tables; idx++) {
> + for (int row = 0; row < num_rows; row++) {
> + vals = &tables[offset];
> +
> + entry = &bufs_mtrx[idx][row];
> + entry->snps.vswing = vals[0];
> + entry->snps.pre_cursor = vals[1];
> + entry->snps.post_cursor = vals[2];
> +
> + offset += block->num_columns;
> + }
> + }
> +}
> +
> static void
> parse_vswing_preemph_lt(union intel_ddi_buf_trans_entry **bufs_mtrx,
> const struct bdb_vswing_preemph *block) @@ -
> 2234,10 +2258,13 @@ parse_vswing_preemph_override(struct intel_display
> *display)
> for (int idx = 0; idx < block->num_tables; idx++)
> bufs_mtrx[idx] = kzalloc_objs(**bufs_mtrx, num_rows);
>
> - if (HAS_LT_PHY(display))
> + if (HAS_LT_PHY(display)) {
> parse_vswing_preemph_lt(bufs_mtrx, block);
> - else
> + } else if (DISPLAY_VER(display) >= 14) {
> + parse_vswing_preemph_snps(bufs_mtrx, block);
> + } else {
> drm_dbg_kms(display->drm, "VS/PE-O parsing not yet
> supported\n");
> + }
>
> display->vbt.vspeo.bufs_mtrx = bufs_mtrx;
> display->vbt.vspeo.num_tables = block->num_tables; @@ -2695,8
> +2722,11 @@ static void override_vswing_preemph(struct
> intel_bios_encoder_data *devdata)
> if (!intel_bios_encoder_overrides_vswing(devdata))
> return;
>
> - if (HAS_LT_PHY(display))
> + if (HAS_LT_PHY(display)) {
> + parseable = true;
> + } else if (DISPLAY_VER(display) >= 14) {
> parseable = true;
> + }
>
> if (!parseable)
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 30fafeeaf62f2..1b48d66189ede 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -45,9 +45,9 @@ struct tgl_dkl_phy_ddi_buf_trans { };
>
> struct dg2_snps_phy_buf_trans {
> - u8 vswing;
> - u8 pre_cursor;
> - u8 post_cursor;
> + u32 vswing;
> + u32 pre_cursor;
> + u32 post_cursor;
> };
>
> struct xe3plpd_lt_phy_buf_trans {
> --
> 2.45.2
