On 8/15/07, Mark <[EMAIL PROTECTED]> wrote: > For an 8x8->16 multiplier, I get: > Synplify tries for 200MHz, achieves 110MHz > MAP reports 41 slices (1%) > PAR tries for 114MHz, achieves 98MHz
Cool. Now, the Xilinx tool will figure out if you've put extra layers or registers after the multiplier and automatically pipeline it. What do you get if you register the product and then add another register delay? Also, how are you ensuring that I/O buffers are not being inferred and considered in the static timing analysis? -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
