On 8/18/07, Farhan Mohamed Ali <[EMAIL PROTECTED]> wrote: > Attached is the radix-4 multiplier. Since it was easy to make it signed, i > just went with that. Adding support to select signed/unsigned is also easy. > Can someone with the Lattice tools try synthesizing this? I don't have it > installed on my laptop as i'm running out of space. On xilinx i get just > under 7.2ns, which is the delay through the 33 bit adder/subtracter. Takes > 17 cycles to complete a 32x32 multiply.
This is cool stuff. For one thing, I think I need to read up on some of the Verilog 2001 syntax. I learned Verilog in 1999, so I'm a bit behind the times and could benefit from some things that would at least save some typing. Anyhow, what I think would be fun is to try out a variety of designs and compare them. Different approaches will take different numbers of clock cycles, require different amounts of logic area, and have different maximum clock rates. A wide exploration of this space could be of academic interest. Perhaps a journal would be interested in a submission on this. Or perhaps we're repeating work already done, but it still might be nice to offer some reference implementations under GPL and/or LGPL with known characteristics for certain FPGAs. On the other hand, we should avoid getting TOO distracted. The nanocontroller is something someone's bound to want to incorporate into another design, and of course, it's in our main path for OGA1. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
