What I usually do is add a few layers of registers between the logic block and the IOBs. In the case of the multiplier, however, be aware that the synthesizer may try to pipeline it for you if it sees stages of registers with no other logic. What you may want to do is make up some dummy logic to go in the surrounding stages.
So to see its performance in isolation in one stage: - register inputs a, b, c, d, and e - compute a+b and c+d and register those, yielding f, and g - multiply f*g, and register that, yielding h - add h+e, and register that, yielding g - add another register from g to the output pins Then, if you want to experiment with automatic pipelining (again, I don't know if Lattice has that option), then just insert another register stage after h, call it h2. On 8/16/07, Farhan Mohamed Ali <[EMAIL PROTECTED]> wrote: > On Thu, August 16, 2007 8:54 am, Timothy Normand Miller said: > > Also, how are you ensuring that I/O buffers are not being inferred and > > considered in the static timing analysis? > Sorry if this has already been described somewhere, but i was wondering > how that is done as well. the IOBs mess up my timing analysis a lot. > > I'll code up the radix-4 multiplier. What formats does it have to > support? signed/unsigned/2c? > > -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
