Farhan Mohamed Ali wrote:
Attached is the radix-4 multiplier. Since it was easy to make it signed, i
just went with that. Adding support to select signed/unsigned is also easy.
Can someone with the Lattice tools try synthesizing this? I don't have it
installed on my laptop as i'm running out of space. On xilinx i get just
under 7.2ns, which is the delay through the 33 bit adder/subtracter. Takes
17 cycles to complete a 32x32 multiply.
Synplify tries for 200Mhz and achieves 125MHz. Map reports 76 slices
(107 4LUTs). PAR tries for 137MHz and achieves 120MHz. It looks like
the source flop is packed into an IO (again, I don't yet know how to
address that on this toolchain). Below is an excerpt from the post-PAR
timing report, FYI:
Logical Details: Cell type Pin type Cell/ASIC name (clock net
+/-)
Source: FF Q multiplicandreg_0io_0
(from clk_c +)
Destination: FF Data in product_62 (to clk_c +)
Delay: 8.345ns (46.0% logic, 54.0% route), 20 logic
levels.
Constraint Details:
8.345ns physical path delay multiplicand_0_MGIOL to SLICE_52 exceeds
7.320ns delay constraint less
-0.129ns skew and
0.129ns DIN_SET requirement (totaling 7.320ns) by 1.025ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.390 IOL_T18A.CLK to IOL_T18A.INFF
multiplicand_0_MGIOL (from clk_c)
ROUTE 2 1.905 IOL_T18A.INFF to R11C19C.A0 multiplicandreg_0
CTOF_DEL --- 0.265 R11C19C.A0 to R11C19C.F0 SLICE_61
ROUTE 1 1.547 R11C19C.F0 to R12C19A.C1 adderin_1
C1TOFCO_DE --- 0.547 R12C19A.C1 to R12C19A.FCO SLICE_0
ROUTE 1 0.000 R12C19A.FCO to R12C19B.FCI product_nxt_cry_1
FCITOFCO_D --- 0.101 R12C19B.FCI to R12C19B.FCO SLICE_19
ROUTE 1 0.000 R12C19B.FCO to R12C19C.FCI product_nxt_cry_3
FCITOFCO_D --- 0.101 R12C19C.FCI to R12C19C.FCO SLICE_18
ROUTE 1 0.000 R12C19C.FCO to R12C19D.FCI product_nxt_cry_5
FCITOFCO_D --- 0.101 R12C19D.FCI to R12C19D.FCO SLICE_17
ROUTE 1 0.000 R12C19D.FCO to R12C20A.FCI product_nxt_cry_7
FCITOFCO_D --- 0.101 R12C20A.FCI to R12C20A.FCO SLICE_16
ROUTE 1 0.000 R12C20A.FCO to R12C20B.FCI product_nxt_cry_9
FCITOFCO_D --- 0.101 R12C20B.FCI to R12C20B.FCO SLICE_15
ROUTE 1 0.000 R12C20B.FCO to R12C20C.FCI
product_nxt_cry_11
FCITOFCO_D --- 0.101 R12C20C.FCI to R12C20C.FCO SLICE_14
ROUTE 1 0.000 R12C20C.FCO to R12C20D.FCI
product_nxt_cry_13
FCITOFCO_D --- 0.101 R12C20D.FCI to R12C20D.FCO SLICE_13
ROUTE 1 0.000 R12C20D.FCO to R12C21A.FCI
product_nxt_cry_15
FCITOFCO_D --- 0.101 R12C21A.FCI to R12C21A.FCO SLICE_12
ROUTE 1 0.000 R12C21A.FCO to R12C21B.FCI
product_nxt_cry_17
FCITOFCO_D --- 0.101 R12C21B.FCI to R12C21B.FCO SLICE_11
ROUTE 1 0.000 R12C21B.FCO to R12C21C.FCI
product_nxt_cry_19
FCITOFCO_D --- 0.101 R12C21C.FCI to R12C21C.FCO SLICE_10
ROUTE 1 0.000 R12C21C.FCO to R12C21D.FCI
product_nxt_cry_21
FCITOFCO_D --- 0.101 R12C21D.FCI to R12C21D.FCO SLICE_9
ROUTE 1 0.000 R12C21D.FCO to R12C22A.FCI
product_nxt_cry_23
FCITOFCO_D --- 0.101 R12C22A.FCI to R12C22A.FCO SLICE_8
ROUTE 1 0.000 R12C22A.FCO to R12C22B.FCI
product_nxt_cry_25
FCITOFCO_D --- 0.101 R12C22B.FCI to R12C22B.FCO SLICE_7
ROUTE 1 0.000 R12C22B.FCO to R12C22C.FCI
product_nxt_cry_27
FCITOFCO_D --- 0.101 R12C22C.FCI to R12C22C.FCO SLICE_6
ROUTE 1 0.000 R12C22C.FCO to R12C22D.FCI
product_nxt_cry_29
FCITOFCO_D --- 0.101 R12C22D.FCI to R12C22D.FCO SLICE_5
ROUTE 1 0.000 R12C22D.FCO to R12C23A.FCI
product_nxt_cry_31
TLATCH_DEL --- 0.860 R12C23A.FCI to R12C23A.Q0 SLICE_4
ROUTE 1 1.051 R12C23A.Q0 to R9C22C.C0 product_nxt_62
CTOF_DEL --- 0.265 R9C22C.C0 to R9C22C.F0 SLICE_52
ROUTE 1 0.000 R9C22C.F0 to R9C22C.DI0 product_6_62
(to clk_c)
--------
8.345 (46.0% logic, 54.0% route), 20 logic levels.
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