I've been wondering about this. A multiplier isn't exactly unusual,
I would think that someone figured out the optimum logic decades ago?
The real problem that that there is not really an "optimal" design.
Every
application requires different amounts of speed, layout size, and power
consumption, so there are different designs that optimize different
variables.
And of course it is not always best to have "the fastest design", since
that
will most likely end up wasting huge amounts of resources. The result is
a continuum of size vs speed.
To read more about multiplication in FPGAs, this is the best source I
have
found. It is very readable and goes into a lot of depth:
http://www.fpga-guru.com/multipli.htm
I am, however, surprised at the limited number of reference designs in
the open domain that are easily accessed. It seems like there are only
so
many ways people would bother to implement a 32x32 multiplier, and
it should be quite easy to make a configurable one based on the size of
each parallel computation (e.g. the number of times to run through
serially).
nick
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