On 11/29/07, John Griessen <[EMAIL PROTECTED]> wrote:
> James Richard Tyrer wrote:
>
> > IIUC, we have a clock generator for the pixel clock -- meaning that the
> > frequency will have to be changed for different formats, but while
> > running it will have a constant frequency.  But, both channels will have
> > different frequency.
> >
> > On the surface of this, it appears that you don't need to use a new
> > clock generator, but rather de-jitter the pixel clocks which you have.
> >
> > On the surface of this, it appears that a PLL for each channel would do
> > this.
>
> Yes, I made a comment about this that got silence... maybe I used

Sorry.  I think I saw that and just forwarded it to Howard.  I did
that with a lot of emails.

> some unknown lingo...   If the 900 ps
> of randomness is longer than the clock period, you would need a 2 bit fifo
> on each PLL input also...and that could easily be made in the FPGA...

The problem with the jitter is what it does on the monitor.  For
analog, it makes the pixels wiggle.  For DVI, you get clock and
sampling problems in the receiver.

>
> Oh... if that kind of delay was needed, you might need it in other places too,
> to keep data and clocks aligned...
>
> Which brings up the question, "Is there an earlier spot in the signal flow
> you could dejitter, so as to avoid the need for many fifos, with their outputs
> aligned to the PLL clock.

The crystal has negligable jitter.  It's the DCM in the Xilinx chip
that's introducing all of the noise.  A lot of it comes from ground
bounce and crosstalk from other activity in the FPGA.  We actually
first figured this out when we were getting memory errors, because its
clock is being driven by a DCM also, and the memory chips couldn't
handle the jitter.

> Killing unwanted randomness early is always best.
>
> John Griessen
>
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-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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