James Richard Tyrer wrote:
IIUC, we have a clock generator for the pixel clock -- meaning that the
frequency will have to be changed for different formats, but while
running it will have a constant frequency. But, both channels will have
different frequency.
On the surface of this, it appears that you don't need to use a new
clock generator, but rather de-jitter the pixel clocks which you have.
On the surface of this, it appears that a PLL for each channel would do
this.
Yes, I made a comment about this that got silence... maybe I used
some unknown lingo... If the 900 ps
of randomness is longer than the clock period, you would need a 2 bit fifo
on each PLL input also...and that could easily be made in the FPGA...
Oh... if that kind of delay was needed, you might need it in other places too,
to keep data and clocks aligned...
Which brings up the question, "Is there an earlier spot in the signal flow
you could dejitter, so as to avoid the need for many fifos, with their outputs
aligned to the PLL clock.
Killing unwanted randomness early is always best.
John Griessen
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