> I have came across custom SOCs where there is a single ARM Coresight DAP and > a riscv processor connected on APB bus on a particular APB port.
Do you happen to mean the WCH CH32VXXX MCUs by any chance? If so then maybe this is of relevance? * https://github.com/fxsheep/openocd_wchlink-rv/issues/1 * https://github.com/openwch/openocd_wch I seem to recall other discussion of this recently (last year) but can't find anything via a quick search of the mailing lists. --- **[tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Wed Jan 10, 2024 12:57 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
