Though this is a off-topic. I have got some queries hence posting I have came across custom SOCs where there is a single ARM Coresight DAP and a riscv processor connected on APB bus on a particular APB port. ARM debug can be achieved using openocd, any idea on how riscv debug can be achieved here ? As there is no separate riscv tap how to ask openocd to look for riscv debug registers from a particular APB port and base address ?
Cinly, from your comment it looks like this type of functionality is not supported in openocd but i have seen a separate version of openocd-riscv. Apparently that is helping to attach to ARM core as well, is there any way to debug riscv with that version in this scenario ? I see some custom debuggers does support this type if debug but that all are license and paid basis. --- **[tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Thu Mar 09, 2023 11:08 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
