On 01:08 PM 14/03/2001 -03-30, Fabian Hartery said:
>Hi Everyone,
>I have some real strange behavior going on with the dreaded hidden pins.
>These are being assigned sub-nets and are showing global netlist behavior
>where none exists. That means, a floating terminal of part 1, pin 2, is
>shown associated with pin 2 of part 2. I would have suspected that a parts
>definitions are held in a 'local' definition and not a global one. I can't
>see  an applicable rule affecting this, unless there is a rub in the
>protocol of creating a netlist.

Hidden pins always imply global connectivity (same as power objects).  You 
can't change it - all you can do is never use hidden pins and make your 
life easier and better documented.

Regular readers will know that I am being very constrained as this whole 
hidden pin thing is one of my *major* hates.  It traps new users over and 
over again. As I have said before all of Protel's vaunted ISO9000 libraries 
use hidden pins so what chance of there being a change to their 
behavior?  But I do think that the tide is turning and Protel would do well 
to take note - hidden pin connectivity should be an option and should be 
OFF for new installations.  They can then deal with the whole library issue 
with copious notes, warnings, erc errors and humble apologies grovelling 
all the time while whipping one-self with a birch and bellowing "I have 
sinned. Hidden pin connectivity is a crime against humanity."

>I can also report that parts created with multilayer pinning create keep out
>zone for components on both sides of the pwb. This means for example, you
>cannot place a coupling cap underneath a DIP part without encountering a DRC
>component spacing error. At least, that is what I have found. There is a
>difference in keep out zone Protel assumes and ones you can actually edit.
>This is very much a shortcoming.

This one can be fixed.

In the Placement design rules have a look at you component placement rules 
and I bet you will see they are set for a "quick" check.  if you change the 
check from Quick to either Multi-layer of Full you will not get errors as 
you describe.  So a bottom side surface mount component will not be flagged 
as fouling with a top side through-hole component and visa-versa.

Ian Wilson

>Guigne International Limited
>Paradise, Newfoundland

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
* To join or leave this list visit:
* http://www.techservinc.com/protelusers/subscrib.html
*                      - or email -
* mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum
* Contact the list manager:
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to