It really is a matter of preference.
We show ALL power pins and do not use hidden pins at all.
This includes 256 pin PGAs etc.
A suffering engineer is one who cannot decipher the different 3.3v, 5v, 12v,
agnd, dig gnd pins on an IC on a circuit diagram because the schematic
drawer did not think they were necessary.
The schematic writer , of course, does not probably use it for servicing later on.
Others do.

If you only have 5v and gnd for a large digital circuit then there may be an
argument for hidden power pins, otherwise
it's horses for courses and personal preference.


Regards,
Chris Mogford  CAD/CAM Specialist
Varian Australia,
Melbourne, Australia

p.s.
A nand sr gate looks great with power pins and bypass caps.
And I just luv those microcontrollers fully pinned in all their glory.
Reminds me.......
Ah,   but that's another story.


----- Original Message -----
From: "Terry Harris" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, December 07, 2001 3:02 PM
Subject: Re: [PEDA] Using Multiple Vcc for same part


> On Thu, 6 Dec 2001 16:22:34 -0800, Dwight wrote:
>
> >PERSONALLY, I don't find a couple extra pins per IC that cluttering.
>
> But what about gates, what does a nand SR latch look like with power pins?
> Or big chips which might have 40 power pins?
>
> >I also
> >find it easier to have the power net listed there than having to flip to
> >another page (especially since that "flipping" is usually on a pdf file!).
> >HOWEVER, much of this stuff IS personal preference -- to each his own!
>
> Unless you are the only one who is ever going to see the schematic I
> disagree. Schematics distributed with products may have to be read by
> hundreds or thousands of engineers for many years to come.
>
> Someone screwing up netlist generation a couple of times because they
> didn't understand or check hidden power connections is not a good excuse
> for making all those engineers suffer.
>
>
> Cheers, Terry.

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