In use Hyperlynx line sim  to calculate impedance from stackup, trace width,
copper thickness, plating thickness, dielectric constant.  There are good
write-ups with tables/equations in the LVDS section of the national semi
website.

Regarding Advanced circuits:   I believe I have read something to the
effedct that they do not necessarily follow your stackup (prepreg/core width
definitions)  Yuo should contact them and get a recommended stackup, and
verification that they will manufacture to that stackup.

Mike

-----Original Message-----
From: rimas [mailto:[EMAIL PROTECTED]]
Sent: Monday, March 04, 2002 7:07 PM
To: Protel EDA Forum
Subject: [PEDA] controlled impedance traces ?


hi there,

i suppose this question doesn't have to do with protel specifically, but i
was hoping someone could answer it for me or at least point me in the right
direction.  (i'm not a full time PCB layout person by the way)  i'm
presently laying out a board with a big xilinx fpga and a gigabit ethernet
phy chip on it.  the datasheet for the gigabit chip says that the
connections between chips need to be done with 50 ohm impedance
traces.  how do i calculate the impedance of a trace ?  it seems like trace
width and stackup order are the only two variables i have to play with.  i
am planning to have protos of this board made by advanced circuits, in case
that makes any difference.

thanks for any help,

-rimas

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