Rimas, Protel's stackup manager in conjunction with the signal integrity tools work as well as any tools I have seen on the market including Hyperlink. If you are not familiar with all of the issues regarding controlled impedance, I recommend using a high end shop as several other users have suggested. so that they follow your stackup. Talk with them first and get a recommended stackup if necessary. By definition controlled impedance means that the path must follow a "constant media". Lee Richie and several others have written many good articles regarding do and donts. Here are some common sense things I have picked up from reading their articles
Do reference all controlled impedance lines to a plane. Do not reference controlled impedance lines to other signals Do not attempt to use broadside coupled traces for controlled impedance because of misregistration between layers. Route diff traces next to each other but you do not have to route for diff impedance. I could spend the rest of the afternoon on this subject but I wont. Lee Richie wrote an article on this on I concur with his article why diff routing is required but diff impedance in not required. Do not run split planes under controlled impedance traces, remember it has to be a constant media. For Gigi bit speeds you might consider using a substrate with a lower DK. We have used both poylimide and Nelco 7000-13 for gigabit rates. Talk to your board house Ideally no vias, but in an imperfect world, use the min of vias, better yet you might consider blind and buried vias because of they inherently have less capacitance. You can travel layer to layer with the same impedance but the reference must remain the same i.e. if you ref gnd for layer 1 then drop to layer 3 gnd must follow as the reference plane. Controlled impedance boards may require many layers for gigabit systems, we often design 18 -24 layers, half of them are planes. Internal signal layers must be 1/2 oz copper for controlled impedance, ( this is because the fabrication difficulty etching a straight edge on 1 oz copper) Again I will skip all of the details Most likely you will not be able to achieve anything greater than 60 ohms on internal traces on a multilayer board. It can be done but with very awkward and unbalanced stackups. Go to pcdmag.com online and search their archives for articles, they have addressed many of these issues from time to time with some good and some not so good writers. Hope this helps Mike Reagan EDSI Frederick MD > i suppose this question doesn't have to do with protel specifically, but i > was hoping someone could answer it for me or at least point me in the right > direction. (i'm not a full time PCB layout person by the way) i'm > presently laying out a board with a big xilinx fpga and a gigabit ethernet > phy chip on it. the datasheet for the gigabit chip says that the > connections between chips need to be done with 50 ohm impedance > traces. how do i calculate the impedance of a trace ? it seems like trace > width and stackup order are the only two variables i have to play with. i > am planning to have protos of this board made by advanced circuits, in case > that makes any difference. > > thanks for any help, > > -rimas > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
