Hello,
The previous posts are great advice on this topic. My experience with my current employer and the board house we recommend has been that I add detailed notes to my fab drawing for the layer controlled impedance(s), and reference the entire stackup. Close calculations during the design and not forbidding a trusted board house to use its resources gives me better than my specified 10% tolerance, every time. Cheers! Drew ----- Original Message ----- From: "rimas" Sent: Monday, March 04, 2002 7:07 PM > hi there, > > i suppose this question doesn't have to do with protel specifically, but i > was hoping someone could answer it for me or at least point me in the right > direction. (i'm not a full time PCB layout person by the way) i'm > presently laying out a board with a big xilinx fpga and a gigabit ethernet > phy chip on it. the datasheet for the gigabit chip says that the > connections between chips need to be done with 50 ohm impedance > traces. how do i calculate the impedance of a trace ? it seems like trace > width and stackup order are the only two variables i have to play with. i > am planning to have protos of this board made by advanced circuits, in case > that makes any difference. > > thanks for any help, > > -rimas > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
