If you set the track size to a larger value the pours take less time.
Also make the trace larger than the grid and pour vertical (or horizontal)
hatch only.
i.e.  24mil track width  20mil grid size 
This is faster since the polygon does not have to generate horizontal and
vertical.

If the outer layers literally have no signal traces, then use a ground plane
layer ( make sure unconnected pads mid layer pads box is checked in gerber
layer setup).  Years ago, (pre 99SE) I merged a ground plane and top layer
for an RF board.  I had to manually place clearances (tracks) on the plane
layer for any tracks on the top layer.  Then I made notes for the board
house to do the merging when they generated the artwork.  You might be able
to do it yourself with Camtastic (just guessing) or some other Gerber
editor.

Duane

-----Original Message-----
From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 30, 2002 4:33 PM
To: Protel EDA Forum
Subject: [PEDA] Copper pours on outer layers


Question to smartest of smartest designers out there:

Here is the delima,   we have a board appox 24 x 30  ( a very large
backplane) , many thousands of connections, every layer controlled
impedance.  The boards are used for high speed  tele comminications
switching and data monitoring.  ( No the the tele com industry is not dead).
The designs are as many as 28 layers, some approching .250 inch in
thickness,  a very expensive baord to design and manufacture.

On the outer layers we avoid placing traces, since we embed the entire
design,  The outer layer are  copper pours tied to gnd  to reduce EMI and to
maintain controlled Z on the next inner layer.  The copper is poured on both
the  top and bottom layers.

Copper pours of this size are poured last because they are time consuming.
The pours can take 4 hours, and even longer if they are not right the first
time.  Question to any of the best out there.....can we avoid a copper pour
and merge a gnd layer to the top?  Does anyone have a method or suggestion
to merge copper to flood the top layer.     Is there a quicker method?   We
are using 99SE on aa 1 gig cpu with 512 meg.

Mike Reagan
EDSI


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