I don't work on boards as  _humongous_  as yours but have done similar on a
smaller scale.   Here are a few suggestions:

(1) Break up your pour into many smaller "tiles" so that any later rework
can be completed with just a local re-pour on one of the tiles.    Its
pretty easy to repour a bunch of polys in a batch: select the polys you
want, exec MOVE SELECTION but don't move any thing at all, and say YES to

(2) Disable any un-needed design rules before you pour.   The time a pour
takes increases logarithmicly with the number of design rules (or so it
seemed to me).

I don't know how one might be able to merge another copper layer with
top/bottom copper.

Initially I was thinking an internal plane layer could be used for this.
I think you could manage to get the proper artwork on the internal plane
layer easy enough.   The solder mask layer could be exported and imported
to an internal plane which would give you the oversize pads of the required
clearance.   Unfortunately, when you were done you would have a negative,
not a positive image.   The gerber of the internal plane is negative too
which doesn't help.   If you had another program (GCprevue??) to change the
internal plane to positive image it might just work.   Then you could just
paste it right on the top/bottom copper layers.    Sounds kind of messy and
tedious to me.

Good luck
Dave Lewis

"Michael Reagan (EDSI)" <[EMAIL PROTECTED]> on 07/30/2002 04:33:02 PM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:    "Protel EDA Forum" <[EMAIL PROTECTED]>

Subject:  [PEDA] Copper pours on outer layers

Question to smartest of smartest designers out there:

Here is the delima,   we have a board appox 24 x 30  ( a very large
backplane) , many thousands of connections, every layer controlled
impedance.  The boards are used for high speed  tele comminications
switching and data monitoring.  ( No the the tele com industry is not
The designs are as many as 28 layers, some approching .250 inch in
thickness,  a very expensive baord to design and manufacture.

On the outer layers we avoid placing traces, since we embed the entire
design,  The outer layer are  copper pours tied to gnd  to reduce EMI and
maintain controlled Z on the next inner layer.  The copper is poured on
the  top and bottom layers.

Copper pours of this size are poured last because they are time consuming.
The pours can take 4 hours, and even longer if they are not right the first
time.  Question to any of the best out there.....can we avoid a copper pour
and merge a gnd layer to the top?  Does anyone have a method or suggestion
to merge copper to flood the top layer.     Is there a quicker method?   We
are using 99SE on aa 1 gig cpu with 512 meg.

Mike Reagan

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