On 02:50 PM 30/07/2002 -0700, Duane Foster said:
>If you set the track size to a larger value the pours take less time.
>Also make the trace larger than the grid and pour vertical (or horizontal)
>hatch only.
>i.e.  24mil track width  20mil grid size
>This is faster since the polygon does not have to generate horizontal and
>vertical.
>
>If the outer layers literally have no signal traces, then use a ground plane
>layer ( make sure unconnected pads mid layer pads box is checked in gerber
>layer setup).  Years ago, (pre 99SE) I merged a ground plane and top layer
>for an RF board.  I had to manually place clearances (tracks) on the plane
>layer for any tracks on the top layer.  Then I made notes for the board
>house to do the merging when they generated the artwork.  You might be able
>to do it yourself with Camtastic (just guessing) or some other Gerber
>editor.
>
>Duane

I have done the positive/negative merge thing as well - though typically on 
smaller RF boards.  I have tried to stay away from them for years, since 
Protel really sped up pours compared to the glacial pours in PCB V3.

As Duane says placing the clearance tracks on the plane layer is a pain but 
necessary.  It is a nuisance during re-work.  You loose a fair bit of DRC 
functionality as well.

If the outer layer has few tracks and not many components then this may be 
manageable.

One issue that does come up.  Protel does not put a copper annulus around 
the holes on plane layers (for vias/pads that do not connect to the 
plane).  many board manufacturers do not liking boards with no copper 
annulus on the outer layers.  This is not an issue when you are doing a 
merge as the positive signal layer can provide the annuli, but is a problem 
when you simply specify the plane be the outer layer.

In either case, you need to be careful with the design rules as Protel 
provides clearance on plane layers based on a clearance from the hole - you 
have to make sure you oversize this plane clearance enough to allow for the 
annuli.

One other thing I have found - make the plane to annuli clearance and the 
clearance from tracks to the plane (by placing suitably oversized tracks on 
the plane layer) quite large.  I have observed an increase in shorts from 
the plane to tracks and vias annuli when there is sooo much copper 
nearby.  I work on a 20 mil plane clearance, sometimes more.

Merging is messy, easy to stuff up, lots to remember, hard to maintain, 
doesn't DRC as well...but apart from that it does work if you are careful 
and have reasonable knowledge of the PCB manufacturing requirements.

Ian Wilson


>-----Original Message-----
>From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED]]
>Sent: Tuesday, July 30, 2002 4:33 PM
>To: Protel EDA Forum
>Subject: [PEDA] Copper pours on outer layers
>
>
>Question to smartest of smartest designers out there:
>
>Here is the delima,   we have a board appox 24 x 30  ( a very large
>backplane) , many thousands of connections, every layer controlled
>impedance.  The boards are used for high speed  tele comminications
>switching and data monitoring.  ( No the the tele com industry is not dead).
>The designs are as many as 28 layers, some approching .250 inch in
>thickness,  a very expensive baord to design and manufacture.
>
>On the outer layers we avoid placing traces, since we embed the entire
>design,  The outer layer are  copper pours tied to gnd  to reduce EMI and to
>maintain controlled Z on the next inner layer.  The copper is poured on both
>the  top and bottom layers.
>
>Copper pours of this size are poured last because they are time consuming.
>The pours can take 4 hours, and even longer if they are not right the first
>time.  Question to any of the best out there.....can we avoid a copper pour
>and merge a gnd layer to the top?  Does anyone have a method or suggestion
>to merge copper to flood the top layer.     Is there a quicker method?   We
>are using 99SE on aa 1 gig cpu with 512 meg.
>
>Mike Reagan
>EDSI


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