Whatever you do, IMO don't hide those power pins. To do so will only bite you later.
I usually take the Protel SCH library part (CMOS, TTL, etc.) and copy it to my own library. Then I unhide the power pins. I show them on one of the multi-part parts. It does add to the clutter, but it helps prevent mistakes. When you give schematics to a tech, they need to see explicit power pin connections, otherwise they don't know where to probe. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com ----- Original Message ----- From: "Shawn" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Friday, August 02, 2002 1:09 PM Subject: Re: [PEDA] OT Metric vs Imperial > I need some opinions/help. > > What is the best was to design the power pins (VCC, VEE, GND, etc) on a > multi-part schematic symbol for, say, a hex inverter. Seems if they are > hidden they can get missed, but if they stick out they clutter the > schematic. > > -Shawn > > > ************************************************************************ > * Tracking #: 7EE15401909040488DE1A886F078BCB5E57A7F9C > * > ************************************************************************ > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
