Hello,

There's two schools of thought on this one, ie. those who DO use hidden
pins and those who DON'T.   I subscribe very enthusiasticly to the former.

I build all my mulit-part IC's with an extra section just for power pins.
That allows great placement flexibility (any gate in any orientation) and
dramatically reduces the amount of editing needed if later during PCB
layout I decide to swap gates around.    Swapping gates only requires
changing the "letter" which is real easy.

I _never_ use hidden pins since I work on multi bias and ground circuits.
I always want to see what power and ground is connected to each and every
IC and I always place power pins on one of the gates.    I don't consider
any of this clutter but important design information which needs to be
displayed on the schematic.

Regards
Dave Lewis







"Shawn" <[EMAIL PROTECTED]> on 08/02/2002 10:09:23 AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:    "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:

Subject:  Re: [PEDA] OT Metric vs Imperial


I need some opinions/help.

What is the best was to design the power pins (VCC, VEE, GND, etc) on a
multi-part schematic symbol for, say, a hex inverter. Seems if they are
hidden they can get missed, but if they stick out they clutter the
schematic.

-Shawn


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