Hi, Running a Protel schematic through the rules checker before going anywhere near the PCB layout (or SPICE for that matter) is a very good idea. Protel may do this automatically when you create a netlist, but check all the option settings to make sure it does what you want. Rule checking can often turn up unconnected pins, net-to-net shorts, nets that don't go anywhere, outputs connected to other outputs, etc, etc. You may have to do a little more work setting up the schematic symbols (especially when using programmable devices like the Xilinx FPGA - you'll need to create or modify your own FPGA schematic symbol showing which pins are inputs, outputs, tri-state busses, power pins, etc..).
SPICE and/or logic simulations I would reserve only for key areas of circuit that require them - simulating an entire board can be extremely time consuming. Hopefully most simulation was done in the design phase before the final schematic is generated. good luck, Mark Harrison Bionic Ear Institute Melbourne, Australia > -----Original Message----- > From: Anand Kulkarni [mailto:[EMAIL PROTECTED]] > Sent: Tuesday, August 27, 2002 6:22 AM > To: PROTEL USER Group > Subject: [PEDA] (No Subject) > > > Hi all, > I am currently designing a printed circuit board in which the > main part is a XILINX FPGA. > > What I want to know is: (please read on) > > Upon completion of the schematics of the board design > do PCB designers do anything to verify the correctness of the board > schematics ....like simulation ? > > Especially where something complex like a XILINX FPGA is involved. > > -------------------OR-------------------- > > do PCB designers simply trust the correctness of the > schematic and proceed with PCB placement and routing ? > > In short ,is any board-level simulation (involving SPICE > models or something similar) done before fabrication of the board ? > > please do reply, > thanks and regards, > > Anand Kulkarni > ************************************************************************ * Tracking #: 4D13509BC982C543A0B89D9C713C4ADD48FB286E * ************************************************************************ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
