Rene Tschaggelar wrote:

> I recently had a look into the subject of FPGA and Protel.
> I was told the FPGA router is still taken from the manufacturer
> (in your case XILINX).
> Meaning you're just using Protel to draw the schematics and
> send the netlist to the other tool doing the FPGA. These
> tools from various manufacturers are free available on the net.
> Since the programming interface is also in that manufacturer
> tool, I tend to fail recognizing the advantage of having Protel
> drawing the schematic.

Have you ever used one of the Aldec-based FPGA tools?  That is
what Xilinx used as the sch-> (x)HDL section of their tools.
The very old one was bad, then last version they used had improved
to passable.  Then, they replaced the Aldec schematic entry with
their own program.  It is abominable!  It is almost always necessary
to erase a net to move a wire, or even relabel a net in many cases.
Truly the worst schematic entry program I've ever seen!

Protel 99SE schematic entry is so many light years ahead of Xilinx,
it is like comparing programming minicomputers through the console
switches to C++.

Yes, using an external sch editor would be more keystrokes, chance
of error, etc.  But, when it takes half an hour to change one signal name,
the extra effort would be minute.  Apparently, there is a large EDA
manager as the 'front panel' of the Xilinx tools, and you can splice in
scripts to use external editors, library managers and sch->HDL
compilers.  Now that I know that Protel fixed the Xilinx FPGA
translator bug in 99SE SP5, I will have to try this out on the next project.

> One advantage of not having the FPGA in protel is :
> The FPGA is a chip with pins and its internal is hidden.
> This allows the FPGA, in the EEPROM-type case to act as copy
> protection.
> Further, you won't have the library of functions that the XILINX
> tool offers.

The sch. library for most FPGAs are pretty public, and I think Protel
already has them.  There were problems in some of the schematic level
versions of this, years ago, but I think the pre-compiled macros are

> I admittedly never tried the FPGA feature of Protel.

I did.  In the abstract, it seemed to work quite well.  When I went to
compile for specific Xilinx chips, things went bad.  The Protel digital
simulator is also pretty nice and fast to use (minimal keystrokes).  The
latest Xilinx simulator won't let you graphically edit timing diagrams.
You have to compile a VHDL testbench as ASCII text every time you
want to move an edge!  I mean, what a step BACKWARDS!  These guys
are still in the IBM punch-card, mainframe batch processing mindset!


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