Hi, There is a new version of 1020-pin BGA routing test for "checking" at :) http://groups.yahoo.com/group/protel-users/files/junk/
please tell me that this is OK? ;) or tell me how to manage this damn chip :) Used layers are TOP, MID1, MID2 and BOT (BOT layer is not routed yet...) so I think it can be done with 4 signal layers (maybe not all signal pads but many of them), there will be 4 layers for power planes 2*GND and 2*POWER (planned 8 layer board) -Juha Pajunen -----Original Message----- From: Juha Pajunen [mailto:[EMAIL PROTECTED]] Sent: 1. lokakuuta 2002 9:43 To: Protel EDA Forum Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add) Here is link for device package itself... http://www.altera.com/support/devices/packaging/specifications/pkg-pin/pdf/1 020-FBGA_Therm.pdf here is link for the pin-out files... http://www.altera.com/literature/lit-dp.html#stratix here is link for the chip... http://www.altera.com/literature/ds/ds_stx.pdf' -Juha Pajunen -----Original Message----- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: 1. lokakuuta 2002 5:19 To: Protel EDA Forum Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add) Is there an actual datasheet for the specific device you are using? Can you provide a Mfg and PN, and possibly a link? It would help alot in seeing what you need. Thanks, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
