I have been able to spend a little time and look at your rev 3 of your
"junk" layout.

I think you are on top of it, and have a good grasp of what you need to do.

It is unfortunate that you cannot use what you have already done, but it is
on a spacing of .040" instead of the required 1.00mm, which has a cumulative
error of just under 20 mil (one half of a ball grid placement) built in from
one side of the device to the other, which renders it totally unusable for
anything but a routing guide. I would recommend that you play around with a
few different track widths and spacings, probably based on increments of
Protels 0.025mm grid, until you come up with something a little more
efficient for the metric requirement. an example might be 4 mil lines on
0.125mm spacing , which will fit quite nicely into your current scheme of 16
mil pads on 1.00mm centers. You can always change the track width and the
spacing grid once you get out beyond the perimeter of the device. If you can
tolerate a little smaller track and tighter spacing (0.6 mil less on each),
then go 0.1mm tracks with 0.1mm spacing. Actually, there is nothing wrong
with the 4 mil track and 4 mil gap that you have now, except it is a little
hard to locate on a metric grid. One of the things that you have to be very
careful about here, is understanding the exact minimum resolution of the
photoplotter that you will be using to generate your film for the board,
since it may not be able to resolve down to 0.025mm or 0.1 mil, which would
mean you are in real trouble if you were using those numbers as placement
increments or feature increments, only to have the photoplotter round up or
down to the next mil or whatever, and totally trash all of your perfectly
worked out spacing. Best to check on what is available from various board
shops before you try to design something that they will only screw up when
they go to produce it.

One thing that I would recommend is that you make a separate "footprint", or
"component" of your "routing" (almost like you have already done, except
make it a "component"), which should include all of your vias associated
with the BGA, so that you can work on it separately, and "update" the board
as necessary until you get it all the way you want it. You can use the
"Update Free Primitives from Component Pads" feature under the "Menu" in the
"Netlist Manager" to define the nets (assign the nets to the traces) that
are associated with the routing inside this special "routing" component,
until the point where you are happy with everything and then you can
"release" all of the "primitives" of this special "routing" component into
the design (where they will become just like any other trace or via).

One thing that I believe that you may have overlooked, is the routing of
such things as the PLL's. You have all of the traces for all of the PLL's
hooked up, so I can only assume that you are going to use them, and while
you may not actually be using all 10 of them, I will operate on the
assumption that you are at least going to use some of them. The PLL's are
placed where they are on the chip because they need very good power
distribution along with very good decoupling. Many of them are on the outer
edge of the chip where you can get to the PLL power and ground pins directly
and bypass them with a capacitor or two right at the pins, and also bring
out the CLK output of each PLL pretty much in the in the open where it can
be routed away from other signals. If you will notice, those PLL's which are
in the internal area of the BGA are placed right along the "via gap" on the
center line of the chip, here again, so that the so that the supply pins can
be directly accessed, and directly decoupled with a decoupling capacitor or
two (placed right there in the "via gap"), and also probably to give you
some more room to handle the output CLK line away from other signals. I am
afraid that you will not be able to handle the power and ground or output
for any of these PLL's simply as a 4 mil trace running next to other noisy
traces with only a 4 mil gap. You will undoubtedly have to run some larger
traces or "split planes" for the supply for each PLL that you use, and
obviously on a plane layer. But look at the bright side of things, although
you will have to place decoupling capacitors on the back of the board right
there in the "via gap" for each PLL you use, you can still use the internal
planes in that area for other routing (as you already have), and you will
also have less things to route in that area.

I would not try to hard to hold onto your current concept of 4 routing and 4
power planes. It may well be that you have to add a couple of analog planes
in the very center of your board to handle the PLL's, and possibly the VREF
supplies (I have not been able to figure out what they are used for yet, and
I am assuming that they may be something analog).

Also remember that you will need to place decoupling capacitors for the main
supply of the device in the "via gap" in the center of the device on the
bottom layer. Here you might also want to look at possibly making room for a
few more decoupling capacitors by combining adjacent power or ground pins
onto one via, and thereby eliminating another via or two, which can possibly
allow you to get in there with yet another capacitor or two. Before you do
this though, you might want to look at the total current requirements of the
device, and make sure you are not "overloading" any vias, current wise. If
you end up needing more capacitors on the back side than you really have
room for, then you may actually have to go to blind and buried vias just to
get some real estate for decoupling capacitors. One thing you also may want
to look at here, is that if you have a solid plane that runs completely
under the BGA, such as your VCCINT might require, you can handle a lot of
your decoupling requirements outside of the periphery of the BGA, providing
that you have a good solid plane and some room on the corners of the device.
Remember that any time you are using decoupling capacitors that you place on
the back of the board that is connected to a net that is using a "plane",
you are virtually decoupling the "plane" anyway (for the most part) since
the device is on the other side of the via with the plane attached in the
middle of the via.

I did see somewhere in one of the datasheets, that all of the LVDS I/O pins
are on the outer two rows on the left and right side of the chip, and I
believe that you did mention that you are going to use some LVDS. Just
remember that you will have to handle these lines as a differential pair
transmission lines and keep them away from each other and other lines as
well. While you could actually route these as individual transmission lines,
it would take up much much more space (since each line has to be isolated
from other lines). Remember that if you do use the LVDS lines configured for
LVDS, in addition to routing them as a pair, that they have to be controlled
impedance which requires that you have them over a ground plane at a
controlled height (controlled "stackup"), and once again, they need to be
properly terminated (see the ALTERA AN75 link I gave you earlier). It may
well be that there are other single ended impedance controlled lines that
you need to worry about, and also some analog lines or analog supplies or
areas that you are going to have to isolate and pay special attention to,
and since I have no idea of what they are, I can't very well help you with

The one thing that I can say, is that you need to take the time to read all
of the specific little requirements in the datasheet that affect the types
of design for the features of the chip that you are infact using in the
implementation of your specific design, because there is nothing worse than
getting towards the end of a complex design and discovering some simple
requirement that requires that you redo half of your layout - I know,
because I have been there. I also remember seeing several different ap notes
and articles and sections of the datasheet last night as I was browsing
around the ALTERS site, that seemed to cover a lot of their specific routing
requirements, and I would say that taking the time to read and understand
these things now, will be a good investment that will have immediate results
and repayment in this design, and may even mean the difference between
getting it right the first time and possibly even not having to do a few
more turns of the board. It really will pay for itself to take the time up
front to learn what you have to about this device.

Juha, one of these devices has 20 times the computing power of one of the
original ALTAIR or IMSAI 8080 microcomputers (I still have a few of each in
my basement), and they are totally programmable and configurable into just
about any kind of device that a person could possibly imagine, and I have
absolutely no idea or conception of what you are going to do with this
device in your design. It would take me a month to read the datasheet for
this monster and understand it, so it may well be that there are many other
"problem areas" lurking out there waiting to surprise you and become a
problem. I can't very well help you any more than I already have here in
these few posts, unless you have some specific questions about some specific
areas of the design, and possibly I can be of some further help to you
there, which I would be more than glad to do.

Anyway, as I said before, you seem to be on top of it, and I am sure that
you are going to come up with an excellent board in the end.

Let me know if I can be of any more help.


PS. Take my email address home with you, and that way you can ask me any
questions that pop up in the evening or on the weekend, and that may help
eleavate the time zone problem.

----- Original Message -----
From: "Juha Pajunen" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, October 01, 2002 6:16 AM
Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add)

> Hi,
> There is a new version of 1020-pin BGA routing test for "checking" at :)
> http://groups.yahoo.com/group/protel-users/files/junk/
> please tell me that this is OK? ;)
> or tell me how to manage this damn chip :)
> Used layers are TOP, MID1, MID2 and BOT
> (BOT layer is not routed yet...)
> so I think it can be done with 4 signal layers
> (maybe not all signal pads but many of them),
> there will be 4 layers for power planes
> 2*GND and 2*POWER (planned 8 layer board)
> -Juha Pajunen
> -----Original Message-----
> From: Juha Pajunen [mailto:[EMAIL PROTECTED]]
> Sent: 1. lokakuuta 2002 9:43
> To: Protel EDA Forum
> Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add)
> Here is link for device package itself...
> 020-FBGA_Therm.pdf
> here is link for the pin-out files...
> http://www.altera.com/literature/lit-dp.html#stratix
> here is link for the chip...
> http://www.altera.com/literature/ds/ds_stx.pdf'
> -Juha Pajunen
> -----Original Message-----
> From: JaMi Smith [mailto:[EMAIL PROTECTED]]
> Sent: 1. lokakuuta 2002 5:19
> To: Protel EDA Forum
> Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add)
> Is there an actual datasheet for the specific device you are using?
> Can you provide a Mfg and PN, and possibly a link?
> It would help alot in seeing what you need.
> Thanks, JaMi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
* Contact the list manager:
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to