Hi, I changed the footprint, 40mil pitch with 20mil pads. VIAs between SMD pad are 16mil pad and 8mil hole, we want use this because there will be more room for routing and SOLDERMASK is bigger between SMD pad and VIA (I have 4mil opening for SMD pads and VIAs are tentd or 0mil opening; which one is better). Traces are 4mil and gap is also 4mil, need to route two trace between SMD pads, do not want make over 10 layer board...
Should I use two powerplanes for FPGA core voltage, I/O voltage for FPGA (there is 8 bank, so we might need 8 different I/O voltages), VREF voltage for each bank (8 bank), 3.3V for memory and other chips... how to manage all those different voltages...??? How about making splitplanes on GNDplane for different "GNDs"? (memory, I/O, of cource there will be own GND splitplane for FPGA chip...???) JaMi wrote... >This will keep your vias as far as >possible from the actual BGA pad, and you want as much here as you can get. >This wili also allow you to use a bigger via (see below). Our VIAs are 16mil pad and 8mil hole, isn't this ok? The board size could be x=8000mil y=4900mil (do not know yet...) I am still intrestd in what kind of board stack up you GURUs recommend! -Jupa -----Original Message----- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: 27. syyskuuta 2002 22:03 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add) Juha, Just looked at your database. First, your vias are misplaced, and need to be exactly in the center of the opening between the pads, which appear to be on a 1mm grid, which means that you vias should be on a .5mm grid. This will keep your vias as far as possible from the actual BGA pad, and you want as much here as you can get. This wili also allow you to use a bigger via (see below). Secondly, you will possibly want a larger pad to drill ratio on your vias if at all possible, to prevent massive breakouts, which while acceptable by some standards. may be excessive with that current ratio. One of "routing" numbers being batted around by some board houses is somthing they call the "five fours", which is three 4 mil gaps with two 4 mil traces, all between a 20 mil pad with 10 mil holes for 40 mil spacing on a BGA. If your spacing on the BGA is actually 1mm, which is .03937 . . . , instead of 40 mil, then you have to slightly adjust the size of the pad, and everything else will fit. Even here you are gonig to possibly see breakout, which once again is allowable, providing that you are using "teardrops" for all of your pad entries. How big is your board anyway, overall size wise. The above numbers are based on "standard" alignment of all features within 5 mil, and unless your board is fairly large. everything seems to be very do-able with out too many layers, or the need to go to micro vias, or ever to blind or burried vias. JaMi ----- Original Message ----- From: "Juha Pajunen" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Friday, September 27, 2002 1:09 AM Subject: [PEDA] 1020-pin BGA out-routing question (some add) > Hi again, > > <> What is the best PCB layer stack for > this type of BGA? <> > > http://groups.yahoo.com/group/protel-users/files/junk/ > > There is 1020-pin 1mm pitch BGA. It would be very > pleasing to have some information and help how to > route that huge BGA. What are trace width and cap > between different tracks and so... > > It would be very nice if you couldedit that file > (how to route it) and then send it to me to this > addrss [EMAIL PROTECTED] > > I really need all useful information > about routing this BGA! :) > > > Sincerely, > Juha Pajunen, Hw Engineer > Bitboys Oy > E-mail: [EMAIL PROTECTED] > ------------ > NOTE: This message, and any attached files, may contain privileged or > confidential information. It is intended for use only by the designated > recipients. Any disclosure, copying or distribution of, or reliance upon, > this message by anyone else is strictly prohibited. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
