Juha,

First, sorry about the delay in responding, but the different time zones
make it hard to keep up. Secondly, I an certainly no guru on the subject,
but can only offer you a few things to think about as you approach this
board, and hopefully if someone out there knows better than I, they will
step in and offer better advice.

I have read both of your responses, and will try to combine all of my
responses here.

Ok, to start, why don't you see below,''

JaMi


----- Original Message -----
From: "Juha Pajunen" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, September 30, 2002 2:52 AM
Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add)


> Hi,
>
> I changed the footprint, 40mil pitch with 20mil pads.
> VIAs between SMD pad are 16mil pad and 8mil hole, we
> want use this because there will be more room for
> routing and SOLDERMASK is bigger between SMD pad
> and VIA (I have 4mil opening for SMD pads and VIAs
> are tentd or 0mil opening; which one is better).
> Traces are 4mil and gap is also 4mil,
> need to route two trace between SMD pads,
> do not want make over 10 layer board...
>

Do not change your spacing to .040" unless that is the actual spacing of
your device. I only offered that because it was used in a presentation that
I attended on the subject, but if I actually understand correctly, your BGA
is 1.00mm spacing (actually .03937" and not .04000"), and the cumulative
error would definitely cause a problem on a pattern this large. Stick with
what the databook calls for on the "pitch", and adjust everything else to
match that.

If you are using an 8 mil hole in a 16 mil pad, that requires a 8 mil
overall feature registration (.004" true position), which is pretty tight
for an 8 by 5 inch board, and that would allow zero for annular ring, which
is acceptable (for certain manufacturing specs), but forces you to use
teardrops on all of your vias. I would think that you would be much better
off tightening up your solder mask, and it's registration, and using the
extra "slop" (as it were) in the rest of the design. Even if you stuck with
the 8 mil hole, and kicked your pad up to 18 mils, but kept the same feature
registration, you could at least avoid breakouts. Anyway, something to think
about. Remember that Protel does allow you to remove "unused internal" pads
when you generate gerbers, but I would not want to depend on this for any
clearances (I would prefer to make a "special via" for the specific occasion
and location in which I "juggled the pad stack" (s it were), if I had a
"tight spot" or two and needed a little extra space. I will try and locate
the number of the IPC Spec that discusses "breakout" in this specific
situation.

Also remember that when you consider overall feature registration and
breakout, you also have to consider the effect on "plane clearance", and
remember that hole size is usually based on "final" hole size, after
plating, while the plane clearance itself has to take into account the max
drill size (including any etchback (if present)).

This brings up the related subject of thermals. The "via farm" under a BGA
usually has the effect of making "swiss cheese" out of any planes that run
under the BGA, and you have to be very careful about how you use "thermals"
here, because you can literally destroy any plane that is left after the
normal clearance for the tightly packed vias if you are not careful. Some
people demand the use of thermals under a BGA, regardless of the number of
perforations in the plane due to vias, in which case, I would say that you
need to be very very careful with the specific dimensions if the thermal
(make one specifically for use under the BGA if necessary) and make sure
that your final gerbers look OK before you ship them out and make the board.
My own opinion in this case, is to NOT use a thermal at all on the via, but
rather the connections to the plane "direct", and then make sure that the
trace that goes between the via and the actual BGA pad, is small enough (say
8 mils) that it acts as a "thermal relief" itself (in just the same manner
as if you have a surface mount pad on an outer layer that you had to isolate
from a plane (just as the "Polygon Plane" fill does)). This is usually
enough "thermal isolation" from the plane itself, to not affect the
soldering of the BGA, but you had better check with your assembly house (it
might require some special profiling) and get their approval on this one,
before you go this route, since I am sure that many people out there would
disagree with me on this point. With the trace between the via and pad at
about 8 mil, it will provide "thermal isolation" that is required for the
soldering operation, but at the same time it is short enough so that it does
not become too much of an inductor for those power and ground connections.
You might want some other opinions on this one.

Two traces per routing "channel" is very do-able, and respecting the actual
number of layers you will need, I can't help you there, as it will take what
ever it takes, and there is not too much that can be done about that.

The only remaining question is where did you get the 20 mil pad for the BGA
ball, as you don't just want to pick a number here because it sounds good.
What does the datasheet recommend?

> Should I use two power planes for FPGA core voltage,

Probably, if you can.

> I/O voltage for FPGA (there is 8 bank, so we might need
> 8 different I/O voltages), VREF voltage for each
> bank (8 bank), 3.3V for memory and other chips...
> how to manage all those different voltages...???
>

You are probably not going to need "8 different I/O voltages", but I have
seen times when an engineer wanted each "bank" to have it's own isolated and
decoupled supply, in which case you could accomplish this on one "split"
plane providing that the "splits" followed the contour of the "banks" of the
BGA.

You are probably not going to have to have any "VREF" or "Memory" voltages
directly under the BGA, so you can worry about them in their own little
corner of the board.

> How about making splitplanes on GNDplane for
> different "GNDs"? (memory, I/O, of cource there will be
> own GND splitplane for FPGA chip...???)
>

While you might need to "split" some of the "power" planes as discussed
above, but I would strongly discourage "splitting" any ground planes unless
you absolutely have to. Something very important to remember here, is that
you do not want to route any signals over (across) any "break" or "gap" in
any planes or "split planes", as this will most certainly introduce noise
into the supplies, and the design as a whole, since any "return currents"
that cannot cross over a gap in the plane will have to go all the way around
the gap, or split, back to the point where they are "common" (even if that
is off of the board back at the supply), and in doing so, they will "infect"
the supplies and planes with the "noise" of that signal.

It would probably be better for you to consider having at least two planes
that are solid ground just under the outer two signal layers, which could
serve as a good solid ground plane for any of the signals that have to
"cross over" any of the "splits" that may be necessary in other planes, such
as "power" planes. This may "blow" your total layer count, but it will
certainly keep your design much quieter. Here again you might want to
consult with your EMI / EMC / RF Engineers, if you have some, and you might
want to look for a couple of other opinions.

Respecting LVDS, which you do mention in the other email:

LVDS is an impedance controlled logic family, although depending on the
device, that impedance can vary, depending on whether you are driving the
LVDS through a ribbon cable or just driving across a PCB. Sometimes, with
some devices, it seems that these requirements can be pretty much ignored,
but I would doublecheck your datasheet, because I don't think that this
might be one of those times. I would expect that you probably need to handle
the LVDS lines as either individual 50 ohm impedance controlled transmission
lines, or 100 ohm differential impedance controlled transmission lines. It
is also quite possible, if not probable, that you will also need to
terminate those lines with terminating resistors, either to themselves, or
to a termination voltage. The datasheet will tell you what is required, and
if it is not specified in the specific individual datasheet for the specific
part that you are using, it may be that you need to consult the
manufacturers databook or website for the "logic family requirements" to
find out just what is required. For example, ECL devices require 50 ohm
impedance controlled transmission lines, for almost all of their individual
IC's, but you may not find those requirements defined on every single
datasheet, as they may be defined at the beginning of the databook. The same
may be happening here with your device and LVDS. You need to find out what
just exactly what is really needed.

That should be enough for now.

I am not quite sure of your time zone, but I would think that it is at least
mid afternoon there, and I hope that this will get to you before time to go
home,

JaMi

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