haven't had time to try your suggestions but I will. Here are some
answers to your questions.

        There is nothing weird about my hierarchy, 4 sheets (actually 3 with
one top sheet to tie the other 3 project sheets together) in a flat parallel
hierarchy. The top sheet has only sheet symbols  All connections between
sheets are made using nets (no ports in the sheets at all). I do this
regularly day in and day out with 2 sheets in this same manner. The
difference in these sheets is the number of nets that tie between sheets,
this project has approx. 50 cross sheet connections while my regular designs
may typically have more like 5 - 10.

1) Just ran the hierarchy report, what is this? It simply looks like a text
file of the explorer pane display, absolutely nothing else in the report.
2) Bom generates fine from the hierarchy, did extensive BOM work before
trying to port over to PCB.
3)Just tried the ASCII save. Saved each page as ASCII, moved the old .sch
files away into a folder, renamed the top  sheet symbols to open the new
ascii filenames. Closed the DDB. Opened the DDB. Generated the Update to a
new blank PCB, voila I got the exact same 14 net duplication errors that I
had previously. This is consistent at least. With the consistency I will be
able to get to the bottom of it I am sure.

        My suspicions are running towards off sheet objects. I just have to
set aside the time to fiddle.

        Generating the old fashion netlist and loading it did not generate
the same duplicate net errors. There were no duplicate net errors but there
were other errors using the old netlist method. The errors that showed up
with the netlist transfer did not show up with the synchronizer method. That
is scary, two methods give differing results. The errors resulted from the
manner in which we named a couple of components, with synchronizer these
were no problem, with netlist this naming screwed the netlist.

Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Norsat's Microwave Products Division has now achieved ISO 9001:2000

> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, October 03, 2002 11:18 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] P99SE SP6 Problem with Update PCB (Solved for the
> inte rim!)
> I wonder if there is a breakdown in the hierarchy of the 
> system rather than 
> the synch itself.
> Brad, does/did the hierarchy look OK?
> You can get a report on the hierarchy.
> Does this produce the expected result?
> What about BOM reports from the SCH?
> Are they OK?
> Does the problem persist after you save the Sch sheets as 
> ASCII and then 
> close and re-open?
> Does saving a particular sheet as ASCII and re-opening fix it (is the 
> problem related to one sheet)?
> I know you said the Netlist load seemed to work OK so some of 
> these next 
> ones may be pointless.
> Have you created a netlist and looked at it?
> When you create a netlist there is some options for tracing 
> the netlister 
> as it does its business.
> What do you see when you turn on tracing (and look at the reports)?
> Ian

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