why?
what is the relevance of this?
i've never really understood that 

Dennis Saputelli


Thomas wrote:
> 
> Do you have "Descend into sheet parts" ticked when running the synchroniser?
> 
> > -----Original Message-----
> > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, 28 November 2002 14:21
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] Connectivity Nightmares
> >
> >
> > >
> > > At 12:36 PM 28/11/02 +1000, you wrote:
> > > >Hi all:
> > > >
> > > >I usually use a hierarchical structure for my schematic
> > > documents, with a
> > > >main document with all the connectors on it, then below
> > that a block
> > > >diagram, and then the actual circuitry on one or more levels
> > > below that.
> > > >
> > > >I'm currently doing a reasonable-sized board, with lots of
> > > digital lines,
> > > >and have amalgamated those lines into busses for the most part,
> > >
> > > Are these busses made up from dissimilar nets - that is stuff
> > > like nRD,
> > > nWR, nCSRAM all being merged in to a bus called something like
> > > CONTROLS?  If so this won't work.  Protel can only cope with
> > > busses of the
> > > "standard" form eg D[7..0] and nets D7 down to D0.
> >
> > A mixture of both; however I'm having just as much trouble on
> > the data bus
> > (TR_D00..TR_D15) as I am on the control busses...
> >
> >
> >
> > Cheers,
> > MvdW
> >
> >
> > >

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