I always assumed It had to be checked for multi sheet hierarchical designs, so that the synchroniser would count all the sheets as one big netlist, and you know what they say about assumptions (they're the mother of all f@*kups). I was wrong.
What it really does is outlined on p132 of the Designers Handbook, "Model 5 - Using Sheet Parts to Create Hierarchy" Imagine you have a two pin daughter PCB you can place in a circuit, or alternatively you can install the components present on the daughter PCB directly onto the main PCB. Use a *component* to specify a sheet path to the daughter circuit, and when synchronising: 1) if you want to use the whole circuit on one PCB check the "Descend into sheet parts" box and all the component footprints present in the daughter PCB (component referenced sheet) will be used. or 2) if you want to use the daughter PCB module, uncheck the "Descend into sheet parts" box and a two pin footprint (for the daughter module) will be used instead. Clear as mud? > -----Original Message----- > From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 15:17 > To: Protel EDA Forum > Subject: Re: [PEDA] Connectivity Nightmares > > > why? > what is the relevance of this? > i've never really understood that > > Dennis Saputelli > > > Thomas wrote: > > > > Do you have "Descend into sheet parts" ticked when running > the synchroniser? > > > > > -----Original Message----- > > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > > > Sent: Thursday, 28 November 2002 14:21 > > > To: Protel EDA Forum > > > Subject: Re: [PEDA] Connectivity Nightmares > > > > > > > > > > > > > > At 12:36 PM 28/11/02 +1000, you wrote: > > > > >Hi all: > > > > > > > > > >I usually use a hierarchical structure for my schematic > > > > documents, with a > > > > >main document with all the connectors on it, then below > > > that a block > > > > >diagram, and then the actual circuitry on one or more levels > > > > below that. > > > > > > > > > >I'm currently doing a reasonable-sized board, with lots of > > > > digital lines, > > > > >and have amalgamated those lines into busses for the most part, > > > > > > > > Are these busses made up from dissimilar nets - that is stuff > > > > like nRD, > > > > nWR, nCSRAM all being merged in to a bus called something like > > > > CONTROLS? If so this won't work. Protel can only cope with > > > > busses of the > > > > "standard" form eg D[7..0] and nets D7 down to D0. > > > > > > A mixture of both; however I'm having just as much trouble on > > > the data bus > > > (TR_D00..TR_D15) as I am on the control busses... > > > > > > > > > > > > Cheers, > > > MvdW > > > > > > > > > > > > -- > ______________________________________________________________ > _____________ > www.integratedcontrolsinc.com Integrated Controls, Inc. > tel: 415-647-0480 2851 21st Street > fax: 415-647-3003 San Francisco, CA 94110 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://firstname.lastname@example.org * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *