Well I guess that is also why when you move a Ref Des on a part that is tied to VCC or GND it take a bit of time to keep analyzing VCC under DRC. Never seen a system do that. I can see a need to specifically drc silkscreen to pads etc on the board but not every time you touch a Ref'Des. And yes you can turn off DRC bu tit still seems to do it and actually whay should you have to turn it off just to touch a silkscreen?
Bob Wolfe. ----- Original Message ----- From: <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Friday, January 17, 2003 3:04 PM Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 . > Okay, call me dumb, but I am having a hard time understanding how the DRC > even comes into play, since the clearance constraint is, by definition, a > constraint on copper layers only. Since the silkscreen is not a copper > layer, the clearance constraint shouldn't even be invoked... > > What am I missing in this "equation"? > > aj > > > -----Original Message----- > > From: JaMi Smith [mailto:[EMAIL PROTECTED]] > > Sent: Friday, January 17, 2003 2:27 PM > > To: Protel EDA Forum > > Cc: JaMi Smith > > Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE > > SP6. > > > > > > John, > > > > You are not doing anything wrong, it's just Protel. > > > > This has been a pet peeve for a long time. > > > > Every other system out there will allow this. > > > > This is the old problem of having a whole row of 0603 or some other > > components with a rectangular box around each one of them and Protel > > demanding that you add and waste additional space between > > components rather > > than simply line them up next to each other with a common > > silkscreen line > > between them. > > > > Protel doesn't understand that this is not really a Design > > Error, and that > > it is not a "short", and that at worst it should only give > > you "warning" (or > > at least provide a "standard" means of allowing you to do this without > > having to resort to "kludging" something). > > > > Options: > > > > 1. Make a new component combining the two jumpers, with the > > silkscreen line > > seperating them drawn within the component itself. > > > > 2. Make a special component with one side of the silkscreen > > missing so that > > you can combine it with the other normal component. > > > > 3. Use a component that does not have an outline, and place > > the two of them > > where you want them, and manually "draw" your own outlines > > the way you want > > them to appear on the silkscreen ("Overlay") layer. While > > this may be the > > simplest way around the problem, it is a "kludge" in and of > > itself simply > > because it takes extra time and everything gets screwed up if > > you ever try > > and move anything involved since the lines are not part of > > the component. > > > > 4. Ignore the DRC Error and overlap the edges of the > > component so that it > > does exactly what you want it to do, and then put a note in a > > text file > > stored within the database that explains the problem to the > > next guy who has > > to work on the project. > > > > While I am sure that there will be some out there that will > > will reply to > > this post that will have some way to modify some special rule > > somewhere, my > > feeling on this is that making "special rules" for "special > > circumstances" > > is something that should be "anathema" in EDA Systems simply > > because the > > next guy to work on the project will never find it or > > understand it, and > > then when someone else (or even you after you forget about > > the "kludge") > > copies your database at a later date and modifies your file > > for a similar > > project he will now end up having a screwed up database with > > non standard > > rules that he doesn't even know about and will never find, > > and you will > > propagate the "special rule" for "special circumstances" > > "kludge" down the > > line "ad infinitium", which is shear stupidity. > > > > Go with the fourth option above and a note. At least everyone > > will be able > > to see it (the DRC Error) and even if they do not understand > > it, it won't > > get overlooked and lost in the process. > > > > JaMi Smith > > > > > > ----- Original Message ----- > > From: "John Branthoover" <[EMAIL PROTECTED]> > > To: "Protel EDA Forum" <[EMAIL PROTECTED]> > > Sent: Friday, January 17, 2003 9:57 AM > > Subject: [PEDA] A Question About PCB Design Rules..... Protel > > 99SE SP6. > > > > > > > Hello All, > > > I have two (2) position jumpers with a rectangular > > silkscreen drawn around > > > them. I want to place them on my PCB such that one side of > > the silkscreen > > > overlap. I created a component jumper class and added > > these two jumpers. > > > In the design rules under Placement, Component Clearance > > Constraint I set > > up > > > a rule for the jumper class to have a gap of 0 mil with > > scope A and B both > > > set to the jumper class. I did this thinking that it would > > allow me to > > > place the jumper side by side with the silkscreen s on one side > > overlapping > > > while not affecting other components. I also left the > > default Component > > > Clearance rule in place - 10 mil gap with scope A and B set > > to board. > > > > > > When I attempt this I get a violation as soon a s the > > silkscreen over lap. > > > If I un-check the On-line Component Clearance check box > > (under Design Rule > > > Check), I stop getting the violations. How ever, if > > click on the Run > > DRC > > > button, I still get a violation. Of coarse this also goes > > away when I > > > un-check the Report Component Clearance check box also > > under Design Rule > > > Check. > > > > > > What am I doing wrong? Any information that you can give > > will be greatly > > > appreciated. Thank you for your time and have a nice day. > > > > > > > > > > > > John Branthoover : > > > Electrical Design Engineer : > > > Acutronic R & D :Phone (412) 968-1051 > > > 640 Alpha Drive :Fax (412) 963-0816 > > > Pittsburgh PA 15238 :Email [EMAIL PROTECTED] > > > USA :WEB http://www.acutronic.com > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://firstname.lastname@example.org * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *