I agree that turning off component clearance checking completely is a
solution of sorts, but I myself am not comfortable doing that, since I am
not quite perfect yet (almost, but not yet), and I would rather have to look
at an error on the screen due to a bogus problem with Protel 99 times out of
100 (is that where the 99 came from), as opposed to look at an error in the
built hardware just once because I blew it and it wasn't caught because I
turned off the clearance checking.

JaMi

----- Original Message -----
From: "Brad Velander" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Friday, January 17, 2003 11:48 AM
Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .


> John,
> adding to Jami's list.
> 5) Do as I do, turn off the component placement DRC check completely. It
> just doesn't work in any usable manner. Use your eyes and personal
> knowledge.
> The component placement DRC uses any land pattern item, visible,
> invisible, regardless of layer to determine the maximum extent of the
> component. It then draws a bounding box around all these items, this
> constitutes the component boundary for the placement checking. Therefore
any
> designator, comment, text string, etc. gets included with the actual
desired
> component boundary.
> As you have found setting "0" allows placement down to touching but
> will still show a violation if items actually touch. I too think that this
> is a failing of Protel/Altium, a setting of "0" should allow items to
touch.
> It probably should allow overlap as well but I wouldn't push it that far
> because I don't see that being really useful or a common need.
>
> Sincerely,
> Brad Velander.
>
> Lead PCB Designer
> Norsat International Inc.
> Microwave Products
> Tel   (604) 292-9089 (direct line)
> Fax  (604) 292-9010
> email: [EMAIL PROTECTED]
> http://www.norsat.com
>
>
> > -----Original Message-----
> > From: John Branthoover [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, January 17, 2003 9:57 AM
> > To: Protel EDA Forum
> > Subject: [PEDA] A Question About PCB Design Rules..... Protel
> > 99SE SP6.
> <SNIP>
> >
> > What am I doing wrong?  Any information that you can
> > give will be greatly
> > appreciated.  Thank you for your time and have a nice day.
> >
> >
> >
> > John Branthoover            :
> > Electrical Design Engineer  :
> > Acutronic  R & D            :Phone  (412) 968-1051
> > 640 Alpha Drive             :Fax    (412) 963-0816
> > Pittsburgh PA 15238         :Email  [EMAIL PROTECTED]
> > USA                         :WEB    http://www.acutronic.com

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