> -----Original Message-----
> From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED] 
> Sent: Thursday, May 06, 2004 5:35 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Connectivity - Netlist issues
> 
> At 07:51 PM 5/5/2004, John A. Ross [RSDTV] wrote:
> snip <

> >There is a bit of pressure on me just now on other projects 
> so I might 
> >be overlooking something obvious, too much haste is usually counter 
> >productive.
> 
> Yes. You can focus on what needs to be done now; as to all 
> the upgrades, I'd suggest trying each of them, if it imports 
> fine, or with a few obvious and easily fixable problems, then 
> finish it. If not, set it aside (with the one you've already 
> described).

I think I might have gave the impression that this was my first
translation, I have designs running in DXP7.x that I translated OK, I
have others that need to be done, but the one in question is an anomaly
at present.

The most common errors I get are either multiple sheet entries of same
name (already covered that) and 'off grid' warnings. 

Off grid warnings are a real pain also as I never understood it. All my
SCH in 98/99SE were on 5/5 grid as was all lib parts. I never use off
grid objects. Perhaps the DB format changing causes issue.  

> If, after you've worked with a few, it looks like most of the 
> projects have serious problems, then you might put the whole 
> translation project on hold and come back to it when you can, 
> or when one of the translations becomes hot.

The translation process at the moment is on an 'as needed ' basis, many
have been done, but before any more are done I would like to get any
issues documented and procedures formed around them so that I am not
always the one that has to do it. 

That is to say a set of procedures to prepare a 99SE design as DXP
friendly to reduce time. 

In 99SE any changes can be done, a forward annotation update to the PCB
and a full PCB DRC done to validate there are no electrical changes or
otherwise that will effect PCB design integrity. 

> If there *are* a lot of problems, it would seem that 99SE 
> error conditions were routinely being ignored and dealt with 
> in an ad-hoc manner, thus accumulating problems, pointing out 
> how failing to fix an error condition when it is first found 
> can lead to more error conditions in the future, etc.

Not the cases, this designs stubborn attitude is an anomaly, albeit an
anomaly that may or may not exist across many designs, a lot of the
designs have had power rails routinely connected via sheet entries and
sheet ports regardless of any error as a precautionary procedure. 

This has been done since P98. As far as risk goes, that could be viewed
as one, but as I never use a connectivity model other than sheet
symbol/port connections the results are consistent and predictable and
never had it effect a PCB. But its always possible.

As DXP2004 did not like this import, (warned that net was reduced to
local....) , on this design, as I have done successfully before, I
removed all the top sheet level power ports and sheet entries, then
edited each sheet to remove the ports/net labels.

I still suspect I have either made a mess of the sheet edits in
frustration and hidden or moved a net label or net naming object, or the
design has a corrupt SCH symbol, or had an update done from a library
other than the company validated one, perhaps with hidden pins or pins
with power nets assigned (if I find that, I will hang the SOB that did
it, as company procedure bans hidden pins or pins with nets pre-assigned
when drafting SCH symbols) 

But my Friday afternoon mission is to nail this down, it will be done
before its time to go home.

All help is greatly appreciated.

Best Regards

John A. Ross

RSD Communications ltd
Email  [EMAIL PROTECTED]
WWW    http://www.rsd.tv
==================================   


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