[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added flexibility to RISC-V FS config
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43625 )
Change subject: arch-riscv: Added flexibility to RISC-V FS config
..
arch-riscv: Added flexibility to RISC-V FS config
Made some small changes to add flexibility to linux boot options.
Also briefly explained the usage in comments.
Change-Id: I4f02e7ffeca3e104a4d640db4cc900a208b74a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43625
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/riscv/fs_linux.py
1 file changed, 68 insertions(+), 32 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 19520be..55097ba 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -1,4 +1,3 @@
-# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -10,6 +9,7 @@
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
+# Copyright (c) 2021 Huawei International
# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
# Copyright (c) 2006-2007 The Regents of The University of Michigan
@@ -63,6 +63,30 @@
from common.Caches import *
from common import Options
+# - Usage Instructions - #
+# Common system confirguration options (cpu types, num cpus, checkpointing
+# etc.) should be supported
+#
+# Ruby not supported in this config file. Not tested on RISC-V FS Linux (as
+# of 25 March 2021).
+#
+# Options (Full System):
+# --kernel (required): Bootloader + kernel binary (e.g. bbl with
+# linux kernel payload)
+# --disk-image (optional): Path to disk image file. Not needed if
using
+# ramfs (might run into issues though).
+# --command-line (optional):Specify to override default.
+# --dtb-filename (optional):Path to DTB file. Auto-generated if empty.
+# --bare-metal (boolean): Use baremetal Riscv (default False). Use
this
+# if bbl is built with "--with-dts" option.
+# (do not forget to include bootargs in dts
file)
+#
+# Not Used:
+# --command-line-file, --script, --frame-capture, --os-type, --timesync,
+# --dual, -b, --etherdump, --root-device, --ruby
+
+
+# --- DTB Generation Function -- #
def generateMemNode(state, mem_range):
node = FdtNode("memory@%x" % int(mem_range.start))
@@ -73,10 +97,6 @@
return node
def generateDtb(system):
-"""
-Autogenerate DTB. Arguments are the folder where the DTB
-will be stored, and the name of the DTB file.
-"""
state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
root = FdtNode('/')
root.append(state.addrCellsProperty())
@@ -104,10 +124,11 @@
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
-
-# NOTE: Ruby in FS Linux has not been tested yet
-if '--ruby' in sys.argv:
-Ruby.define_options(parser)
+parser.add_argument("--bare-metal", action="store_true",
+help="Provide the raw system without the linux specific bits")
+parser.add_argument("--dtb-filename", action="store", type=str,
+help="Specifies device tree blob file to use with device-tree-"\
+"enabled kernels")
# Parse Options --- #
args = parser.parse_args()
@@ -119,21 +140,26 @@
np = args.num_cpus
# Setup System #
-# Edit this section to customize peripherals and system settings
+# Default Setup
system = System()
mdesc = SysConfig(disks=args.disk_image, rootdev=args.root_device,
mem=args.mem_size, os_type=args.os_type)
system.mem_mode = mem_mode
system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
-system.workload = RiscvLinux()
+if args.bare_metal:
+system.workload = RiscvBareMetal()
+system.workload.bootloader = args.kernel
+else:
+system.workload = RiscvLinux()
+system.workload.object_file = args.kernel
system.iobus = IOXBar()
system.membus = MemBus()
system.system_port = system.membus.cpu_side_ports
-# HiFive platform
+# HiFive Platform
system.platform = HiFive()
# RTCCLK (Set to 100MHz for faster simulation)
@@ -141,14 +167,15 @@
system.platform.clint.int_pin = system.platform.rtc.int_pin
# VirtIOMMIO
-image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
-image.child.image_file = mdesc.disks()[0]
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Added flexibility to RISC-V FS config
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43625 )
Change subject: arch-riscv: Added flexibility to RISC-V FS config
..
arch-riscv: Added flexibility to RISC-V FS config
Made some small changes to add flexibility to linux boot options.
Also briefly explained the usage in comments.
Change-Id: I4f02e7ffeca3e104a4d640db4cc900a208b74a5a
---
M configs/common/Options.py
M configs/example/riscv/fs_linux.py
2 files changed, 67 insertions(+), 36 deletions(-)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index c48bfe6..1b320c6 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -462,6 +462,12 @@
parser.add_option("--vio-9p", action="store_true",
help=vio_9p_help)
parser.add_option("--bootloader", action='append',
help="executable file that runs before the --kernel")
+if buildEnv['TARGET_ISA'] == "riscv":
+parser.add_option("--bare-metal", action="store_true",
+help="Provide the raw system without the linux specific bits")
+parser.add_option("--dtb-filename", action="store", type="string",
+help="Specifies device tree blob file to use with
device-tree-"\
+ "enabled kernels")
# Benchmark options
parser.add_option("--dual", action="store_true",
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 28e6714..64ba142 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -1,4 +1,3 @@
-# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -10,6 +9,7 @@
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
+# Copyright (c) 2021 Huawei International
# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
# Copyright (c) 2006-2007 The Regents of The University of Michigan
@@ -63,6 +63,30 @@
from common.Caches import *
from common import Options
+# - Usage Instructions - #
+# Common system confirguration options (cpu types, num cpus, checkpointing
+# etc.) should be supported
+#
+# Ruby not supported in this config file. Not tested on RISC-V FS Linux (as
+# of 25 March 2021).
+#
+# Options (Full System):
+# --kernel (required): Bootloader + kernel binary (e.g. bbl with
+# linux kernel payload)
+# --disk-image (optional): Path to disk image file. Not needed if
using
+# ramfs (might run into issues though).
+# --command-line (optional):Specify to override default.
+# --dtb-filename (optional):Path to DTB file. Auto-generated if empty.
+# --bare-metal (boolean): Use baremetal Riscv (default False). Use
this
+# if bbl is built with "--with-dts" option.
+# (do not forget to include bootargs in dts
file)
+#
+# Not Used:
+# --command-line-file, --script, --frame-capture, --os-type, --timesync,
+# --dual, -b, --etherdump, --root-device, --ruby
+
+
+# --- DTB Generation Function -- #
def generateMemNode(state, mem_range):
node = FdtNode("memory@%x" % int(mem_range.start))
@@ -73,10 +97,6 @@
return node
def generateDtb(system):
-"""
-Autogenerate DTB. Arguments are the folder where the DTB
-will be stored, and the name of the DTB file.
-"""
state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
root = FdtNode('/')
root.append(state.addrCellsProperty())
@@ -105,10 +125,6 @@
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
-# NOTE: Ruby in FS Linux has not been tested yet
-if '--ruby' in sys.argv:
-Ruby.define_options(parser)
-
# Parse Options --- #
(options, args) = parser.parse_args()
@@ -123,14 +139,19 @@
np = options.num_cpus
# Setup System #
-# Edit this section to customize peripherals and system settings
+# Default Setup
system = System()
mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
mem=options.mem_size, os_type=options.os_type)
system.mem_mode = mem_mode
system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
-system.workload = RiscvLinux()
+if options.bare_metal:
+system.workload = RiscvBareMetal()
+system.workload.bootloader = options.kernel
+else:
+system.workload = RiscvLinux()
+system.workload.object_file = options.kernel
system.iobus = IOXBar()
system.membus = MemBus()
@@ -139,7 +160,7 @@
system.intrctrl = IntrControl()
-#
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Fix Clint and SATP write side effects
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43244 )
Change subject: arch-riscv: Fix Clint and SATP write side effects
..
arch-riscv: Fix Clint and SATP write side effects
Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:
1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).
2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).
Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43244
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Ayaz Akram
Reviewed-by: Peter Yuen
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/pma_checker.cc
M src/dev/riscv/clint.cc
3 files changed, 9 insertions(+), 3 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, but someone else must approve
Peter Yuen: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index aa94942..709c944 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -92,7 +92,11 @@
CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
csr(FUNCT12), uimm(CSRIMM)
-{}
+{
+if (csr == CSR_SATP) {
+flags[IsSquashAfter] = true;
+}
+}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index d36dc1d..15c5cf9 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -54,7 +54,7 @@
PMAChecker::check(const RequestPtr )
{
if (isUncacheable(req->getPaddr(), req->getSize())) {
-req->setFlags(Request::UNCACHEABLE);
+req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
}
}
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 641ba6f..ced9122 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -64,7 +64,9 @@
for (int context_id = 0; context_id < nThread; context_id++) {
// Update misc reg file
-system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME,
mtime);
+ISA* isa = dynamic_cast(
+system->threads[context_id]->getIsaPtr());
+isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
// Post timer interrupt
uint64_t mtimecmp = registers.mtimecmp[context_id].get();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43244
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Gerrit-Change-Number: 43244
Gerrit-PatchSet: 3
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Peter Yuen
Gerrit-Reviewer: kokoro
Gerrit-CC: Liao Xiongfei
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Added DTB Generation Functionality to RISC-V FS
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42053 )
Change subject: arch-riscv: Added DTB Generation Functionality to RISC-V FS
..
arch-riscv: Added DTB Generation Functionality to RISC-V FS
Changes:
1. RiscvBareMetal
The RiscvBareMetal class and API are preserved for backwards
compatibility, but the base class RiscvFSWorkload is removed
as it inherits from the Workload class. However, most needed
functionalities are already implemented in the KernelWorkload
class
2. RiscvLinux
The RiscvLinux class is added. A dtb filename can be specified
to be loaded to the corresponding memory address.
3. HiFive, Clint, Plic, Uart8250, VirtIOMMIO
Devicetree node generation function is added.
4. tlb, faults
Unnecessary includes of arch/riscv/fs_workload are removed.
Change-Id: Ia239b5614bd93d8e794330ead266f6121a4d13cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42053
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Ayaz Akram
Reviewed-by: Bobby R. Bruce
---
M configs/example/riscv/fs_linux.py
M src/arch/riscv/RiscvFsWorkload.py
M src/arch/riscv/SConscript
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/faults.cc
A src/arch/riscv/linux/fs_workload.cc
R src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/tlb.cc
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/PlicDevice.py
M src/dev/riscv/VirtIOMMIO.py
M src/dev/serial/Uart.py
15 files changed, 305 insertions(+), 58 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 3d40061..28e6714 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -40,6 +40,7 @@
import optparse
import sys
+from os import path
import m5
from m5.defines import buildEnv
@@ -62,6 +63,43 @@
from common.Caches import *
from common import Options
+
+def generateMemNode(state, mem_range):
+node = FdtNode("memory@%x" % int(mem_range.start))
+node.append(FdtPropertyStrings("device_type", ["memory"]))
+node.append(FdtPropertyWords("reg",
+state.addrCells(mem_range.start) +
+state.sizeCells(mem_range.size()) ))
+return node
+
+def generateDtb(system):
+"""
+Autogenerate DTB. Arguments are the folder where the DTB
+will be stored, and the name of the DTB file.
+"""
+state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
+root = FdtNode('/')
+root.append(state.addrCellsProperty())
+root.append(state.sizeCellsProperty())
+root.appendCompatible(["riscv-virtio"])
+
+for mem_range in system.mem_ranges:
+root.append(generateMemNode(state, mem_range))
+
+sections = [*system.cpu, system.platform]
+
+for section in sections:
+for node in section.generateDeviceTree(state):
+if node.get_name() == root.get_name():
+root.merge(node)
+else:
+root.append(node)
+
+fdt = Fdt()
+fdt.add_rootnode(root)
+fdt.writeDtsFile(path.join(m5.options.outdir, 'device.dts'))
+fdt.writeDtbFile(path.join(m5.options.outdir, 'device.dtb'))
+
# - Add Options #
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
@@ -92,12 +130,12 @@
system.mem_mode = mem_mode
system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
-system.workload = RiscvBareMetal()
+system.workload = RiscvLinux()
system.iobus = IOXBar()
system.membus = MemBus()
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
system.intrctrl = IntrControl()
@@ -147,7 +185,7 @@
voltage_domain =
system.cpu_voltage_domain)
-system.workload.bootloader = options.kernel
+system.workload.object_file = options.kernel
# NOTE: Not yet tested
if options.script is not None:
@@ -161,12 +199,12 @@
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
system.iocache = IOCache(addr_ranges = system.mem_ranges)
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
+system.iocache.cpu_side = system.iobus.mem_side_ports
+system.iocache.mem_side = system.membus.cpu_side_ports
elif not options.external_memory_system:
system.iobridge = Bridge(delay='50ns', ranges = system.mem_ranges)
-system.iobridge.slave = system.iobus.master
-system.iobridge.master = system.membus.slave
+system.iobridge.cpu_side_ports = system.iobus.mem_side_ports
+system.iobridge.mem_side_ports =
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch,cpu: Stop using << and to_number for VecReg serialization.
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43243
to review the following change.
Change subject: arch,cpu: Stop using << and to_number for VecReg
serialization.
..
arch,cpu: Stop using << and to_number for VecReg serialization.
Override ParseParam<>::parse and ShowParam<>::parse directly. This will
allow using a different format for serializing and displaying registers.
Also get rid of the print() methods. When any cprintf based mechanism is
used (like DPRINTF), the underlying mechanism will use << to output the
value. Since we already override <<, there's no reason to wrap that in a
method which calls csprintf which calls << anyway.
Change-Id: Id65b9a657507f2f2cdf9673fd961cfeb0590f48c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41994
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
---
M src/arch/generic/vec_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 38 insertions(+), 44 deletions(-)
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 379de28..64c131f 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -97,14 +97,13 @@
#define __ARCH_GENERIC_VEC_REG_HH__
#include
-#include
#include
#include
#include
-#include
#include "base/cprintf.hh"
#include "base/logging.hh"
+#include "sim/serialize_handlers.hh"
constexpr unsigned MaxVecRegLenInBytes = 4096;
@@ -175,8 +174,6 @@
return os;
}
-const std::string print() const { return csprintf("%s", *this); }
-
/**
* Cast to VecRegContainer&
* It is useful to get the reference to the container for ISA tricks,
@@ -211,12 +208,6 @@
public:
VecRegContainer() {}
VecRegContainer(const VecRegContainer &) = default;
-/* This is required for de-serialisation. */
-VecRegContainer(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), [0], SIZE);
-}
/** Zero the container. */
void zero() { memset(container.data(), 0, SIZE); }
@@ -239,17 +230,6 @@
std::memcpy(container.data(), that.data(), SIZE);
return *this;
}
-
-/** From vector.
- * This is required for de-serialisation.
- * */
-MyClass&
-operator=(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), that.data(), SIZE);
-return *this;
-}
/** @} */
/** Equality operator.
@@ -272,7 +252,6 @@
return !operator==(that);
}
-const std::string print() const { return csprintf("%s", *this); }
/** Get pointer to bytes. */
template
const Ret* raw_ptr() const { return (const Ret*)container.data(); }
@@ -313,19 +292,20 @@
return VecRegT(*this);
}
-/** @} */
-/**
- * Output operator.
- * Used for serialization.
- */
friend std::ostream&
operator<<(std::ostream& os, const MyClass& v)
{
for (auto& b: v.container) {
-os << csprintf("%02x", b);
+ccprintf(os, "%02x", b);
}
return os;
}
+
+/** @} */
+/**
+ * Used for serialization.
+ */
+friend ShowParam;
};
/**
@@ -333,20 +313,34 @@
*/
/** @{ */
template
-inline bool
-to_number(const std::string& value, VecRegContainer& v)
+struct ParseParam>
{
-fatal_if(value.size() > 2 * VecRegContainer::size(),
- "Vector register value overflow at unserialize");
+static bool
+parse(const std::string , VecRegContainer )
+{
+fatal_if(str.size() > 2 * Sz,
+ "Vector register value overflow at unserialize");
-for (int i = 0; i < VecRegContainer::size(); i++) {
-uint8_t b = 0;
-if (2 * i < value.size())
-b = stoul(value.substr(i * 2, 2), nullptr, 16);
-v.template raw_ptr()[i] = b;
+for (int i = 0; i < Sz; i++) {
+uint8_t b = 0;
+if (2 * i < value.size())
+b = stoul(str.substr(i * 2, 2), nullptr, 16);
+value.template raw_ptr()[i] = b;
+}
+return true;
}
-return true;
-}
+};
+
+template
+struct ShowParam>
+{
+static void
+show(std::ostream , const VecRegContainer )
+{
+for (auto& b: value.container)
+ccprintf(os, "%02x", b);
+}
+};
/** @} */
/**
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 71f2e72..6c6b9b3 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -203,7 +203,7 @@
DPRINTF(IEW, "RegFile: Access to vector register %i, has "
"data %s\n", int(phys_reg->index()),
-vectorRegFile[phys_reg->index()].print());
+
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Fix Clint and SATP write side effects
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43244 )
Change subject: arch-riscv: Fix Clint and SATP write side effects
..
arch-riscv: Fix Clint and SATP write side effects
Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:
1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).
2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).
Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/pma_checker.cc
M src/dev/riscv/clint.cc
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index aa94942..4a3f5ef 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -92,7 +92,11 @@
CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
csr(FUNCT12), uimm(CSRIMM)
-{}
+{
+ if (csr == CSR_SATP) {
+flags[IsSquashAfter] = true;
+ }
+}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index d36dc1d..15c5cf9 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -54,7 +54,7 @@
PMAChecker::check(const RequestPtr )
{
if (isUncacheable(req->getPaddr(), req->getSize())) {
-req->setFlags(Request::UNCACHEABLE);
+req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
}
}
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 641ba6f..ced9122 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -64,7 +64,9 @@
for (int context_id = 0; context_id < nThread; context_id++) {
// Update misc reg file
-system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME,
mtime);
+ISA* isa = dynamic_cast(
+system->threads[context_id]->getIsaPtr());
+isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
// Post timer interrupt
uint64_t mtimecmp = registers.mtimecmp[context_id].get();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43244
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Gerrit-Change-Number: 43244
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: cpu: Eliminate the unused "lane" interface from the ThreadContext.
Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43240
to review the following change.
Change subject: cpu: Eliminate the unused "lane" interface from the
ThreadContext.
..
cpu: Eliminate the unused "lane" interface from the ThreadContext.
If someone needs to access a component of a vector register, they can do
so through the other interfaces.
Change-Id: Idf1d9b68339eb31b95d4a347548240aa9d2a85cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41899
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
7 files changed, 0 insertions(+), 393 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index b7ea0b5..019baca 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -283,62 +283,6 @@
panic("%s not implemented.", __FUNCTION__);
}
-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-ConstVecLane8
-readVec8BitLaneReg(const RegId ) const override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
-/** Reads source vector 16bit operand. */
-ConstVecLane16
-readVec16BitLaneReg(const RegId ) const override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
-/** Reads source vector 32bit operand. */
-ConstVecLane32
-readVec32BitLaneReg(const RegId ) const override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
-/** Reads source vector 64bit operand. */
-ConstVecLane64
-readVec64BitLaneReg(const RegId ) const override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
-/** Write a lane of the destination vector register. */
-void
-setVecLane(const RegId , const LaneData )
override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-/** @} */
-
const VecElem &
readVecElem(const RegId ) const override
{
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 338e871..661c710 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -249,63 +249,6 @@
return actualTC->getWritableVecReg(reg);
}
-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-ConstVecLane8
-readVec8BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec8BitLaneReg(reg);
-}
-
-/** Reads source vector 16bit operand. */
-ConstVecLane16
-readVec16BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec16BitLaneReg(reg);
-}
-
-/** Reads source vector 32bit operand. */
-ConstVecLane32
-readVec32BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec32BitLaneReg(reg);
-}
-
-/** Reads source vector 64bit operand. */
-ConstVecLane64
-readVec64BitLaneReg(const RegId ) const override
-{
-return actualTC->readVec64BitLaneReg(reg);
-}
-
-/** Write a lane of the destination vector register. */
-virtual void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
- const LaneData ) override
-{
-return actualTC->setVecLane(reg, val);
-}
-/** @} */
-
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 596fa19..73b86af 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -345,37 +345,6 @@
void vecRenameMode(Enums::VecRegRenameMode vec_mode)
{ vecMode = vec_mode; }
-
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch: Eliminate the "Lane" view of vector registers.
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43241
to review the following change.
Change subject: arch: Eliminate the "Lane" view of vector registers.
..
arch: Eliminate the "Lane" view of vector registers.
Nothing uses it.
Change-Id: I1b8a629cfff5c9a58584045ac25424fa8b6dfb24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41900
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
---
M src/arch/generic/vec_reg.hh
1 file changed, 3 insertions(+), 270 deletions(-)
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index a647cd8..3091034 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -47,8 +47,8 @@
* As the (maximum) length of the physical vector register is a
compile-time
* constant, it is defined as a template parameter.
*
- * This file also describes two views of the container that have semantic
- * information about the bytes. The first of this views is VecRegT.
+ * This file also describe one view of the container that has semantic
+ * information about the bytes, the VecRegT.
*A VecRegT is a view of a VecRegContainer (by reference). The VecRegT
has
*a type (VecElem) to which bytes are casted, and the amount of such
*elements that the vector contains (NumElems). The size of a view,
@@ -56,18 +56,9 @@
*underlying container. As VecRegT has some degree of type information
it
*has vector semantics, and defines the index operator ([]) to get
*references to particular bytes understood as a VecElem.
- * The second view of a container implemented in this file is VecLaneT,
which
- * is a view of a subset of the container.
- *A VecLaneT is a view of a lane of a vector register, where a lane is
- *identified by a type (VecElem) and an index (although the view is
- *unaware of its index). Operations on the lane are directly applied to
- *the corresponding bytes of the underlying VecRegContainer through a
- *reference.
*
* The intended usage is requesting views to the VecRegContainer via the
- * member 'as' for VecRegT and the member 'laneView' for VecLaneT. Kindly
- * find an example of usage in the following.
- *
+ * member 'as' for VecRegT.
*
* // We declare 512 bits vectors
* using Vec512 = VecRegContainer<64>;
@@ -100,41 +91,6 @@
*xc->setWriteRegOperand(this, 0, vdstraw);
* }
*
- * // Usage example, for a micro op that operates over lane number _lidx:
- * VecFloatLaneAdd(ExecContext* xd) {
- *// Request source vector register to the execution context (const as
it
- *// is read only).
- *const Vec512& vsrc1raw = xc->readVecRegOperand(this, 0);
- *// View it as a lane of a vector of floats (we could just specify the
- *// first template parametre, the second is derived by the constness
of
- *// vsrc1raw).
- *VecLaneT& src1 = vsrc1raw->laneView(this->_lidx);
- *
- *// Second source and view
- *const Vec512& vsrc2raw = xc->readVecRegOperand(this, 1);
- *VecLaneT& src2 = vsrc2raw->laneView(this->_lidx);
- *
- *// (Writable) destination and view
- *// As this is a partial write, we need the exec context to support
that
- *// through, e.g., 'readVecRegOperandToWrite' returning a writable
- *// reference to the register
- *Vec512 vdstraw = xc->readVecRegOperandToWrite(this, 3);
- *VecLaneT& dst = vdstraw->laneView(this->_lidx);
- *
- *dst = src1 + src2;
- *// There is no need to copy the value back into the exec context, as
- *// the assignment to dst modifies the appropriate bytes in vdstraw
which
- *// is in turn, a reference to the register in the cpu model.
- *// For operations that do conditional writeback, we can decouple the
- *// write by doing:
- *// auto tmp = src1 + src2;
- *// if (test) {
- *// dst = tmp; // do writeback
- *// } else {
- *// // do not do writeback
- *// }
- * }
- *
*/
#ifndef __ARCH_GENERIC_VEC_REG_HH__
@@ -257,10 +213,6 @@
operator Container&() { return container; }
};
-/* Forward declaration. */
-template
-class VecLaneT;
-
/**
* Vector Register Abstraction
* This generic class is the model in a particularization of MVC, to vector
@@ -402,14 +354,6 @@
return VecRegT(*this);
}
-template
-VecLaneT laneView();
-template
-VecLaneT laneView() const;
-template
-VecLaneT laneView(int laneIdx);
-template
-VecLaneT laneView(int laneIdx) const;
/** @} */
/**
* Output operator.
@@ -424,217 +368,6 @@
}
};
-/** We define an auxiliary abstraction for LaneData. The ISA should care
- * about the semantics of a, e.g., 32bit element, treating it as a signed
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch: Simplify and correct style of VecReg types.
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43242
to review the following change.
Change subject: arch: Simplify and correct style of VecReg types.
..
arch: Simplify and correct style of VecReg types.
Change-Id: Ib15d2e03c3e9cabcf56b316d5c57d2e892ad255d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41993
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/generic/vec_reg.hh
1 file changed, 23 insertions(+), 63 deletions(-)
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 3091034..379de28 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -125,12 +125,14 @@
template
class VecRegT
{
+ private:
/** Size of the register in bytes. */
static constexpr inline size_t
size()
{
return sizeof(VecElem) * NumElems;
}
+
public:
/** Container type alias. */
using Container = typename std::conditional
-typename std::enable_if_t
-zero() { container.zero(); }
-
-template
-typename std::enable_if_t
-operator=(const MyClass& that)
-{
-container = that.container;
-return *this;
-}
-
/** Index operator. */
-const VecElem& operator[](size_t idx) const
+const VecElem &
+operator[](size_t idx) const
{
return container.template raw_ptr()[idx];
}
@@ -173,25 +163,6 @@
return container.template raw_ptr()[idx];
}
-/** Equality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator==(const VecRegT& that) const
-{
-return container == that.container;
-}
-/** Inequality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator!=(const VecRegT& that) const
-{
-return !operator==(that);
-}
-
/** Output stream operator. */
friend std::ostream&
operator<<(std::ostream& os, const MyClass& vr)
@@ -205,6 +176,7 @@
}
const std::string print() const { return csprintf("%s", *this); }
+
/**
* Cast to VecRegContainer&
* It is useful to get the reference to the container for ISA tricks,
@@ -223,10 +195,11 @@
template
class VecRegContainer
{
- static_assert(SIZE > 0,
- "Cannot create Vector Register Container of zero size");
- static_assert(SIZE <= MaxVecRegLenInBytes,
- "Vector Register size limit exceeded");
+ private:
+static_assert(SIZE > 0,
+"Cannot create Vector Register Container of zero size");
+static_assert(SIZE <= MaxVecRegLenInBytes,
+"Vector Register size limit exceeded");
public:
static constexpr inline size_t size() { return SIZE; };
using Container = std::array;
@@ -251,16 +224,17 @@
/** Assignment operators. */
/** @{ */
/** From VecRegContainer */
-MyClass& operator=(const MyClass& that)
+MyClass&
+operator=(const MyClass& that)
{
if ( == this)
return *this;
-memcpy(container.data(), that.container.data(), SIZE);
-return *this;
+return *this = that.container;
}
/** From appropriately sized uint8_t[]. */
-MyClass& operator=(const Container& that)
+MyClass&
+operator=(const Container& that)
{
std::memcpy(container.data(), that.data(), SIZE);
return *this;
@@ -269,7 +243,8 @@
/** From vector.
* This is required for de-serialisation.
* */
-MyClass& operator=(const std::vector& that)
+MyClass&
+operator=(const std::vector& that)
{
assert(that.size() >= SIZE);
std::memcpy(container.data(), that.data(), SIZE);
@@ -277,24 +252,6 @@
}
/** @} */
-/** Copy the contents into the input buffer. */
-/** @{ */
-/** To appropriately sized uint8_t[] */
-void copyTo(Container& dst) const
-{
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-
-/** To vector
- * This is required for serialisation.
- * */
-void copyTo(std::vector& dst) const
-{
-dst.resize(SIZE);
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-/** @} */
-
/** Equality operator.
* Required to compare thread contexts.
*/
@@ -335,7 +292,8 @@
*/
/** @{ */
template
-VecRegT as() const
+VecRegT
+as() const
{
static_assert(SIZE % sizeof(VecElem) == 0,
"VecElem does not evenly divide the register size");
@@ -345,7 +303,8 @@
}
template
-VecRegT as()
+VecRegT
+as()
{
static_assert(SIZE % sizeof(VecElem) == 0,
"VecElem does not evenly divide the register size");
@@ -359,7
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Add a szext function for true sign extension.
Attention is currently required from: Daniel Carvalho.
Hello kokoro, Daniel Carvalho,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43236
to review the following change.
Change subject: base: Add a szext function for true sign extension.
..
base: Add a szext function for true sign extension.
The existing sext function is a bit of a misnomer since it doesn't
actually sign extend its input, it just extends the sign if the sign bit
was zero.
This change adds a new szext function which truly sign extends the
value, although with a tiny amount of additional overhead.
Change-Id: I562ce479b771be8a3319934aeff55e797126a146
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42384
Reviewed-by: Daniel Carvalho
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/bitfield.hh
M src/base/bitfield.test.cc
2 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 9dc7722..d47ab8c 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -112,7 +112,9 @@
}
/**
- * Sign-extend an N-bit value to 64 bits.
+ * Sign-extend an N-bit value to 64 bits. Assumes all bits past the sign
are
+ * currently zero. For true sign extension regardless of the value of the
sign
+ * bit, see szext.
*
* @ingroup api_bitfield
*/
@@ -127,6 +129,24 @@
}
/**
+ * Sign-extend an N-bit value to 64 bits. Zero any bits past the sign if
+ * necessary.
+ *
+ * @ingroup api_bitfield
+ */
+template
+constexpr inline uint64_t
+szext(uint64_t val)
+{
+bool sign_bit = bits(val, N - 1);
+if (sign_bit)
+val |= ~mask(N);
+else
+val &= mask(N);
+return val;
+}
+
+/**
* Returns val with bits first to last set to the LSBs of bit_val
*
* E.g.:
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 8097415..c2ef8d2 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -164,7 +164,8 @@
/*
* The following tests the "sext(X)" function. sext carries out a sign
- * extention from N bits to 64 bits on value X.
+ * extention from N bits to 64 bits on value X. It does not zero bits past
the
+ * sign bit if it was zero.
*/
TEST(BitfieldTest, SignExtendPositiveInput)
{
@@ -191,6 +192,36 @@
uint64_t output = 0xF8001008;
EXPECT_EQ(output, sext<60>(val));
}
+/*
+ * The following tests the "szext(X)" function. szext carries out a sign
+ * extention from N bits to 64 bits on value X. Will zero bits past the
sign
+ * bit if it was zero.
+ */
+TEST(BitfieldTest, SignZeroExtendPositiveInput)
+{
+int8_t val = 14;
+int64_t output = 14;
+EXPECT_EQ(output, szext<8>(val));
+}
+
+TEST(BitfieldTest, SignZeroExtendNegativeInput)
+{
+int8_t val = -14;
+uint64_t output = -14;
+EXPECT_EQ(output, szext<8>(val));
+}
+
+TEST(BitfieldTest, SignZeroExtendPositiveInputOutsideRange)
+{
+EXPECT_EQ(0, szext<8>(1 << 10));
+}
+
+TEST(BitfieldTest, SignZeroExtendNegativeInputOutsideRange)
+{
+uint64_t val = 0x48001008;
+uint64_t output = 0xF8001008;
+EXPECT_EQ(output, szext<60>(val));
+}
/* The following tests "insertBits(A, B, C, D)". insertBits returns A
* with bits B to C set to D's (B - C) LSBs. "insertBits(A, B, D)"
overrides
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43236
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: I562ce479b771be8a3319934aeff55e797126a146
Gerrit-Change-Number: 43236
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-Attention: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Remove "inline" from bitfield.hh.
Attention is currently required from: Daniel Carvalho.
Hello kokoro, Daniel Carvalho,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43237
to review the following change.
Change subject: base: Remove "inline" from bitfield.hh.
..
base: Remove "inline" from bitfield.hh.
Those functions are all constexpr which implies inline, so the inline is
redundant.
Change-Id: I7ddf13ddc833365f60f644c40c9fcb16a3e6285e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42385
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/base/bitfield.hh
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index d47ab8c..888b365 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -56,7 +56,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline uint64_t
+constexpr uint64_t
mask(unsigned nbits)
{
return (nbits >= 64) ? (uint64_t)-1LL : (1ULL << nbits) - 1;
@@ -69,7 +69,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline T
+constexpr T
bits(T val, unsigned first, unsigned last)
{
assert(first >= last);
@@ -83,7 +83,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline T
+constexpr T
bits(T val, unsigned bit)
{
return bits(val, bit, bit);
@@ -96,7 +96,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline T
+constexpr T
mbits(T val, unsigned first, unsigned last)
{
return val & (mask(first + 1) & ~mask(last));
@@ -105,7 +105,7 @@
/**
* @ingroup api_bitfield
*/
-constexpr inline uint64_t
+constexpr uint64_t
mask(unsigned first, unsigned last)
{
return mbits((uint64_t)-1LL, first, last);
@@ -119,7 +119,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline uint64_t
+constexpr uint64_t
sext(uint64_t val)
{
bool sign_bit = bits(val, N - 1);
@@ -135,7 +135,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline uint64_t
+constexpr uint64_t
szext(uint64_t val)
{
bool sign_bit = bits(val, N - 1);
@@ -159,7 +159,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline T
+constexpr T
insertBits(T val, unsigned first, unsigned last, B bit_val)
{
assert(first >= last);
@@ -175,7 +175,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline T
+constexpr T
insertBits(T val, unsigned bit, B bit_val)
{
return insertBits(val, bit, bit, bit_val);
@@ -190,7 +190,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline void
+constexpr void
replaceBits(T& val, unsigned first, unsigned last, B bit_val)
{
val = insertBits(val, first, last, bit_val);
@@ -202,7 +202,7 @@
* @ingroup api_bitfield
*/
template
-constexpr inline void
+constexpr void
replaceBits(T& val, unsigned bit, B bit_val)
{
val = insertBits(val, bit, bit, bit_val);
@@ -256,7 +256,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline int
+constexpr int
findMsbSet(uint64_t val)
{
int msb = 0;
@@ -292,7 +292,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline int
+constexpr int
findLsbSet(uint64_t val)
{
int lsb = 0;
@@ -330,7 +330,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline int
+constexpr int
popCount(uint64_t val)
{
#ifndef __has_builtin
@@ -365,7 +365,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline uint64_t
+constexpr uint64_t
alignToPowerOfTwo(uint64_t val)
{
val--;
@@ -388,7 +388,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline int
+constexpr int
ctz32(uint32_t value)
{
return value ? __builtin_ctzl(value) : 32;
@@ -402,7 +402,7 @@
*
* @ingroup api_bitfield
*/
-constexpr inline int
+constexpr int
ctz64(uint64_t value)
{
return value ? __builtin_ctzll(value) : 64;
--
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Gerrit-Change-Number: 43237
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-arm,base,dev: Eliminate the power() function from intmath.hh.
Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43238
to review the following change.
Change subject: arch-arm,base,dev: Eliminate the power() function from
intmath.hh.
..
arch-arm,base,dev: Eliminate the power() function from intmath.hh.
This function causes problems with gcc 5 which incorrectly complains
about the call to warn_if inside a constexpr function. That should only
be an error if a call to a non-constexpr is unavoidable, and even then
the compiler isn't required to emit a diagnostic.
Rather than drop the warning, or add ifdefs to deal with these defective
versions of gcc, this change eliminates the power() function entirely.
Most inputs to this function would overflow anyway, which is reportedly
why no integer version of an exponentiation function is defined in the
standard library, and all uses of this function can easily and more
efficiently be replaced by simple left and right shifts.
Finally, by eliminating the power() function, we also remove the
dependence on base/logging.hh.
Change-Id: I4d014163883d12db46da4ee752696c8225534ee8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42504
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/isa/insts/data64.isa
M src/base/intmath.hh
M src/base/intmath.test.cc
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/timer_sp804.cc
5 files changed, 8 insertions(+), 36 deletions(-)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 1cd17b7..46a046b 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -382,7 +382,7 @@
Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO;
EA = XBase;
assert(!(Dczid & 0x10));
- uint64_t op_size = power(2, Dczid + 2);
+ uint64_t op_size = 1ULL << (Dczid + 2);
EA &= ~(op_size - 1);
'''
diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index ba20177..85ee525 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -46,31 +46,11 @@
#include
#include "base/bitfield.hh"
-#include "base/logging.hh"
#include "base/types.hh"
/**
* @ingroup api_base_utils
*/
-static constexpr uint64_t
-power(uint32_t n, uint32_t e)
-{
-uint64_t result = 1;
-uint64_t component = n;
-while (e) {
-uint64_t last = result;
-if (e & 0x1)
-result *= component;
-warn_if(result < last, "power() overflowed!");
-e >>= 1;
-component *= component;
-}
-return result;
-}
-
-/**
- * @ingroup api_base_utils
- */
template
static constexpr std::enable_if_t::value, int>
floorLog2(T x)
diff --git a/src/base/intmath.test.cc b/src/base/intmath.test.cc
index e953a7e..b4bd2a5 100644
--- a/src/base/intmath.test.cc
+++ b/src/base/intmath.test.cc
@@ -54,13 +54,6 @@
EXPECT_FALSE(isPowerOf2(1679616));
}
-TEST(IntmathTest, power)
-{
-EXPECT_EQ(65536, power(2, 16));
-EXPECT_EQ(9765625, power(5, 10));
-EXPECT_EQ(43046721, power(power(3, 4), 4));
-}
-
TEST(IntmathTest, floorLog2)
{
EXPECT_EQ(0, floorLog2(1));
diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc
index 760adf5..3b120f6 100644
--- a/src/dev/arm/timer_cpulocal.cc
+++ b/src/dev/arm/timer_cpulocal.cc
@@ -123,8 +123,7 @@
timerZeroEvent.when(), parent->clockPeriod(),
timerControl.prescalar);
time = timerZeroEvent.when() - curTick();
-time = time / parent->clockPeriod() /
-power(16, timerControl.prescalar);
+time = (time / parent->clockPeriod()) >> (4 *
timerControl.prescalar);
DPRINTF(Timer, "-- returning counter at %d\n", time);
pkt->setLE(time);
break;
@@ -143,8 +142,8 @@
watchdogZeroEvent.when(), parent->clockPeriod(),
watchdogControl.prescalar);
time = watchdogZeroEvent.when() - curTick();
-time = time / parent->clockPeriod() /
-power(16, watchdogControl.prescalar);
+time = (time / parent->clockPeriod()) >>
+(4 * watchdogControl.prescalar);
DPRINTF(Timer, "-- returning counter at %d\n", time);
pkt->setLE(time);
break;
@@ -269,7 +268,7 @@
if (!timerControl.enable)
return;
-Tick time = parent->clockPeriod() * power(16, timerControl.prescalar);
+Tick time = parent->clockPeriod() << (4 * timerControl.prescalar);
time *= val;
if (timerZeroEvent.scheduled()) {
@@ -287,7 +286,7 @@
if (!watchdogControl.enable)
return;
-Tick time = parent->clockPeriod() * power(16,
watchdogControl.prescalar);
+Tick time = parent->clockPeriod() << (4 * watchdogControl.prescalar);
time *= val;
if
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Adding static constexpr keywords to log2i
Attention is currently required from: Giacomo Travaglini, Gabe Black.
Hello kokoro, Giacomo Travaglini, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43239
to review the following change.
Change subject: base: Adding static constexpr keywords to log2i
..
base: Adding static constexpr keywords to log2i
Aligning to the rest of the file
Change-Id: If1e2d120f77843f8fdd4838fdb806a804236e58a
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42543
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/intmath.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 85ee525..ff5753d 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -155,7 +155,7 @@
*
* @ingroup api_base_utils
*/
-inline int
+static constexpr int
log2i(int value)
{
assert(isPowerOf2(value) && value > 0);
--
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Gerrit-Change-Id: If1e2d120f77843f8fdd4838fdb806a804236e58a
Gerrit-Change-Number: 43239
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Add log2i to calculate log2 for integers
Attention is currently required from: Daniel Carvalho, Giacomo Travaglini.
Hello kokoro, Daniel Carvalho, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43234
to review the following change.
Change subject: base: Add log2i to calculate log2 for integers
..
base: Add log2i to calculate log2 for integers
This is meant to evaluate the log2 for power of 2 integers
Change-Id: Iaa110cce4d36c578a201c8a45e9e2e3a369ffb30
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41494
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/base/intmath.hh
M src/base/intmath.test.cc
2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index acf7681..ba20177 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2001, 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -33,6 +45,7 @@
#include
#include
+#include "base/bitfield.hh"
#include "base/logging.hh"
#include "base/types.hh"
@@ -154,4 +167,19 @@
return val & ~mask;
}
+/**
+ * Calculate the log2 of a power of 2 integer
+ *
+ * @param An input value
+ * @return The base 2 log of value
+ *
+ * @ingroup api_base_utils
+ */
+inline int
+log2i(int value)
+{
+assert(isPowerOf2(value) && value > 0);
+return ctz32(value);
+}
+
#endif // __BASE_INTMATH_HH__
diff --git a/src/base/intmath.test.cc b/src/base/intmath.test.cc
index e985a1b..e953a7e 100644
--- a/src/base/intmath.test.cc
+++ b/src/base/intmath.test.cc
@@ -1,4 +1,15 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2019 The Regents of the University of California
* All rights reserved
*
@@ -123,3 +134,47 @@
EXPECT_EQ(4096, roundDown(4101, 16));
EXPECT_EQ(7936, roundDown(7991, 256));
}
+
+/** This is testing if log2i actually works.
+ * at every iteration value is multiplied by 2 (left shift) and expected
+ * is incremented by one. This until value reaches becomes negative (by
+ * left shifting) which is when expected points to the MSB
+ */
+TEST(IntmathTest, Log2i)
+{
+int expected = 0;
+for (int value = 1; value > 0; expected++, value <<= 1) {
+EXPECT_EQ(expected, log2i(value));
+}
+
+// Just as a sanity check for expected to point to the MSB
+EXPECT_EQ(expected, sizeof(int) * 8 - 1);
+}
+
+/** This is testing the assertions: what if invalid arguments are
+ * provided to log2i:
+ *
+ * 1) value = 0
+ * 2) value < 0
+ * 3) value is not a power of 2
+ */
+TEST(IntmathDeathTest, Log2iDeath)
+{
+// 1) value = 0
+EXPECT_DEATH({
+const int value = 0;
+log2i(value);
+}, "value > 0.*failed");
+
+// 2) value < 0
+EXPECT_DEATH({
+const int value = -1;
+log2i(value);
+}, "value > 0.*failed");
+
+// 3) value is not a power of 2
+EXPECT_DEATH({
+const int value = 5;
+log2i(value);
+}, "isPowerOf2");
+}
--
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Gerrit-Change-Number: 43234
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Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Make the functions in intmath.hh constexpr.
Attention is currently required from: Daniel Carvalho.
Hello kokoro, Daniel Carvalho,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43233
to review the following change.
Change subject: base: Make the functions in intmath.hh constexpr.
..
base: Make the functions in intmath.hh constexpr.
These simple functions can potentially be evaluated at compile time, and
marking them constexpr makes them available in more contexts.
Change-Id: I9cf39c517e7c53c276883f311739c1b153ccfd44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42357
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/base/intmath.hh
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 473f0e3..acf7681 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -39,7 +39,7 @@
/**
* @ingroup api_base_utils
*/
-inline uint64_t
+static constexpr uint64_t
power(uint32_t n, uint32_t e)
{
uint64_t result = 1;
@@ -59,7 +59,7 @@
* @ingroup api_base_utils
*/
template
-inline typename std::enable_if_t::value, int>
+static constexpr std::enable_if_t::value, int>
floorLog2(T x)
{
assert(x > 0);
@@ -84,7 +84,7 @@
* @ingroup api_base_utils
*/
template
-inline int
+static constexpr int
ceilLog2(const T& n)
{
assert(n > 0);
@@ -98,7 +98,7 @@
* @ingroup api_base_utils
*/
template
-inline bool
+static constexpr bool
isPowerOf2(const T& n)
{
// If n is non-zero, and subtracting one borrows all the way to the MSB
@@ -110,7 +110,7 @@
* @ingroup api_base_utils
*/
template
-inline T
+static constexpr T
divCeil(const T& a, const U& b)
{
return (a + b - 1) / b;
@@ -127,7 +127,7 @@
* @ingroup api_base_utils
*/
template
-inline T
+static constexpr T
roundUp(const T& val, const U& align)
{
assert(isPowerOf2(align));
@@ -146,7 +146,7 @@
* @ingroup api_base_utils
*/
template
-inline T
+static constexpr T
roundDown(const T& val, const U& align)
{
assert(isPowerOf2(align));
--
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Gerrit-Change-Number: 43233
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: mem: Fix some transitive includes.
Attention is currently required from: Daniel Carvalho.
Hello kokoro, Daniel Carvalho,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43235
to review the following change.
Change subject: mem: Fix some transitive includes.
..
mem: Fix some transitive includes.
Some headers were including base/logging.hh transitively and
accidentally through base/intmath.hh. Make the includes explicit and
direct.
Change-Id: Ie5852abaf32b3fba5001d29b3d0546103ee492b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42503
Reviewed-by: Daniel Carvalho
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/mem/ruby/common/Histogram.cc
M src/mem/stack_dist_calc.cc
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/common/Histogram.cc
b/src/mem/ruby/common/Histogram.cc
index a6569ad..5c7630e 100644
--- a/src/mem/ruby/common/Histogram.cc
+++ b/src/mem/ruby/common/Histogram.cc
@@ -32,6 +32,7 @@
#include
#include "base/intmath.hh"
+#include "base/logging.hh"
Histogram::Histogram(int binsize, uint32_t bins)
{
diff --git a/src/mem/stack_dist_calc.cc b/src/mem/stack_dist_calc.cc
index 2557bea..280e9cd 100644
--- a/src/mem/stack_dist_calc.cc
+++ b/src/mem/stack_dist_calc.cc
@@ -39,6 +39,7 @@
#include "base/chunk_generator.hh"
#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/StackDist.hh"
--
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Gerrit-Change-Number: 43235
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: cpu: Remove "lane" accessors from the ExecContext classes.
Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43230
to review the following change.
Change subject: cpu: Remove "lane" accessors from the ExecContext classes.
..
cpu: Remove "lane" accessors from the ExecContext classes.
These are not used by instructions. If something other than instructions
needs that style of access, it would use the ThreadContext, not the
ExecContext.
Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41897
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/exec_context.hh
5 files changed, 0 insertions(+), 316 deletions(-)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 42a38fc..0900125 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -218,79 +218,6 @@
return thread->getWritableVecReg(reg);
}
-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec8BitLaneReg(reg);
-}
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec16BitLaneReg(reg);
-}
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec32BitLaneReg(reg);
-}
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneOperand(const StaticInst *si, int idx) const override
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVec64BitLaneReg(reg);
-}
-
-/** Write a lane of the destination vector operand. */
-template
-void
-setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-{
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->setVecLane(reg, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{
-setVecLaneOperandT(si, idx, val);
-}
-/** @} */
-
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 42dafbc..3c40f31 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -117,36 +117,6 @@
const TheISA::VecRegContainer& val) = 0;
/** @} */
-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8 readVec8BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16 readVec16BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32 readVec32BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64 readVec64BitLaneOperand(
-const StaticInst *si, int idx) const = 0;
-
-/** Write a lane of the destination vector operand. */
-/** @{ */
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-virtual void setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) = 0;
-/** @} */
-
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43224
to review the following change.
Change subject: arch,arch-arm: Eliminate the "zeroing" field of vec reg
elements.
..
arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.
This field wasn't used for anything.
Change-Id: I81f38743a7b4f87c56adb8ffeda6f9a096d09842
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41895
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/operand_types.py
2 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f18ffd..da78561 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -131,8 +131,8 @@
def vectorReg(idx, elems = None):
return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
-def vectorRegElem(elem, ext = 'sf', zeroing = False):
-return (elem, ext, zeroing)
+def vectorRegElem(elem, ext = 'sf'):
+return (elem, ext)
def vecPredReg(idx):
return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -354,9 +354,9 @@
'AA64FpOp1P1': vectorRegElem('1'),
'AA64FpOp1P2': vectorRegElem('2'),
'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1S': vectorRegElem('0', 'sf'),
+'AA64FpOp1D': vectorRegElem('0', 'df'),
+'AA64FpOp1Q': vectorRegElem('0', 'tud')
}),
'AA64FpOp2': vectorReg('op2',
@@ -365,9 +365,9 @@
'AA64FpOp2P1': vectorRegElem('1'),
'AA64FpOp2P2': vectorRegElem('2'),
'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp2S': vectorRegElem('0', 'sf'),
+'AA64FpOp2D': vectorRegElem('0', 'df'),
+'AA64FpOp2Q': vectorRegElem('0', 'tud')
}),
'AA64FpOp3': vectorReg('op3',
@@ -376,9 +376,9 @@
'AA64FpOp3P1': vectorRegElem('1'),
'AA64FpOp3P2': vectorRegElem('2'),
'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp3S': vectorRegElem('0', 'sf'),
+'AA64FpOp3D': vectorRegElem('0', 'df'),
+'AA64FpOp3Q': vectorRegElem('0', 'tud')
}),
'AA64FpDest': vectorReg('dest',
@@ -387,9 +387,9 @@
'AA64FpDestP1': vectorRegElem('1'),
'AA64FpDestP2': vectorRegElem('2'),
'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDestS': vectorRegElem('0', 'sf'),
+'AA64FpDestD': vectorRegElem('0', 'df'),
+'AA64FpDestQ': vectorRegElem('0', 'tud')
}),
'AA64FpDest2': vectorReg('dest2',
@@ -398,9 +398,9 @@
'AA64FpDest2P1': vectorRegElem('1'),
'AA64FpDest2P2': vectorRegElem('2'),
'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpDest2S': vectorRegElem('0', 'sf'),
+'AA64FpDest2D': vectorRegElem('0', 'df'),
+'AA64FpDest2Q': vectorRegElem('0', 'tud')
}),
'AA64FpOp1V0': vectorReg('op1',
@@ -409,9 +409,9 @@
'AA64FpOp1P1V0': vectorRegElem('1'),
'AA64FpOp1P2V0': vectorRegElem('2'),
'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
-'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpOp1SV0': vectorRegElem('0', 'sf'),
+'AA64FpOp1DV0': vectorRegElem('0', 'df'),
+'AA64FpOp1QV0': vectorRegElem('0', 'tud')
}),
'AA64FpOp1V1': vectorReg('op1+1',
@@ -420,9 +420,9 @@
'AA64FpOp1P1V1': vectorRegElem('1'),
'AA64FpOp1P2V1': vectorRegElem('2'),
'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
-
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: sim: Simplify some code in the guest ABI mechanism.
Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43228
to review the following change.
Change subject: sim: Simplify some code in the guest ABI mechanism.
..
sim: Simplify some code in the guest ABI mechanism.
Instead of using recursively applied templates to accumulate a series of
wrapper lambdas which dispatch to a call, use pure parameter pack
expansion. This has two benefits. One, it makes the code simpler(ish) and
easier to understand. The parameter pack machinery is still intrinsically
fairly tricky, but there's less of it and it's a fairly straightforward
application of that mechanism.
Also, a nice side benefit is that the template for simcall dispatch will
expand to a small fixed number of functions which do all their work
locally, instead of having a new function for each layer of the onion,
one per parameter, and no calls through lambdas. That should hopefully
make debugging easier, and produce less bookkeeping overhead as far as
really long names, lots of functions, etc.
This code, specifically the code in dispatch.hh, can be simplified even
further in the future once we start using c++17 which is if constexpr,
and std::apply which explodes a tuple and uses its components as
arguments to a function, something I'm doing manually here.
Change-Id: If7c9234cc1014101211474c2ec20362702cf78c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41600
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/guest_abi.hh
M src/sim/guest_abi/dispatch.hh
M src/sim/guest_abi/layout.hh
3 files changed, 48 insertions(+), 112 deletions(-)
diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index ea3325f..75c4e00 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -51,7 +51,7 @@
// types will be zero initialized.
auto state = GuestABI::initializeState(tc);
GuestABI::prepareForFunction(tc, state);
-return GuestABI::callFrom(tc, state,
target);
+return GuestABI::callFrom(tc, state,
target);
}
template
@@ -86,7 +86,7 @@
// types will be zero initialized.
auto state = GuestABI::initializeState(tc);
GuestABI::prepareForArguments(tc, state);
-GuestABI::callFrom(tc, state, target);
+GuestABI::callFrom(tc, state, target);
}
template
@@ -113,7 +113,7 @@
GuestABI::prepareForFunction(tc, state);
ss << name;
-GuestABI::dumpArgsFrom(0, ss, tc, state);
+GuestABI::dumpArgsFrom(ss, tc, state);
return ss.str();
}
diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh
index bc365b9..8f3a4ac 100644
--- a/src/sim/guest_abi/dispatch.hh
+++ b/src/sim/guest_abi/dispatch.hh
@@ -30,8 +30,11 @@
#include
#include
+#include
#include
+#include
+#include "base/compiler.hh"
#include "sim/guest_abi/definition.hh"
#include "sim/guest_abi/layout.hh"
@@ -50,114 +53,60 @@
* still possible to support by redefining these functions..
*/
-// With no arguments to gather, call the target function and store the
-// result.
-template
-static typename std::enable_if_t::value && store_ret,
Ret>
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+template
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args
&,
+std::index_sequence)
{
-Ret ret = target(tc);
+return target(tc, std::get(args)...);
+}
+
+template
+static inline typename std::enable_if_t
+callFromHelper(Target , ThreadContext *tc, State , Args
&,
+std::index_sequence)
+{
+Ret ret = target(tc, std::get(args)...);
storeResult(tc, ret, state);
return ret;
}
-template
-static typename std::enable_if_t::value && !store_ret,
Ret>
+template
+static inline Ret
callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
+std::function target)
{
-return target(tc);
+// Extract all the arguments from the thread context. Braced
initializers
+// are evaluated from left to right.
+auto args = std::tuple{getArgument(tc, state)...};
+
+// Call the wrapper which will call target.
+return callFromHelper(
+target, tc, state, std::move(args),
+std::make_index_sequence{});
}
-// With no arguments to gather and nothing to return, call the target
function.
-template
-static void
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-target(tc);
-}
-
-// Recursively gather arguments for target from tc until we get to the base
-// case above.
-template
-static typename std::enable_if_t::value, Ret>
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-// Extract the next argument from the thread context.
-NextArg next = getArgument(tc, state);
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-arm: Consolidate defintions of vectorReg operands.
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43225
to review the following change.
Change subject: arch-arm: Consolidate defintions of vectorReg operands.
..
arch-arm: Consolidate defintions of vectorReg operands.
Each vectorReg operand defined a set of seven elements which all
followed a very predictable pattern. Since we already have a small
utility function to help generate those definitions, we can just
generate the elements at the same time and save a lot of boilerplate.
Change-Id: I065c6c319612b79c53570b313bf5ad8770796252
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41896
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/operands.isa
1 file changed, 36 insertions(+), 278 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index da78561..f50144e 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -128,11 +128,17 @@
def vectorElem(idx, elem):
return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
-def vectorReg(idx, elems = None):
-return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
-
-def vectorRegElem(elem, ext = 'sf'):
-return (elem, ext)
+def vectorReg(idx, base, suffix = ''):
+elems = {
+base + 'P0' + suffix : ('0', 'sf'),
+base + 'P1' + suffix : ('1', 'sf'),
+base + 'P2' + suffix : ('2', 'sf'),
+base + 'P3' + suffix : ('3', 'sf'),
+base + 'S' + suffix : ('0', 'sf'),
+base + 'D' + suffix : ('0', 'df'),
+base + 'Q' + suffix : ('0', 'tud')
+}
+return ('VecReg', 'vc', (idx, elems), 'IsVector', srtNormal)
def vecPredReg(idx):
return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -348,281 +354,33 @@
# All the constituents are hierarchically defined as part of the Vector
# Register they belong to
-'AA64FpOp1': vectorReg('op1',
-{
-'AA64FpOp1P0': vectorRegElem('0'),
-'AA64FpOp1P1': vectorRegElem('1'),
-'AA64FpOp1P2': vectorRegElem('2'),
-'AA64FpOp1P3': vectorRegElem('3'),
-'AA64FpOp1S': vectorRegElem('0', 'sf'),
-'AA64FpOp1D': vectorRegElem('0', 'df'),
-'AA64FpOp1Q': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp2': vectorReg('op2',
-{
-'AA64FpOp2P0': vectorRegElem('0'),
-'AA64FpOp2P1': vectorRegElem('1'),
-'AA64FpOp2P2': vectorRegElem('2'),
-'AA64FpOp2P3': vectorRegElem('3'),
-'AA64FpOp2S': vectorRegElem('0', 'sf'),
-'AA64FpOp2D': vectorRegElem('0', 'df'),
-'AA64FpOp2Q': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp3': vectorReg('op3',
-{
-'AA64FpOp3P0': vectorRegElem('0'),
-'AA64FpOp3P1': vectorRegElem('1'),
-'AA64FpOp3P2': vectorRegElem('2'),
-'AA64FpOp3P3': vectorRegElem('3'),
-'AA64FpOp3S': vectorRegElem('0', 'sf'),
-'AA64FpOp3D': vectorRegElem('0', 'df'),
-'AA64FpOp3Q': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest': vectorReg('dest',
-{
-'AA64FpDestP0': vectorRegElem('0'),
-'AA64FpDestP1': vectorRegElem('1'),
-'AA64FpDestP2': vectorRegElem('2'),
-'AA64FpDestP3': vectorRegElem('3'),
-'AA64FpDestS': vectorRegElem('0', 'sf'),
-'AA64FpDestD': vectorRegElem('0', 'df'),
-'AA64FpDestQ': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDest2': vectorReg('dest2',
-{
-'AA64FpDest2P0': vectorRegElem('0'),
-'AA64FpDest2P1': vectorRegElem('1'),
-'AA64FpDest2P2': vectorRegElem('2'),
-'AA64FpDest2P3': vectorRegElem('3'),
-'AA64FpDest2S': vectorRegElem('0', 'sf'),
-'AA64FpDest2D': vectorRegElem('0', 'df'),
-'AA64FpDest2Q': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V0': vectorReg('op1',
-{
-'AA64FpOp1P0V0': vectorRegElem('0'),
-'AA64FpOp1P1V0': vectorRegElem('1'),
-'AA64FpOp1P2V0': vectorRegElem('2'),
-'AA64FpOp1P3V0': vectorRegElem('3'),
-'AA64FpOp1SV0': vectorRegElem('0', 'sf'),
-'AA64FpOp1DV0': vectorRegElem('0', 'df'),
-'AA64FpOp1QV0': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V1': vectorReg('op1+1',
-{
-'AA64FpOp1P0V1': vectorRegElem('0'),
-'AA64FpOp1P1V1': vectorRegElem('1'),
-'AA64FpOp1P2V1': vectorRegElem('2'),
-'AA64FpOp1P3V1': vectorRegElem('3'),
-'AA64FpOp1SV1': vectorRegElem('0', 'sf'),
-'AA64FpOp1DV1': vectorRegElem('0', 'df'),
-'AA64FpOp1QV1': vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOp1V2': vectorReg('op1+2',
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: cpu: Style fixes in the base and O3 dynamic inst classes.
Attention is currently required from: Daniel Carvalho.
Hello kokoro, Daniel Carvalho,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43226
to review the following change.
Change subject: cpu: Style fixes in the base and O3 dynamic inst classes.
..
cpu: Style fixes in the base and O3 dynamic inst classes.
Change-Id: Idfd8e71856931fa101e00c58a2aa4018d076
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42093
Reviewed-by: Daniel Carvalho
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/dyn_inst.hh
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 68a6bb3..a5a842a 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -729,8 +729,11 @@
OpClass opClass() const { return staticInst->opClass(); }
/** Returns the branch target address. */
-TheISA::PCState branchTarget() const
-{ return staticInst->branchTarget(pc); }
+TheISA::PCState
+branchTarget() const
+{
+return staticInst->branchTarget(pc);
+}
/** Returns the number of source registers. */
size_t numSrcRegs() const { return regs.numSrcs(); }
@@ -1016,11 +1019,15 @@
/** Return whether dest registers' pinning status updated after squash
*/
bool
-isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
+isPinnedRegsSquashDone() const
+{
+return status[PinnedRegsSquashDone];
+}
/** Sets dest registers' status updated after squash */
void
-setPinnedRegsSquashDone() {
+setPinnedRegsSquashDone()
+{
assert(!status[PinnedRegsSquashDone]);
status.set(PinnedRegsSquashDone);
}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f084368..7a54c7f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -184,37 +184,37 @@
this->thread->noSquashFromTC = no_squash_from_TC;
}
-void forwardOldRegs()
+void
+forwardOldRegs()
{
for (int idx = 0; idx < this->numDestRegs(); idx++) {
PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
-const RegId& original_dest_reg =
-this->staticInst->destRegIdx(idx);
+const RegId& original_dest_reg =
this->staticInst->destRegIdx(idx);
switch (original_dest_reg.classValue()) {
case IntRegClass:
this->setIntRegOperand(this->staticInst.get(), idx,
- this->cpu->readIntReg(prev_phys_reg));
+this->cpu->readIntReg(prev_phys_reg));
break;
case FloatRegClass:
this->setFloatRegOperandBits(this->staticInst.get(), idx,
- this->cpu->readFloatReg(prev_phys_reg));
+this->cpu->readFloatReg(prev_phys_reg));
break;
case VecRegClass:
this->setVecRegOperand(this->staticInst.get(), idx,
- this->cpu->readVecReg(prev_phys_reg));
+this->cpu->readVecReg(prev_phys_reg));
break;
case VecElemClass:
this->setVecElemOperand(this->staticInst.get(), idx,
- this->cpu->readVecElem(prev_phys_reg));
+this->cpu->readVecElem(prev_phys_reg));
break;
case VecPredRegClass:
this->setVecPredRegOperand(this->staticInst.get(), idx,
- this->cpu->readVecPredReg(prev_phys_reg));
+this->cpu->readVecPredReg(prev_phys_reg));
break;
case CCRegClass:
this->setCCRegOperand(this->staticInst.get(), idx,
- this->cpu->readCCReg(prev_phys_reg));
+this->cpu->readCCReg(prev_phys_reg));
break;
case MiscRegClass:
// no need to forward misc reg values
@@ -309,25 +309,25 @@
{
return cpu->template setVecLane(this->regs.renamedDestIdx(idx),
val);
}
-virtual void
+void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData& val) override
{
return setVecLaneOperandT(si, idx, val);
}
-virtual void
+void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData& val) override
{
return setVecLaneOperandT(si, idx, val);
}
-virtual void
+void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData& val) override
{
return setVecLaneOperandT(si, idx, val);
}
-virtual void
+void
setVecLaneOperand(const StaticInst *si, int idx,
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().
Attention is currently required from: Giacomo Travaglini.
Hello kokoro, Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43229
to review the following change.
Change subject: arch-arm: Switch the AAPCS ABIs to .as<>() instead
of .laneView<>().
..
arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().
Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41898
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..c450237 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -463,7 +463,7 @@
RegId id(VecRegClass, 0);
auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
tc->setVecReg(id, reg);
};
};
@@ -487,7 +487,7 @@
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
-return val.laneView(lane);
+return val.as()[lane];
}
return loadFromStack(tc, state);
@@ -558,7 +558,7 @@
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
-ha[i] = val.laneView(lane);
+ha[i] = val.as()[lane];
}
return ha;
}
@@ -605,7 +605,7 @@
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
-val.laneView(lane) = ha[i];
+val.as()[lane] = ha[i];
tc->setVecReg(id, val);
}
}
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..ddd5606 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -186,7 +186,7 @@
{
if (state.nsrn <= state.MAX_SRN) {
RegId id(VecRegClass, state.nsrn++);
-return tc->readVecReg(id).laneView();
+return tc->readVecReg(id).as()[0];
}
return loadFromStack(tc, state);
@@ -203,7 +203,7 @@
{
RegId id(VecRegClass, 0);
auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
tc->setVecReg(id, reg);
}
};
--
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Gerrit-Change-Number: 43229
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-mips: Fix a bug in the MIPS yield instruction.
Attention is currently required from: Boris Shingarov.
Hello kokoro, Boris Shingarov,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43231
to review the following change.
Change subject: arch-mips: Fix a bug in the MIPS yield instruction.
..
arch-mips: Fix a bug in the MIPS yield instruction.
The yieldThread function implements MIPS's yield instruction, and had a
if condition in it, (src_reg && !yield_mask != 0), which upset clang. When
originally committed, this check read (src_reg & !yield_mask != 0), but
apparently as part of a cleanup sweep a long time ago, it was assumed
that the & was being used as a logical operator and was turned into &&.
Reading the actual description of what the yield instruction is supposed
to do, if src_reg is positive (it is at this point in the function),
then it's supposed to be treated as a bitvector. The YQMask register,
what gets passed in as yield_mask, can have bits set in it which mask
bits that might be set in src_reg, and if any are still set, the an
interrupt should happen, as implemented by the body of the if.
From this description, it's apparent that what the original code was
*trying* to do was to use yield_mask to mask any set bits in src_reg,
and then if any bits were left go into the body. The original author
used ! as a bitwise negating operator since what they *wanted* to do was
to block any bits in src_reg where yield_mask *is* set, and let through
any where yield_mask *is not* set. The & would do that, but only with a
bitwise negated yield_mask. Hence:
if ((src_reg & ~yield_mask) != 0) {
...
}
Change-Id: I30d0a47992750adf78c8aa0c28217da187e0cbda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40957
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Boris Shingarov
---
M src/arch/mips/mt.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 9ab3290..da4c51a 100644
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -273,7 +273,7 @@
curTick(), tc->threadId());
}
} else if (src_reg > 0) {
-if (src_reg && !yield_mask != 0) {
+if ((src_reg & ~yield_mask) != 0) {
VPEControlReg vpeControl =
tc->readMiscReg(MISCREG_VPE_CONTROL);
vpeControl.excpt = 2;
tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
--
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Gerrit-Change-Number: 43231
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Add a macro to expand parameter pack expressions in order.
Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43227
to review the following change.
Change subject: base: Add a macro to expand parameter pack expressions in
order.
..
base: Add a macro to expand parameter pack expressions in order.
This wraps up the strange compiler goop necessary to evaluate
expressions based on parameter pack expansions in order.
Change-Id: I16fbd53d22492a8c20524e3ef8bb8ff5e5d59b14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42033
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/compiler.hh
1 file changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 643352c..c003bfa 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -112,6 +112,16 @@
// we can't do that with direct substitution.
# define M5_LIKELY(cond) __builtin_expect(!!(cond), 1)
# define M5_UNLIKELY(cond) __builtin_expect(!!(cond), 0)
+
+// Evaluate an expanded parameter pack in order. Multiple arguments can be
+// passed in which be evaluated in order relative to each other as a group.
+// The argument(s) must include a parameter pack to expand. This works
because
+// the elements of a brace inclosed initializer list are evaluated in
order,
+// as are the arguments to the comma operator, which evaluates to the last
+// value. This is compiler specific because it uses variadic macros.
+#define M5_FOR_EACH_IN_PACK(...) \
+do { M5_VAR_USED int i[] = { 0, ((void)(__VA_ARGS__), 0)... }; } while
(false)
+
#else
# error "Don't know what to do for your compiler."
#endif
--
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-sparc: Fix an operator precedence bug in the iob device.
Attention is currently required from: Boris Shingarov.
Hello kokoro, Boris Shingarov,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43232
to review the following change.
Change subject: arch-sparc: Fix an operator precedence bug in the iob
device.
..
arch-sparc: Fix an operator precedence bug in the iob device.
Like in the nomali library, this bug is in some code making a bitmask
where what bits are enabled depends on some conditions. It used ?: to
evaluate the conditions and | to aggregate the bits, but didn't use any
()s, so the | happened first, then the ?:s. This would generate an
incorrect bitmask.
Change-Id: Iabcc8a9fd38cde5de3c0627a3b143407247c0c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40955
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Boris Shingarov
---
M src/dev/sparc/iob.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index a0d1982..624563e 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -101,8 +101,8 @@
if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr +
IntCtlSize) {
int index = (accessAddr - IntCtlAddr) >> 3;
-uint64_t data = intCtl[index].mask ? 1 << 2 : 0 |
-intCtl[index].pend ? 1 << 0 : 0;
+uint64_t data = (intCtl[index].mask ? (1 << 2) : 0) |
+(intCtl[index].pend ? (1 << 0) : 0);
pkt->setBE(data);
return;
}
--
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: base: Remove DDUMPN
Attention is currently required from: Daniel Carvalho, Gabe Black.
Hello kokoro, Daniel Carvalho, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/43223
to review the following change.
Change subject: base: Remove DDUMPN
..
base: Remove DDUMPN
It is not used in the codebase. It has been broken (not compilable)
since commit 105b2c8914946867f040caf6a8ff7da3c5d028d7.
Change-Id: I6fe048910ad1d39b6b10af509ba84aab1792b8fb
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41335
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
---
M src/base/trace.hh
1 file changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/base/trace.hh b/src/base/trace.hh
index f7c0066..b5d579d 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -172,7 +172,6 @@
* \def DPRINTF(x, ...)
* \def DPRINTFS(x, s, ...)
* \def DPRINTFR(x, ...)
- * \def DDUMPN(data, count)
* \def DPRINTFN(...)
* \def DPRINTFNR(...)
* \def DPRINTF_UNCONDITIONAL(x, ...)
@@ -214,10 +213,6 @@
} \
} while (0)
-#define DDUMPN(data, count) do { \
-Trace::getDebugLogger()->dump(curTick(), name(), data, count); \
-} while (0)
-
#define DPRINTFN(...) do { \
Trace::getDebugLogger()->dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
@@ -237,7 +232,6 @@
#define DPRINTF(x, ...) do {} while (0)
#define DPRINTFS(x, ...) do {} while (0)
#define DPRINTFR(...) do {} while (0)
-#define DDUMPN(data, count) do {} while (0)
#define DPRINTFN(...) do {} while (0)
#define DPRINTFNR(...) do {} while (0)
#define DPRINTF_UNCONDITIONAL(x, ...) do {} while (0)
--
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Gerrit-Change-Number: 43223
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Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.
Peter Yuen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39816 ) Change subject: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses. .. arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses. readMiscRegNoEffect reads directly from the misc reg file. However, MIP and MIE actually reads directly from the interrupt controller and does not store the values in the misc reg file. As such, readMiscReg should be used instead. Change-Id: I6bd71da5c83e12c06043889bdbef7e4c0cf78190 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39816 Reviewed-by: Bobby R. Bruce Reviewed-by: Ayaz Akram Maintainer: Bobby R. Bruce Tested-by: kokoro --- M src/arch/riscv/remote_gdb.cc 1 file changed, 18 insertions(+), 18 deletions(-) Approvals: Ayaz Akram: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 021b388..da78957 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -211,7 +211,7 @@ // U mode CSR r.ustatus = context->readMiscRegNoEffect( CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS); -r.uie = context->readMiscRegNoEffect( +r.uie = context->readMiscReg( CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE); r.utvec = context->readMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex); @@ -223,7 +223,7 @@ CSRData.at(CSR_UCAUSE).physIndex); r.utval = context->readMiscRegNoEffect( CSRData.at(CSR_UTVAL).physIndex); -r.uip = context->readMiscRegNoEffect( +r.uip = context->readMiscReg( CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP); // S mode CSR @@ -233,7 +233,7 @@ CSRData.at(CSR_SEDELEG).physIndex); r.sideleg = context->readMiscRegNoEffect( CSRData.at(CSR_SIDELEG).physIndex); -r.sie = context->readMiscRegNoEffect( +r.sie = context->readMiscReg( CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE); r.stvec = context->readMiscRegNoEffect( CSRData.at(CSR_STVEC).physIndex); @@ -247,7 +247,7 @@ CSRData.at(CSR_SCAUSE).physIndex); r.stval = context->readMiscRegNoEffect( CSRData.at(CSR_STVAL).physIndex); -r.sip = context->readMiscRegNoEffect( +r.sip = context->readMiscReg( CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP); r.satp = context->readMiscRegNoEffect( CSRData.at(CSR_SATP).physIndex); @@ -269,7 +269,7 @@ CSRData.at(CSR_MEDELEG).physIndex); r.mideleg = context->readMiscRegNoEffect( CSRData.at(CSR_MIDELEG).physIndex); -r.mie = context->readMiscRegNoEffect( +r.mie = context->readMiscReg( CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE); r.mtvec = context->readMiscRegNoEffect( CSRData.at(CSR_MTVEC).physIndex); @@ -283,7 +283,7 @@ CSRData.at(CSR_MCAUSE).physIndex); r.mtval = context->readMiscRegNoEffect( CSRData.at(CSR_MTVAL).physIndex); -r.mip = context->readMiscRegNoEffect( +r.mip = context->readMiscReg( CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP); // H mode CSR (to be implemented) @@ -340,11 +340,11 @@ newVal = (oldVal & ~mask) | (r.ustatus & mask); context->setMiscRegNoEffect( CSRData.at(CSR_USTATUS).physIndex, newVal); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_UIE).physIndex); mask = CSRMasks.at(CSR_UIE); newVal = (oldVal & ~mask) | (r.uie & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_UIE).physIndex, newVal); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); @@ -356,11 +356,11 @@ CSRData.at(CSR_UCAUSE).physIndex, r.ucause); context->setMiscRegNoEffect( CSRData.at(CSR_UTVAL).physIndex, r.utval); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_UIP).physIndex); mask = CSRMasks.at(CSR_UIP); newVal = (oldVal & ~mask) | (r.uip & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_UIP).physIndex, newVal); // S mode CSR @@ -374,11 +374,11 @@ CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( CSRData.at(CSR_SIDELEG).physIndex, r.sideleg); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_SIE).physIndex); mask = CSRMasks.at(CSR_SIE); newVal = (oldVal & ~mask) | (r.sie & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_SIE).physIndex, newVal); context->setMiscRegNoEffect( CSRData.at(CSR_STVEC).physIndex, r.stvec);
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added DTB Generation Functionality to RISC-V FS
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42053 )
Change subject: arch-riscv: Added DTB Generation Functionality to RISC-V FS
..
arch-riscv: Added DTB Generation Functionality to RISC-V FS
Changes:
1. RiscvBareMetal
The RiscvBareMetal class and API are preserved for backwards
compatibility, but the base class RiscvFSWorkload is removed
as it inherits from the Workload class. However, most needed
functionalities are already implemented in the KernelWorkload
class
2. RiscvLinux
The RiscvLinux class is added. A dtb filename can be specified
to be loaded to the corresponding memory address.
3. HiFive, Clint, Plic, Uart8250, VirtIOMMIO
Devicetree node generation function is added.
4. tlb, faults
Unnecessary includes of arch/riscv/fs_workload are removed.
Change-Id: Ia239b5614bd93d8e794330ead266f6121a4d13cb
---
M configs/example/riscv/fs_linux.py
M src/arch/riscv/RiscvFsWorkload.py
M src/arch/riscv/SConscript
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/faults.cc
A src/arch/riscv/linux/fs_workload.cc
R src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/tlb.cc
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/PlicDevice.py
M src/dev/riscv/VirtIOMMIO.py
M src/dev/serial/Uart.py
15 files changed, 305 insertions(+), 56 deletions(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 3d40061..8f059ba 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -40,6 +40,7 @@
import optparse
import sys
+from os import path
import m5
from m5.defines import buildEnv
@@ -62,6 +63,43 @@
from common.Caches import *
from common import Options
+
+def generateMemNode(state, mem_range):
+node = FdtNode("memory@%x" % int(mem_range.start))
+node.append(FdtPropertyStrings("device_type", ["memory"]))
+node.append(FdtPropertyWords("reg",
+state.addrCells(mem_range.start) +
+state.sizeCells(mem_range.size()) ))
+return node
+
+def generateDtb(system):
+"""
+Autogenerate DTB. Arguments are the folder where the DTB
+will be stored, and the name of the DTB file.
+"""
+state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
+root = FdtNode('/')
+root.append(state.addrCellsProperty())
+root.append(state.sizeCellsProperty())
+root.appendCompatible(["riscv-virtio"])
+
+for mem_range in system.mem_ranges:
+root.append(generateMemNode(state, mem_range))
+
+sections = [*system.cpu, system.platform]
+
+for section in sections:
+for node in section.generateDeviceTree(state):
+if node.get_name() == root.get_name():
+root.merge(node)
+else:
+root.append(node)
+
+fdt = Fdt()
+fdt.add_rootnode(root)
+fdt.writeDtsFile(path.join(m5.options.outdir, 'device.dts'))
+fdt.writeDtbFile(path.join(m5.options.outdir, 'device.dtb'))
+
# - Add Options #
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
@@ -92,12 +130,12 @@
system.mem_mode = mem_mode
system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
-system.workload = RiscvBareMetal()
+system.workload = RiscvLinux()
system.iobus = IOXBar()
system.membus = MemBus()
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
system.intrctrl = IntrControl()
@@ -147,7 +185,7 @@
voltage_domain =
system.cpu_voltage_domain)
-system.workload.bootloader = options.kernel
+system.workload.object_file = options.kernel
# NOTE: Not yet tested
if options.script is not None:
@@ -161,12 +199,12 @@
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
system.iocache = IOCache(addr_ranges = system.mem_ranges)
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
+system.iocache.cpu_side = system.iobus.mem_side_ports
+system.iocache.mem_side = system.membus.cpu_side_ports
elif not options.external_memory_system:
system.iobridge = Bridge(delay='50ns', ranges = system.mem_ranges)
-system.iobridge.slave = system.iobus.master
-system.iobridge.master = system.membus.slave
+system.iobridge.cpu_side_ports = system.iobus.mem_side_ports
+system.iobridge.mem_side_ports = system.membus.cpu_side_ports
# Sanity check
if options.simpoint_profile:
@@ -197,13 +235,24 @@
*system.platform._on_chip_ranges(),
*system.platform._off_chip_ranges()
]
-pma_checker = PMAChecker(uncacheable=uncacheable_range)
# PMA checker can be defined at system-level (system.pma_checker)
# or MMU-level
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41933 )
Change subject: arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
..
arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Added takeover methods for PMA Checker and RiscvTLB to ensure
that checkpoint restoration works. Also added logic in PLIC
to prevent posting interrupts to a CPU that has yet to complete
the current interrupt. PLIC's behaviour when a CPU claims another
interrupt before completion is also changed. Now PLIC will return
the uncompleted interrupt ID instead of return 0. This behaviour
is not documented in the specs but is designed this way to avoid
issues from CPU side (especially MinorCPU).
Change-Id: I68eaaf56d2c4d76cc1e0a1e2160f5abe184c2cd5
---
M src/arch/riscv/pma_checker.cc
M src/arch/riscv/pma_checker.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/dev/riscv/plic.cc
5 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index 32cb66d..d36dc1d 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -81,3 +81,9 @@
{
return isUncacheable(pkt->getAddrRange());
}
+
+void
+PMAChecker::takeOverFrom(PMAChecker *old)
+{
+uncacheable = old->uncacheable;
+}
diff --git a/src/arch/riscv/pma_checker.hh b/src/arch/riscv/pma_checker.hh
index 5833dbe..298d4a0 100644
--- a/src/arch/riscv/pma_checker.hh
+++ b/src/arch/riscv/pma_checker.hh
@@ -74,6 +74,8 @@
bool isUncacheable(const AddrRange );
bool isUncacheable(const Addr , const unsigned size);
bool isUncacheable(PacketPtr pkt);
+
+void takeOverFrom(PMAChecker *old);
};
#endif // __ARCH_RISCV_PMA_CHECKER_HH__
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 5109d2a..8d21fe3 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -87,6 +87,13 @@
}
void
+TLB::takeOverFrom(BaseTLB *_old)
+{
+TLB *old = dynamic_cast(_old);
+pma->takeOverFrom(old->pma);
+}
+
+void
TLB::evictLRU()
{
// Find the entry with the lowest (and hence least recently updated)
@@ -519,3 +526,9 @@
readAccesses + writeAccesses)
{
}
+
+Port *
+TLB::getTableWalkerPort()
+{
+return >getPort("port");
+}
\ No newline at end of file
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 8dcf0fc..287d8e7 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -92,7 +92,7 @@
Walker *getWalker();
-void takeOverFrom(BaseTLB *otlb) override {}
+void takeOverFrom(BaseTLB *old) override;
TlbEntry *insert(Addr vpn, const TlbEntry );
void flushAll() override;
@@ -108,6 +108,18 @@
void serialize(CheckpointOut ) const override;
void unserialize(CheckpointIn ) override;
+/**
+ * Get the table walker port. This is used for
+ * migrating port connections during a CPU takeOverFrom()
+ * call. For architectures that do not have a table walker,
+ * NULL is returned, hence the use of a pointer rather than a
+ * reference. For RISC-V this method will always return a valid
+ * port pointer.
+ *
+ * @return A pointer to the walker port
+ */
+Port *getTableWalkerPort() override;
+
Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode);
Fault translateAtomic(const RequestPtr ,
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 60ac192..2183183 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -354,17 +354,18 @@
context_id, max_int_id);
clear(max_int_id);
reg.update(max_int_id);
+return reg.get();
} else {
DPRINTF(Plic,
"Claim already cleared - context: %d, interrupt ID: %d\n",
context_id, max_int_id);
-reg.update(0);
+return 0;
}
} else {
-warn("PLIC claim failed (not completed) - context: %d",
context_id);
-reg.update(0);
+warn("PLIC claim repeated (not completed) - context: %d, last: %d",
+context_id, lastID[context_id]);
+return lastID[context_id];
}
-return reg.get();
}
void
@@ -381,6 +382,7 @@
DPRINTF(Plic,
"Complete - context: %d, interrupt ID: %d\n",
context_id, reg.get());
+updateInt();
}
void
@@ -445,11 +447,11 @@
uint32_t max_id = output.maxID[i];
uint32_t priority = output.maxPriority[i];
uint32_t threshold = registers.threshold[i].get();
-if (priority > threshold && max_id > 0) {
+if (priority > threshold && max_id > 0 && lastID[i] == 0) {
DPRINTF(Plic,
"Int posted - thread: %d, int id: %d, ",
thread_id, int_id);
-DPRINTF(Plic,
+DPRINTFR(Plic,
"pri: %d, thres: %d\n", priority, threshold);
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Implementation of CLINT
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40597 )
Change subject: arch-riscv: Implementation of CLINT
..
arch-riscv: Implementation of CLINT
This patch implements the CLINT device model based
on the SiFive U54MC datasheet. CLINT is modelled to
receive its clock signal via an interrupt pin. A
generic RTC (non-MMIO) is also implemented to provide
this signal at arbitrary frequencies.
isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).
Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40597
Tested-by: kokoro
Reviewed-by: Ayaz Akram
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/riscv/isa.cc
A src/dev/riscv/Clint.py
A src/dev/riscv/RTC.py
A src/dev/riscv/SConscript
A src/dev/riscv/clint.cc
A src/dev/riscv/clint.hh
A src/dev/riscv/rtc.cc
A src/dev/riscv/rtc.hh
8 files changed, 696 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Ayaz Akram: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 98798e7..8d200d4 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -255,7 +255,7 @@
if (hpmCounterEnabled(MISCREG_TIME)) {
DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
std::time(nullptr));
-return std::time(nullptr);
+return readMiscRegNoEffect(MISCREG_TIME);
} else {
warn("Wall clock disabled.\n");
return 0;
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
new file mode 100644
index 000..25b595b
--- /dev/null
+++ b/src/dev/riscv/Clint.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.IntPin import IntSinkPin
+from m5.params import *
+from m5.proxy import *
+
+class Clint(BasicPioDevice):
+"""
+This implementation of CLINT is based on
+the SiFive U54MC datasheet:
+https://sifive.cdn.prismic.io/sifive/fab000f6-
+0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
+full_20G1.03.00_manual.pdf
+"""
+type = 'Clint'
+cxx_header = 'dev/riscv/clint.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+int_pin = IntSinkPin('Pin to receive RTC signal')
+pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/RTC.py b/src/dev/riscv/RTC.py
new file mode 100644
index 000..2de7d32
--- /dev/null
+++ b/src/dev/riscv/RTC.py
@@ -0,0 +1,51 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+#
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: RISC-V HiFive Platform implementation
Peter Yuen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40599 ) Change subject: arch-riscv: RISC-V HiFive Platform implementation .. arch-riscv: RISC-V HiFive Platform implementation This patch implements the RISC-V HiFive Platform (based on the SiFive HiFive series). The HiFive platform requires a PLIC and CLINT device (based on current HiFive boards). The optional uart_int_id field redirects Console interrupts to the PLIC interrupt controller. PlicDevice is a wrapper around BasicPioDevice that requires an interrupt ID. Interrupts are expected to be raised via platform->postPciInterrupt(id). VirtIOMMIO is a slight modification from the ARM implementation such that interrupts are posted through PLIC PlicDevice is a wrapper around BasicPioDevice that requires an interrupt ID. Interrupts are expected to be raised via platform->postPciInterrupt(id). VirtIOMMIO is a slight modification from the ARM implementation such that interrupts are posted through PLIC. Uart8250 was modified slightly for easier Python setup. Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40599 Reviewed-by: Ayaz Akram Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- A src/dev/riscv/HiFive.py A src/dev/riscv/PlicDevice.py M src/dev/riscv/SConscript A src/dev/riscv/VirtIOMMIO.py A src/dev/riscv/hifive.cc A src/dev/riscv/hifive.hh A src/dev/riscv/plic_device.cc A src/dev/riscv/plic_device.hh A src/dev/riscv/vio_mmio.cc A src/dev/riscv/vio_mmio.hh M src/dev/serial/Uart.py M src/dev/serial/uart8250.cc 12 files changed, 944 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Ayaz Akram: Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py new file mode 100755 index 000..17d54e3 --- /dev/null +++ b/src/dev/riscv/HiFive.py @@ -0,0 +1,169 @@ +# Copyright (c) 2021 Huawei International +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.Platform import Platform +from m5.objects.PMAChecker import PMAChecker +from m5.objects.Clint import Clint +from m5.objects.Plic import Plic +from m5.objects.RTC import RiscvRTC +from m5.objects.Uart import Uart8250 +from m5.objects.Terminal import Terminal +from m5.params import * +from m5.proxy import * + +class HiFive(Platform): +"""HiFive Platform + +Implementation: +This is the base class for SiFive's HiFive +board series. It contains the CLINT and PLIC +interrupt controllers, Uart and Disk. + +Implementation details are based on SiFive +FU540-C000. https://sifive.cdn.prismic.io/ +sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 +1_FU540-C000-v1p3.pdf + +Setup: +The
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: PLIC Implementation
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40598 )
Change subject: arch-riscv: PLIC Implementation
..
arch-riscv: PLIC Implementation
This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.
Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40598
Reviewed-by: Ayaz Akram
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
A src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
A src/dev/riscv/plic.cc
A src/dev/riscv/plic.hh
4 files changed, 882 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
new file mode 100644
index 000..0e2f386
--- /dev/null
+++ b/src/dev/riscv/Plic.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+class Plic(BasicPioDevice):
+"""
+This implementation of PLIC is based on
+the SiFive U54MC datasheet:
+https://sifive.cdn.prismic.io/sifive/fab000f6-
+0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
+full_20G1.03.00_manual.pdf
+"""
+type = 'Plic'
+cxx_header = 'dev/riscv/plic.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+pio_size = Param.Addr(0x400, "PIO Size")
+n_src = Param.Int("Number of interrupt sources")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index 43946c2..08d462b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -31,9 +31,12 @@
if env['TARGET_ISA'] == 'riscv':
SimObject('Clint.py')
+SimObject('Plic.py')
SimObject('RTC.py')
DebugFlag('Clint')
+DebugFlag('Plic')
Source('clint.cc')
+Source('plic.cc')
Source('rtc.cc')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
new file mode 100644
index 000..60ac192
--- /dev/null
+++ b/src/dev/riscv/plic.cc
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added PMA support for RiscvTLB
Peter Yuen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40596 ) Change subject: arch-riscv: Added PMA support for RiscvTLB .. arch-riscv: Added PMA support for RiscvTLB Since the RISC-V privileged specs V1.11 did not specify an implementation of physical memory attributes (PMA), e.g. cacheability, an abstract PMAChecker class is created. This class acts as a generic PMAChecker hardware without any latency modelling. The TLB finds the PMAChecker defined at the MMU level by Parent.any. Change-Id: I4400133895be44da67536d80b82422ec3a49d786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40596 Reviewed-by: Ayaz Akram Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A src/arch/riscv/PMAChecker.py M src/arch/riscv/RiscvMMU.py M src/arch/riscv/RiscvTLB.py M src/arch/riscv/SConscript M src/arch/riscv/pagetable_walker.cc M src/arch/riscv/pagetable_walker.hh A src/arch/riscv/pma_checker.cc A src/arch/riscv/pma_checker.hh M src/arch/riscv/tlb.cc M src/arch/riscv/tlb.hh 10 files changed, 234 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Ayaz Akram: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/src/arch/riscv/PMAChecker.py b/src/arch/riscv/PMAChecker.py new file mode 100644 index 000..12b1ca3 --- /dev/null +++ b/src/arch/riscv/PMAChecker.py @@ -0,0 +1,45 @@ +# -*- mode:python -*- + +# Copyright (c) 2021 Huawei International +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class PMAChecker(SimObject): +type = 'PMAChecker' +cxx_header = 'arch/riscv/pma_checker.hh' +uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges") diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py index 238e11e..4ff477e 100644 --- a/src/arch/riscv/RiscvMMU.py +++ b/src/arch/riscv/RiscvMMU.py @@ -37,6 +37,7 @@ from m5.objects.BaseMMU import BaseMMU from m5.objects.RiscvTLB import RiscvTLB +from m5.objects.PMAChecker import PMAChecker class RiscvMMU(BaseMMU): type = 'RiscvMMU' @@ -44,6 +45,7 @@ cxx_header = 'arch/riscv/mmu.hh' itb = RiscvTLB() dtb = RiscvTLB() +pma_checker = PMAChecker() @classmethod def walkerPorts(cls): diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py index 4844feb..b419262 100644 --- a/src/arch/riscv/RiscvTLB.py +++ b/src/arch/riscv/RiscvTLB.py @@ -2,6 +2,7 @@ # Copyright (c) 2007 MIPS Technologies, Inc. # Copyright (c) 2020 Barkhausen Institut +# Copyright (c) 2021 Huawei International # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,6 +42,8 @@ system = Param.System(Parent.any, "system object")
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: FS Linux config file for RISC-V
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41033 )
Change subject: arch-riscv: FS Linux config file for RISC-V
..
arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux
configuration.
Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41033
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Ayaz Akram
Maintainer: Jason Lowe-Power
---
A configs/example/riscv/fs_linux.py
1 file changed, 221 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
new file mode 100644
index 000..3d40061
--- /dev/null
+++ b/configs/example/riscv/fs_linux.py
@@ -0,0 +1,221 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import optparse
+import sys
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+from m5.util.fdthelper import *
+
+addToPath('../../')
+
+from ruby import Ruby
+
+from common.FSConfig import *
+from common.SysPaths import *
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common.Caches import *
+from common import Options
+
+# - Add Options #
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addFSOptions(parser)
+
+# NOTE: Ruby in FS Linux has not been tested yet
+if '--ruby' in sys.argv:
+Ruby.define_options(parser)
+
+# Parse Options --- #
+(options, args) = parser.parse_args()
+
+if args:
+print("Error: script doesn't take any positional arguments")
+sys.exit(1)
+
+# CPU and Memory
+(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(options)
+MemClass = Simulation.setMemClass(options)
+
+np = options.num_cpus
+
+# Setup System #
+# Edit this section to customize peripherals and system settings
+system = System()
+mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
+mem=options.mem_size, os_type=options.os_type)
+system.mem_mode = mem_mode
+system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
+
+system.workload =
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixing interrupt handling order and effect of mideleg
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40076 )
Change subject: arch-riscv: Fixing interrupt handling order and effect of
mideleg
..
arch-riscv: Fixing interrupt handling order and effect of mideleg
This patch fixes the issues listed in:
https://gem5.atlassian.net/browse/GEM5-887
https://gem5.atlassian.net/browse/GEM5-889
The code change has been verified by booting FS linux.
Software, timer and external interrupts work as expected.
Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40076
Reviewed-by: Ayaz Akram
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/interrupts.hh
1 file changed, 19 insertions(+), 6 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f07e7d7..142911e 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -66,16 +66,24 @@
{
INTERRUPT mask = 0;
STATUS status = tc->readMiscReg(MISCREG_STATUS);
+INTERRUPT mideleg = tc->readMiscReg(MISCREG_MIDELEG);
+INTERRUPT sideleg = tc->readMiscReg(MISCREG_SIDELEG);
PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
switch (prv) {
case PRV_U:
-mask.mei = mask.mti = mask.msi = 1;
-mask.sei = mask.sti = mask.ssi = 1;
+mask.mei = (!sideleg.mei) | (sideleg.mei & status.uie);
+mask.mti = (!sideleg.mti) | (sideleg.mti & status.uie);
+mask.msi = (!sideleg.msi) | (sideleg.msi & status.uie);
+mask.sei = (!sideleg.sei) | (sideleg.sei & status.uie);
+mask.sti = (!sideleg.sti) | (sideleg.sti & status.uie);
+mask.ssi = (!sideleg.ssi) | (sideleg.ssi & status.uie);
if (status.uie)
mask.uei = mask.uti = mask.usi = 1;
break;
case PRV_S:
-mask.mei = mask.mti = mask.msi = 1;
+mask.mei = (!mideleg.mei) | (mideleg.mei & status.sie);
+mask.mti = (!mideleg.mti) | (mideleg.mti & status.sie);
+mask.msi = (!mideleg.msi) | (mideleg.msi & status.sie);
if (status.sie)
mask.sei = mask.sti = mask.ssi = 1;
mask.uei = mask.uti = mask.usi = 0;
@@ -105,9 +113,14 @@
{
assert(checkInterrupts());
std::bitset mask = globalMask();
-for (int c = 0; c < NumInterruptTypes; c++)
-if (checkInterrupt(c) && mask[c])
-return std::make_shared(c);
+const std::vector interrupt_order {
+INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
+INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
+INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+};
+for (const int : interrupt_order)
+if (checkInterrupt(id) && mask[id])
+return std::make_shared(id);
return NoFault;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40076
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Gerrit-Change-Number: 40076
Gerrit-PatchSet: 3
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Peter Yuen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: FS Linux config file for RISC-V
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41033 )
Change subject: arch-riscv: FS Linux config file for RISC-V
..
arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux
configuration.
Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
---
A configs/example/riscv/fs_linux.py
1 file changed, 228 insertions(+), 0 deletions(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
new file mode 100644
index 000..75c54a5
--- /dev/null
+++ b/configs/example/riscv/fs_linux.py
@@ -0,0 +1,228 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import optparse
+import sys
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+from m5.util.fdthelper import *
+
+addToPath('../../')
+
+from ruby import Ruby
+
+from common.FSConfig import *
+from common.SysPaths import *
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common.Caches import *
+from common import Options
+
+# - Add Options #
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addFSOptions(parser)
+
+# NOTE: Ruby in FS Linux has not been tested yet
+if '--ruby' in sys.argv:
+Ruby.define_options(parser)
+
+# Parse Options --- #
+(options, args) = parser.parse_args()
+
+if args:
+print("Error: script doesn't take any positional arguments")
+sys.exit(1)
+
+# CPU and Memory
+(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(options)
+MemClass = Simulation.setMemClass(options)
+
+np = options.num_cpus
+
+# Setup System #
+# Edit this section to customize peripherals and system settings
+system = System()
+mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
+mem=options.mem_size, os_type=options.os_type)
+system.mem_mode = mem_mode
+system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
+
+system.workload = RiscvBareMetal()
+
+system.iobus = IOXBar()
+system.membus = MemBus()
+
+system.system_port = system.membus.slave
+
+system.intrctrl = IntrControl()
+
+# HiFive platform
+system.platform = HiFive()
+
+# CLNT
+system.platform.clint = Clint()
+system.platform.clint.frequency = Frequency("100MHz")
+system.platform.clint.pio =
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: RISC-V HiFive Platform implementation
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40599 )
Change subject: arch-riscv: RISC-V HiFive Platform implementation
..
arch-riscv: RISC-V HiFive Platform implementation
This patch implements the RISC-V HiFive Platform
(based on the SiFive HiFive series). The HiFive
platform requires a PLIC and CLINT device (based on
current HiFive boards).
The optional uart_int_id field redirects Console interrupts
to the PLIC interrupt controller.\
PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).
VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC\
PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).
VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC.
Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56
---
A src/dev/riscv/HiFive.py
A src/dev/riscv/PlicDevice.py
M src/dev/riscv/SConscript
A src/dev/riscv/VirtIOMMIO.py
A src/dev/riscv/hifive.cc
A src/dev/riscv/hifive.hh
A src/dev/riscv/plic_device.cc
A src/dev/riscv/plic_device.hh
A src/dev/riscv/vio_mmio.cc
A src/dev/riscv/vio_mmio.hh
10 files changed, 832 insertions(+), 0 deletions(-)
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
new file mode 100755
index 000..f1b12fc
--- /dev/null
+++ b/src/dev/riscv/HiFive.py
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Platform import Platform
+from m5.params import *
+from m5.proxy import *
+
+class HiFive(Platform):
+type = 'HiFive'
+cxx_header = "dev/riscv/hifive.hh"
+system = Param.System(Parent.any, "system")
+clint = Param.Clint("CLINT")
+plic = Param.Plic("PLIC")
+# Int source ID to redirect console interrupts to
+# Set to 0 if using a pci interrupt for Uart instead
+uart_int_id = Param.Int(0, "PLIC Uart interrupt ID")
\ No newline at end of file
diff --git a/src/dev/riscv/PlicDevice.py b/src/dev/riscv/PlicDevice.py
new file mode 100644
index 000..f94b04b
--- /dev/null
+++ b/src/dev/riscv/PlicDevice.py
@@ -0,0 +1,48 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+#
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: PLIC Implementation
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40598 )
Change subject: arch-riscv: PLIC Implementation
..
arch-riscv: PLIC Implementation
This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.
Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
---
A src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
A src/dev/riscv/plic.cc
A src/dev/riscv/plic.hh
4 files changed, 884 insertions(+), 0 deletions(-)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
new file mode 100644
index 000..9650ff3
--- /dev/null
+++ b/src/dev/riscv/Plic.py
@@ -0,0 +1,47 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+class Plic(BasicPioDevice):
+type = 'Plic'
+cxx_header = 'dev/riscv/plic.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+pio_size = Param.Addr(0x400, "PIO Size")
+n_src = Param.Int("Number of interrupt sources")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index b2092ca..300c099 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -30,7 +30,10 @@
if env['TARGET_ISA'] == 'riscv':
SimObject('Clint.py')
+SimObject('Plic.py')
DebugFlag('RiscvClint')
+DebugFlag('RiscvPlic')
Source('clint.cc')
+Source('plic.cc')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
new file mode 100644
index 000..fbea925
--- /dev/null
+++ b/src/dev/riscv/plic.cc
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Implementation of CLINT
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40597 )
Change subject: arch-riscv: Implementation of CLINT
..
arch-riscv: Implementation of CLINT
This patch implements the CLINT device model based
on the SiFive U54MC datasheet. Currently, the RTC
is included in the CLINT device model. This will be
moved out in future patches. Instead, CLINT will receive
the clock signal via an InterruptPin.
isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).
Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
---
M src/arch/riscv/isa.cc
A src/dev/riscv/Clint.py
A src/dev/riscv/SConscript
A src/dev/riscv/clint.cc
A src/dev/riscv/clint.hh
5 files changed, 484 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 8401310..2251f9f 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -261,7 +261,7 @@
if (hpmCounterEnabled(MISCREG_TIME)) {
DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
std::time(nullptr));
-return std::time(nullptr);
+return readMiscRegNoEffect(MISCREG_TIME);
} else {
warn("Wall clock disabled.\n");
return 0;
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
new file mode 100644
index 000..8d527f7
--- /dev/null
+++ b/src/dev/riscv/Clint.py
@@ -0,0 +1,49 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+
+class Clint(BasicPioDevice):
+type = 'Clint'
+cxx_header = 'dev/riscv/clint.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+time = Param.Time('01/01/2009', "System time ('Now' for actual time)")
+frequency = Param.Frequency("1MHz", "RTC Frequency")
+pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
new file mode 100755
index 000..b2092ca
--- /dev/null
+++ b/src/dev/riscv/SConscript
@@ -0,0 +1,36 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,dev: Extended Register class to contain property
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40595 )
Change subject: arch-riscv,dev: Extended Register class to contain property
..
arch-riscv,dev: Extended Register class to contain property
This is an extension of the templated Register class to
include an arbitrary property object associated with
the register. This allows for pre- and post-processing
before reads and after writes based on the register
property (using callbacks).
This register class is used in CLINT and PLIC to post
interrupts based on the register index.
Currently it is put under src/dev/riscv. If there are
more use cases in the future it might be useful to merge
it into the src/dev/reg_bank.hh file.
Change-Id: Ife58f4e89549e60c840a9e991e0041e83e479d4a
---
A src/dev/riscv/reg_bank.hh
1 file changed, 203 insertions(+), 0 deletions(-)
diff --git a/src/dev/riscv/reg_bank.hh b/src/dev/riscv/reg_bank.hh
new file mode 100644
index 000..8e72e37
--- /dev/null
+++ b/src/dev/riscv/reg_bank.hh
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_RISCV_REG_BANK_HH__
+#define __DEV_RISCV_REG_BANK_HH__
+#include "dev/reg_bank.hh"
+
+template
+class PropRegisterBank : public RegisterBank {
+
+ public:
+
+constexpr PropRegisterBank(const std::string _name, Addr
new_base) :
+RegisterBank(new_name, new_base)
+{}
+
+template
+class PropRegister : public PropRegisterBank::RegisterBase
+{
+public:
+/**
+ * Type definitions for template deduction
+ */
+using This = PropRegister;
+typedef typename RegisterBank::template
+Register Register;
+typedef typename RegisterBank::RegisterBase
RegisterBase;
+using CallBackFunc = std::function;
+
+/**
+ * Class variables
+ */
+Register reg;
+
+private:
+Prop _prop = {};
+CallBackFunc _readCallBack = emptyCallBack;
+CallBackFunc _writeCallBack = emptyCallBack;
+
+public:
+// Constructors
+constexpr PropRegister(const std::string _name,
+const Prop _prop, const Data _data) :
+RegisterBase(new_name, sizeof(new_data)),
+reg(new_name, new_data),
+_prop(new_prop) {}
+
+constexpr PropRegister(const std::string _name,
+const Prop &_prop, const Data &_data) :
+RegisterBase(new_name, sizeof(new_data)),
+reg(new_name, new_data),
+_prop(new_prop) {}
+
+// Callback functions
+static void emptyCallBack(This ) {}
+
+template
+constexpr This &
+beforeRead(Parent *parent, void (Parent::*nr)(Args... args)) {
+auto wrapper = [parent, nr](Args &&... args) {
+
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Modifications to Riscv FS Configuration
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40600 )
Change subject: arch-riscv: Modifications to Riscv FS Configuration
..
arch-riscv: Modifications to Riscv FS Configuration
FSConfig is modified to connect necessary devices for
booting FS Linux. In future patches this will be organized
further. Devicetree generation feature might also be
added.
Change-Id: I94a07fc337f543f9a049ccac66689cfc50fdc8c8
---
M configs/common/FSConfig.py
M configs/example/fs.py
2 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6665225..597fcf2 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,5 +1,6 @@
# Copyright (c) 2010-2012, 2015-2019 ARM Limited
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -611,27 +612,72 @@
self.workload.command_line = fillInCmdline(mdesc, cmdline)
return self
-def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+def makeLinuxRiscvSystem(mem_mode, mdesc=None, cmdline=None):
self = System()
if not mdesc:
# generic system
mdesc = SysConfig()
self.mem_mode = mem_mode
-self.mem_ranges = [AddrRange(mdesc.mem())]
+self.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
self.workload = RiscvBareMetal()
self.iobus = IOXBar()
self.membus = MemBus()
+self.system_port = self.membus.slave
+
+self.intrctrl = IntrControl()
+
+# HiFive platform
+self.platform = HiFive()
+
+# CLNT
+self.platform.clint = Clint()
+self.platform.clint.frequency = Frequency("100MHz")
+self.platform.clint.pio = self.membus.master
+
+# PLIC
+self.platform.plic = Plic()
+self.platform.clint.pio_addr = 0x200
+self.platform.plic.pio_addr = 0xc00
+self.platform.plic.n_src = 11
+self.platform.plic.pio = self.membus.master
+
+# UART
+self.uart = Uart8250(pio_addr=0x1000)
+self.terminal = Terminal()
+self.platform.uart_int_id = 0xa
+self.uart.pio = self.iobus.master
+
+# VirtIOMMIO
+image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
+image.child.image_file = mdesc.disks()[0]
+self.platform.disk = MmioVirtIO(
+vio=VirtIOBlock(image=image),
+interrupt_id=0x8,
+pio_size = 4096
+)
+self.platform.disk.pio_addr = 0x10008000
+self.platform.disk.pio = self.iobus.master
+
+# PMA
+self.pma = PMA()
+self.pma.uncacheable = [
+AddrRange(0x1000, 0x1008),
+AddrRange(0x10008000, 0x10009000),
+AddrRange(0xc00, 0xc21),
+AddrRange(0x200, 0x201)
+]
+
self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
-# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO
space
-IO_address_space_base = 0x00FF
-self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+self.bridge.ranges = [
+AddrRange(0x1000, 0x1080),
+AddrRange(0x10008000, 0x10009000)
+]
-self.system_port = self.membus.slave
return self
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
diff --git a/configs/example/fs.py b/configs/example/fs.py
index f388503..f71912a 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,5 +1,6 @@
# Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -81,7 +82,7 @@
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "riscv":
-test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
+test_sys = makeLinuxRiscvSystem(test_mem_mode, bm[0],
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, np, bm[0],
options.ruby,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40600
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I94a07fc337f543f9a049ccac66689cfc50fdc8c8
Gerrit-Change-Number: 40600
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added PMA support for RiscvTLB
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40596 )
Change subject: arch-riscv: Added PMA support for RiscvTLB
..
arch-riscv: Added PMA support for RiscvTLB
Since the RISC-V privileged specs V1.11 did not specify
an implementation of physical memory attributes (PMA), e.g.
cacheability, an abstract PMA class is created. This
class acts as a container storing the PMAs.
The TLB finds the PMA defined at the system level by
Parent.any.
Change-Id: I4400133895be44da67536d80b82422ec3a49d786
---
A src/arch/riscv/RiscvPMA.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
A src/arch/riscv/pma.cc
A src/arch/riscv/pma.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
7 files changed, 217 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/RiscvPMA.py b/src/arch/riscv/RiscvPMA.py
new file mode 100644
index 000..8ab67ab
--- /dev/null
+++ b/src/arch/riscv/RiscvPMA.py
@@ -0,0 +1,46 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+
+class PMA(SimObject):
+type = 'PMA'
+cxx_header = 'arch/riscv/pma.hh'
+uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 4844feb..a1f7e03 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -2,6 +2,7 @@
# Copyright (c) 2007 MIPS Technologies, Inc.
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -49,3 +50,7 @@
size = Param.Int(64, "TLB size")
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
+# The pma is found under the System object
+# defining PMA under the Platform object might not work
+# as the CPU and MMU are not children of the Platform
+pma = Param.PMA(Parent.any, "Physical Memory Attributes")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 472264f..ae0b438 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -54,6 +54,7 @@
Source('reg_abi.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
+Source('pma.cc')
Source('linux/se_workload.cc')
Source('linux/linux.cc')
@@ -64,6 +65,7 @@
SimObject('RiscvInterrupts.py')
SimObject('RiscvISA.py')
SimObject('RiscvMMU.py')
+SimObject('RiscvPMA.py')
SimObject('RiscvSeWorkload.py')
SimObject('RiscvTLB.py')
diff --git a/src/arch/riscv/pma.cc b/src/arch/riscv/pma.cc
new file mode 100644
index 000..a41e912
--- /dev/null
+++ b/src/arch/riscv/pma.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixing interrupt handling order and effect of mideleg
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40076 )
Change subject: arch-riscv: Fixing interrupt handling order and effect of
mideleg
..
arch-riscv: Fixing interrupt handling order and effect of mideleg
This patch fixes the issues listed in:
https://gem5.atlassian.net/browse/GEM5-887
https://gem5.atlassian.net/browse/GEM5-889
The code change has been verified by booting FS linux.
Software, timer and external interrupts work as expected.
Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
---
M src/arch/riscv/interrupts.hh
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index e1460ab..10638dd 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -72,16 +72,24 @@
{
INTERRUPT mask = 0;
STATUS status = tc->readMiscReg(MISCREG_STATUS);
+INTERRUPT mideleg = tc->readMiscReg(MISCREG_MIDELEG);
+INTERRUPT sideleg = tc->readMiscReg(MISCREG_SIDELEG);
PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
switch (prv) {
case PRV_U:
-mask.mei = mask.mti = mask.msi = 1;
-mask.sei = mask.sti = mask.ssi = 1;
+mask.mei = mideleg.mei ^ status.uie;
+mask.mti = mideleg.mti ^ status.uie;
+mask.msi = mideleg.msi ^ status.uie;
+mask.sei = sideleg.sei ^ status.uie;
+mask.sti = sideleg.sti ^ status.uie;
+mask.ssi = sideleg.ssi ^ status.uie;
if (status.uie)
mask.uei = mask.uti = mask.usi = 1;
break;
case PRV_S:
-mask.mei = mask.mti = mask.msi = 1;
+mask.mei = mideleg.mei ^ status.sie;
+mask.mti = mideleg.mti ^ status.sie;
+mask.msi = mideleg.msi ^ status.sie;
if (status.sie)
mask.sei = mask.sti = mask.ssi = 1;
mask.uei = mask.uti = mask.usi = 0;
@@ -111,9 +119,14 @@
{
assert(checkInterrupts());
std::bitset mask = globalMask();
-for (int c = 0; c < NumInterruptTypes; c++)
-if (checkInterrupt(c) && mask[c])
-return std::make_shared(c);
+const std::vector interrupt_order {
+INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
+INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
+INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+};
+for (const int : interrupt_order)
+if (checkInterrupt(id) && mask[id])
+return std::make_shared(id);
return NoFault;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40076
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Gerrit-Change-Number: 40076
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Moving ExceptionCode to registers.hh for reusability
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39955 )
Change subject: arch-riscv: Moving ExceptionCode to registers.hh for
reusability
..
arch-riscv: Moving ExceptionCode to registers.hh for reusability
The ExceptionCode enum was originally defined in faults.hh. However,
it can actually be reused in registers.hh were interrupt bit locations
were previously hardcoded. I hence suggest moving the ExceptionCode
enum definition to registers.hh and have made the replacements for
the bit locations.
Change-Id: I9475f362b98b2a438786b39f6c0da4fb0e68aa02
---
M src/arch/riscv/faults.hh
M src/arch/riscv/registers.hh
2 files changed, 61 insertions(+), 58 deletions(-)
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 5e24da2..a078662 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -49,46 +49,6 @@
FloatInvalid = 0x10
};
-/*
- * In RISC-V, exception and interrupt codes share some values. They can be
- * differentiated by an 'Interrupt' flag that is enabled for interrupt
faults
- * but not exceptions. The full fault cause can be computed by placing the
- * exception (or interrupt) code in the least significant bits of the CAUSE
- * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
- * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
- * privileged specification v 1.10. Codes are enumerated in Table 3.6.
- */
-enum ExceptionCode : uint64_t {
-INST_ADDR_MISALIGNED = 0,
-INST_ACCESS = 1,
-INST_ILLEGAL = 2,
-BREAKPOINT = 3,
-LOAD_ADDR_MISALIGNED = 4,
-LOAD_ACCESS = 5,
-STORE_ADDR_MISALIGNED = 6,
-AMO_ADDR_MISALIGNED = 6,
-STORE_ACCESS = 7,
-AMO_ACCESS = 7,
-ECALL_USER = 8,
-ECALL_SUPER = 9,
-ECALL_MACHINE = 11,
-INST_PAGE = 12,
-LOAD_PAGE = 13,
-STORE_PAGE = 15,
-AMO_PAGE = 15,
-
-INT_SOFTWARE_USER = 0,
-INT_SOFTWARE_SUPER = 1,
-INT_SOFTWARE_MACHINE = 3,
-INT_TIMER_USER = 4,
-INT_TIMER_SUPER = 5,
-INT_TIMER_MACHINE = 7,
-INT_EXT_USER = 8,
-INT_EXT_SUPER = 9,
-INT_EXT_MACHINE = 11,
-NumInterruptTypes
-};
-
class RiscvFault : public FaultBase
{
protected:
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 9721635..2ba5d2c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,8 +93,11 @@
const int ZeroReg = 0;
const int ReturnAddrReg = 1;
const int StackPointerReg = 2;
+const int GlobalPointerReg = 3;
const int ThreadPointerReg = 4;
+const int FramePointerReg = 8;
const int ReturnValueReg = 10;
+const std::vector ReturnValueRegs = {10, 11};
const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
@@ -616,6 +619,46 @@
Bitfield<0> uie;
EndBitUnion(STATUS)
+/*
+ * In RISC-V, exception and interrupt codes share some values. They can be
+ * differentiated by an 'Interrupt' flag that is enabled for interrupt
faults
+ * but not exceptions. The full fault cause can be computed by placing the
+ * exception (or interrupt) code in the least significant bits of the CAUSE
+ * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
+ * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
+ * privileged specification v 1.10. Codes are enumerated in Table 3.6.
+ */
+enum ExceptionCode : uint64_t {
+INST_ADDR_MISALIGNED = 0,
+INST_ACCESS = 1,
+INST_ILLEGAL = 2,
+BREAKPOINT = 3,
+LOAD_ADDR_MISALIGNED = 4,
+LOAD_ACCESS = 5,
+STORE_ADDR_MISALIGNED = 6,
+AMO_ADDR_MISALIGNED = 6,
+STORE_ACCESS = 7,
+AMO_ACCESS = 7,
+ECALL_USER = 8,
+ECALL_SUPER = 9,
+ECALL_MACHINE = 11,
+INST_PAGE = 12,
+LOAD_PAGE = 13,
+STORE_PAGE = 15,
+AMO_PAGE = 15,
+
+INT_SOFTWARE_USER = 0,
+INT_SOFTWARE_SUPER = 1,
+INT_SOFTWARE_MACHINE = 3,
+INT_TIMER_USER = 4,
+INT_TIMER_SUPER = 5,
+INT_TIMER_MACHINE = 7,
+INT_EXT_USER = 8,
+INT_EXT_SUPER = 9,
+INT_EXT_MACHINE = 11,
+NumInterruptTypes
+};
+
/**
* These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
* v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the
MIP
@@ -623,15 +666,15 @@
* this bit union.
*/
BitUnion64(INTERRUPT)
-Bitfield<11> mei;
-Bitfield<9> sei;
-Bitfield<8> uei;
-Bitfield<7> mti;
-Bitfield<5> sti;
-Bitfield<4> uti;
-Bitfield<3> msi;
-Bitfield<1> ssi;
-Bitfield<0> usi;
+Bitfield mei;
+Bitfield sei;
+Bitfield uei;
+Bitfield mti;
+Bitfield sti;
+Bitfield uti;
+Bitfield msi;
+Bitfield ssi;
+Bitfield usi;
EndBitUnion(INTERRUPT)
const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
@@ -685,15 +728,15 @@
STATUS_FS_MASK | STATUS_UPIE_MASK |
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.
Peter Yuen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39816 ) Change subject: arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses. .. arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses. Change-Id: I6bd71da5c83e12c06043889bdbef7e4c0cf78190 --- M src/arch/riscv/remote_gdb.cc 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 021b388..da78957 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -211,7 +211,7 @@ // U mode CSR r.ustatus = context->readMiscRegNoEffect( CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS); -r.uie = context->readMiscRegNoEffect( +r.uie = context->readMiscReg( CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE); r.utvec = context->readMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex); @@ -223,7 +223,7 @@ CSRData.at(CSR_UCAUSE).physIndex); r.utval = context->readMiscRegNoEffect( CSRData.at(CSR_UTVAL).physIndex); -r.uip = context->readMiscRegNoEffect( +r.uip = context->readMiscReg( CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP); // S mode CSR @@ -233,7 +233,7 @@ CSRData.at(CSR_SEDELEG).physIndex); r.sideleg = context->readMiscRegNoEffect( CSRData.at(CSR_SIDELEG).physIndex); -r.sie = context->readMiscRegNoEffect( +r.sie = context->readMiscReg( CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE); r.stvec = context->readMiscRegNoEffect( CSRData.at(CSR_STVEC).physIndex); @@ -247,7 +247,7 @@ CSRData.at(CSR_SCAUSE).physIndex); r.stval = context->readMiscRegNoEffect( CSRData.at(CSR_STVAL).physIndex); -r.sip = context->readMiscRegNoEffect( +r.sip = context->readMiscReg( CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP); r.satp = context->readMiscRegNoEffect( CSRData.at(CSR_SATP).physIndex); @@ -269,7 +269,7 @@ CSRData.at(CSR_MEDELEG).physIndex); r.mideleg = context->readMiscRegNoEffect( CSRData.at(CSR_MIDELEG).physIndex); -r.mie = context->readMiscRegNoEffect( +r.mie = context->readMiscReg( CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE); r.mtvec = context->readMiscRegNoEffect( CSRData.at(CSR_MTVEC).physIndex); @@ -283,7 +283,7 @@ CSRData.at(CSR_MCAUSE).physIndex); r.mtval = context->readMiscRegNoEffect( CSRData.at(CSR_MTVAL).physIndex); -r.mip = context->readMiscRegNoEffect( +r.mip = context->readMiscReg( CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP); // H mode CSR (to be implemented) @@ -340,11 +340,11 @@ newVal = (oldVal & ~mask) | (r.ustatus & mask); context->setMiscRegNoEffect( CSRData.at(CSR_USTATUS).physIndex, newVal); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_UIE).physIndex); mask = CSRMasks.at(CSR_UIE); newVal = (oldVal & ~mask) | (r.uie & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_UIE).physIndex, newVal); context->setMiscRegNoEffect( CSRData.at(CSR_UTVEC).physIndex, r.utvec); @@ -356,11 +356,11 @@ CSRData.at(CSR_UCAUSE).physIndex, r.ucause); context->setMiscRegNoEffect( CSRData.at(CSR_UTVAL).physIndex, r.utval); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_UIP).physIndex); mask = CSRMasks.at(CSR_UIP); newVal = (oldVal & ~mask) | (r.uip & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_UIP).physIndex, newVal); // S mode CSR @@ -374,11 +374,11 @@ CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg); context->setMiscRegNoEffect( CSRData.at(CSR_SIDELEG).physIndex, r.sideleg); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_SIE).physIndex); mask = CSRMasks.at(CSR_SIE); newVal = (oldVal & ~mask) | (r.sie & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_SIE).physIndex, newVal); context->setMiscRegNoEffect( CSRData.at(CSR_STVEC).physIndex, r.stvec); @@ -392,11 +392,11 @@ CSRData.at(CSR_SCAUSE).physIndex, r.scause); context->setMiscRegNoEffect( CSRData.at(CSR_STVAL).physIndex, r.stval); -oldVal = context->readMiscRegNoEffect( +oldVal = context->readMiscReg( CSRData.at(CSR_SIP).physIndex); mask = CSRMasks.at(CSR_SIP); newVal = (oldVal & ~mask) | (r.sip & mask); -context->setMiscRegNoEffect( +context->setMiscReg( CSRData.at(CSR_SIP).physIndex, newVal); context->setMiscRegNoEffect(
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38955 )
Change subject: arch-riscv: CSR registers support in RISC-V remote GDB.
..
arch-riscv: CSR registers support in RISC-V remote GDB.
Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.
Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs
Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38955
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
A ext/gdb-xml/riscv-64bit-cpu.xml
A ext/gdb-xml/riscv-64bit-csr.xml
A ext/gdb-xml/riscv-64bit-fpu.xml
A ext/gdb-xml/riscv.xml
M src/arch/riscv/SConscript
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
7 files changed, 740 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/gdb-xml/riscv-64bit-cpu.xml
b/ext/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 000..ca59ac3
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
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+
\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-csr.xml
b/ext/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 000..6b2ae79
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,248 @@
+
+
+
+
+
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+
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-fpu.xml
b/ext/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 000..7b68ba4
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,58 @@
+
+
+
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+
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv.xml b/ext/gdb-xml/riscv.xml
new file mode 100644
index 000..cae8bf7
--- /dev/null
+++ b/ext/gdb-xml/riscv.xml
@@ -0,0 +1,13 @@
+
+
+
+
+ riscv
+
+
+
+
\ No newline at end of file
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 3913be9..0179fbc 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -3,6 +3,7 @@
# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -73,3 +74,8 @@
# Add in files generated by the ISA description.
ISADesc('isa/main.isa')
+
+GdbXml('riscv.xml', 'gdb_xml_riscv_target')
+GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
+GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
+GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 0e4c544..75f1820 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2021 Huawei International
* Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2010 ARM Limited
@@ -137,6 +138,11 @@
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
+#include "blobs/gdb_xml_riscv_cpu.hh"
+#include "blobs/gdb_xml_riscv_csr.hh"
+#include "blobs/gdb_xml_riscv_fpu.hh"
+#include "blobs/gdb_xml_riscv_target.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -165,7 +171,7 @@
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
-context(), paddr, logBytes, BaseTLB::Read);
+context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
return false;
}
@@ -179,21 +185,304 @@
RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
{
DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
+
+// General registers
for (int i = 0; i <
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38955 )
Change subject: arch-riscv: CSR registers support in RISC-V remote GDB.
..
arch-riscv: CSR registers support in RISC-V remote GDB.
Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.
Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs
Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
---
A ext/gdb-xml/riscv-64bit-cpu.xml
A ext/gdb-xml/riscv-64bit-csr.xml
A ext/gdb-xml/riscv-64bit-fpu.xml
A ext/gdb-xml/riscv.xml
M src/arch/riscv/SConscript
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
7 files changed, 733 insertions(+), 2 deletions(-)
diff --git a/ext/gdb-xml/riscv-64bit-cpu.xml
b/ext/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 000..cd45b19
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,46 @@
+
+
+
+
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-csr.xml
b/ext/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 000..218397b
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,247 @@
+
+
+
+
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-fpu.xml
b/ext/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 000..8342da9
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,57 @@
+
+
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv.xml b/ext/gdb-xml/riscv.xml
new file mode 100644
index 000..731ef95
--- /dev/null
+++ b/ext/gdb-xml/riscv.xml
@@ -0,0 +1,13 @@
+
+
+
+
+ riscv
+
+
+
+
\ No newline at end of file
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 3913be9..33a9841 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -73,3 +73,8 @@
# Add in files generated by the ISA description.
ISADesc('isa/main.isa')
+
+GdbXml('riscv.xml', 'gdb_xml_riscv_target')
+GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
+GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
+GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 0e4c544..aa871c6 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -137,6 +137,11 @@
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
+#include "blobs/gdb_xml_riscv_cpu.hh"
+#include "blobs/gdb_xml_riscv_csr.hh"
+#include "blobs/gdb_xml_riscv_fpu.hh"
+#include "blobs/gdb_xml_riscv_target.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -165,7 +170,7 @@
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
-context(), paddr, logBytes, BaseTLB::Read);
+context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
return false;
}
@@ -179,21 +184,304 @@
RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
{
DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
+
+// General registers
for (int i = 0; i < NumIntArchRegs; i++)
+{
r.gpr[i] = context->readIntReg(i);
+}
r.pc = context->pcState().pc();
+
+// Floating point registers
+for (int i = 0; i < NumFloatRegs; i++)
+r.fpu[i] = context->readFloatReg(i);
+r.fflags = context->readMiscRegNoEffect(
+CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
+r.frm = context->readMiscRegNoEffect(
+CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
+r.fcsr = context->readMiscRegNoEffect(
+CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
+
+// CSR registers
+r.cycle = context->readMiscRegNoEffect(
+CSRData.at(CSR_CYCLE).physIndex);
