[gem5-users] Re: Difference between using the Configuration Script vs Standard Library?

2024-04-17 Thread Jason Lowe-Power via gem5-users
Hi Kaze,

Thank you for reaching out and expressing your interest in gem5
simulations. I understand that you’re curious about the difference between
the configuration script and the standard library when executing the SE
binary with the same parameters.

gem5’s interface is primarily based on Python scripts. These scripts are
written by users like yourself to control the simulation. The standard
library, on the other hand, is a collection of Python classes that serve as
a wrapper for gem5’s models, which are written in C++.

The standard library Python classes are essentially instances of gem5’s
models, with specific parameters already set for you. This means that when
you’re using the standard library, you’re using pre-configured instances of
the models, which can simplify the process of setting up your simulation.

Therefore, when you want to create a simulation for a system you’re
interested in modeling, you should write a Python script that utilizes
these standard library Python classes. This approach allows you to leverage
the pre-set parameters of the standard library and focus more on the
specifics of your system model.

I hope this explanation helps clarify your confusion. If you have any more
questions or need further clarification, please don’t hesitate to ask.

Cheers,
Jason


On Sat, Apr 6, 2024 at 11:18 AM Kaze Kuma via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, I recently started using Gem5 and playing around with the simulations
> using tte tutorials for reference, but I'm kinda confused on why and how
> the configuration script differs for output from using the standard library
> if using the same parameters for executing SE binary?
> If someone could explain, I'd greatly appreciate it!
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[gem5-users] Re: catching the traces of communication between the processors

2024-02-23 Thread Jason Lowe-Power via gem5-users
Note: this is the output from the gem5 GPT (
https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt/)

Certainly, Ojas!

To capture traces of communication between processors in your gem5
simulation, a more specialized approach involves using the Communication
Monitor component. This feature is designed to monitor and record various
types of communication events within the system, making it an ideal tool
for your needs.

Here's how you can utilize the Communication Monitor in gem5:

### 1. **Enable the Communication Monitor in Your Configuration**

The Communication Monitor needs to be explicitly enabled and configured in
your system definition. This usually involves modifying your Python
simulation script to include the monitor in the system interconnects or
between specific components that you're interested in observing.

For instance, if you're using a simple system with a few cores and want to
monitor the traffic between them, you would integrate the Communication
Monitor into the system's interconnects. This might look something like
adding a monitor component to the bus or directly between caches and
processors, depending on your system architecture.

### 2. **Configure the Monitor**

The Communication Monitor can be configured to capture various types of
data, such as packet transfers, latency information, and bandwidth usage.
You'll need to decide what information is relevant for your analysis and
configure the monitor accordingly. This could involve setting parameters
for what types of transactions to record, whether to capture all
transactions or only those that meet certain criteria, and how to log this
information.

### 3. **Run the Simulation**

With the Communication Monitor configured, run your simulation as usual.
The monitor will operate in the background, capturing data on the
communication patterns and events that occur during the simulation.

### 4. **Analyze the Results**

After the simulation, the Communication Monitor will produce output that
details the observed communication events. This output will typically be in
a form that can be easily analyzed, such as a CSV file or a series of log
entries. You can use this data to understand the communication patterns,
identify bottlenecks, and make informed decisions about optimizing your
system.

### 5. **Adjust and Iterate**

Based on your findings, you may want to adjust the configuration of the
Communication Monitor or the system itself to capture additional data or
focus on specific areas of interest. This iterative process can help refine
your understanding and optimize your system's performance.

### Additional Notes:

- Integrating the Communication Monitor requires some familiarity with
gem5's configuration scripts and potentially modifying existing system
definitions. If you're new to this, it might take some time to get used to
how these scripts work.
- The gem5 documentation and specific guides on the Communication Monitor
can provide more detailed instructions and examples on how to set up and
use this feature effectively.

Using the Communication Monitor offers a targeted approach to understanding
processor communication in your gem5 simulations, providing valuable
insights that can guide system optimization and research. If you have
further questions or need clarification on the setup, feel free to ask!

More sources: https://www.youtube.com/watch?v=TeHKMVOWUAY,
https://www.mail-archive.com/gem5-users@gem5.org/msg18792.html

On Fri, Feb 23, 2024 at 10:53 AM Flash Mobster via gem5-users <
gem5-users@gem5.org> wrote:

> I am new to GEM5, and I want to catch traces of communication between the
> processors in my defined system. How exactly can this be done? I read
> somewhere that --debug is needed for this. Can someone please tell me what
> should I do?
>
> thanks,
> Ojas
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[gem5-users] Re: Limit debug output to certain instruction address range

2024-02-21 Thread Jason Lowe-Power via gem5-users
Hi Hossam,

If you're using the stdlib, you can override the default ROI begin handler.
See the documentation here:
https://github.com/gem5/gem5/blob/stable/src/python/gem5/simulate/simulator.py#L145

If you're not using the stdlib, then look for where the code you're using
calls m5.stats.dump() and comment it out :)

Cheers,
Jason

On Wed, Feb 21, 2024 at 4:59 PM Hossam ElAtali 
wrote:

> Hi Jason,
>
> Thanks for the very quick response!
>
> I managed to surround the ROI with m5op instructions to issue WORKBEGIN
> and WORKEND events,  but now the stats.txt​ file is getting out of hand.
> It dumps stats every time the simulation pauses. Is there a way to make it
> not dump on every event or disable it altogether? I tried using the
> --stats-file​ command line option with an empty string but that caused a
> crash. I also tried truncating and/or deleting the file in the event
> handler in the config script (using the open and truncate python
> functions), but that did nothing (my guess is because the file is already
> open elsewhere).
>
> Thanks again!
>
> Best,
> Hossam
> --
> *From:* Jason Lowe-Power 
> *Sent:* Wednesday, February 21, 2024 1:59 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Hossam ElAtali 
> *Subject:* Re: [gem5-users] Limit debug output to certain instruction
> address range
>
> Hi Hossam,
>
> >  Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> You can definitely do this.
>
> You can use the m5.trace.enable()  and m5.trace.disable() functions in
> python to enable and disable the debug output. You can use m5 ops to exit
> the simulation as you mentioned as well and then call these functions.
>
> Cheers,
> Jason
>
> On Wed, Feb 21, 2024 at 10:46 AM Hossam ElAtali via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi,
>
> I'm currently experimenting with Spectre on gem5, and I'm dumping
> debugging output using the O3PipeView flag. However, I get a lot of output
> for instructions that are not relevant to the attack sequence. I was
> wondering if it's possible to limit the debugging output to a certain
> instruction address range. I know I can limit it to a tick range, but I'd
> like to dump every instance of the attack, not just a specific one. I have
> the instruction addresses for the attack and it would be great if I can
> just use that.
>
> Another option would be to dynamically enable and disable debugging output
> (or the O3PipeView flag, at least) using an m5op.
>
> Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> Any help is greatly appreciated. Thank you.
>
> Best,
> Hossam
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>
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[gem5-users] Re: Can I use RiscvO3CPU with TSO?

2024-02-21 Thread Jason Lowe-Power via gem5-users
Hello,

That *should* work, but my confidence isn't very high. I suggest running
tests to see if you can produce TSO and non-TSO executions with and without
the option.

Cheers,
Jason

On Thu, Feb 15, 2024 at 12:32 PM Z HW via gem5-users 
wrote:

>
> I know that RISC-V assumes RVWMO. But if I want to run a TSO RISC-V
> implementation, can I simply set needsTSO = True in the RiscvO3CPU
> configuration and be done, or am I overlooking some details about using TSO
> in RISC-V?
>
> I need TSO because I want to enforce load->load, load->store ordering by
> default in my program and don't want to use fences.
>
> Thanks!
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[gem5-users] Re: Executing Binary Code in FS without a Kernel

2024-02-21 Thread Jason Lowe-Power via gem5-users
Hi Alain,

I'm the gem5-GPT bot, here to assist with your queries about the gem5
simulator. Please note that while I aim to provide accurate information, my
responses could be wrong or may have been slightly edited for clarity. You
can access the gem5-GPT on chat.openai.com/g/g-o3y1y4t8J-gem5-gpt if you
subscribe to chatGPT.

Welcome to the world of gem5, Alain! Let's address your inquiries one by
one:

1. **Full System (FS) Mode and the Requirement of a Kernel**:
   In gem5's Full System (FS) mode, the simulation environment is designed
to emulate an entire computer system, including processors, memory, and I/O
devices. This mode indeed requires a kernel, as it simulates the hardware
and software interactions that occur in a real system. The kernel is
responsible for managing the hardware resources, including CPU scheduling,
memory management, and the handling of I/O operations. Therefore, to run
binary code in FS mode, you must have an operating system kernel (such as
Linux) loaded and configured to bootstrap the system and execute your
binary code.

2. **Mounting I/O Devices, Including Disk Images**:
   In FS mode, the mounting and management of I/O devices, including disk
images, are typically handled by the kernel. The kernel uses device drivers
to interact with the hardware simulated by gem5, such as disk drives. You
can specify disk images in your gem5 simulation setup, and these will be
recognized as physical disks by the simulated kernel, which can then mount
the filesystems contained within them, similar to how a real system
operates.

   However, you do have the ability to configure certain aspects of how
these devices are presented to the simulated system through gem5's
configuration scripts. For example, you can specify the disk image to use,
the type of disk (e.g., IDE, SATA), and the connection point (e.g., primary
master) in the system's configuration file. This setup is part of the
simulation environment configuration and is done before starting the
simulation.

To summarize, running assembly benchmark code that accesses memory
addresses pre-dumped on a RAW disk image in FS mode requires:
- An operating system kernel to manage hardware interactions, including
those with the disk image.
- Configuration of the gem5 simulation environment to include the disk
image as part of the simulated system's hardware, which the kernel will
then manage.

If you're looking to run binaries without involving a full operating system
kernel, gem5's System Call Emulation (SE) mode is what you're looking for.
SE mode allows you to run user-level applications directly on gem5, with
the simulator providing a minimal environment to handle system calls made
by the application. Here's a detailed overview of SE mode and its
implications for your project:

### SE Mode Overview

- **Direct Execution of Binaries**: SE mode enables the direct execution of
compiled binary applications without the need for a full operating system.
This mode is particularly useful for running benchmarks or specific
application tests where the overhead and complexity of simulating an entire
OS are unnecessary.

- **System Call Emulation**: gem5 in SE mode emulates the system calls that
the application makes. This emulation is handled internally by gem5, which
intercepts system calls and provides the necessary responses, simulating
the effect of having an OS handle these calls. This includes calls for file
I/O, memory allocation, and process control, among others.

- **Simplified I/O and Filesystem Interaction**: Although SE mode can
emulate system calls related to file I/O, the way it handles disk images
and I/O devices is different from FS mode. You can specify input and output
files for your application through gem5's command-line options, but the
direct simulation of disk images as block devices (like in FS mode) is not
supported. Instead, you would typically use virtual filesystems or specify
file paths that gem5 will redirect to real files on your host system.

### Running Binaries in SE Mode

To run a binary in SE mode, you'll generally follow these steps:

1. **Compile Your Binary**: Ensure your benchmark or application is
compiled for the target architecture you intend to simulate (e.g., ARM,
x86).

2. **Set Up Your gem5 Simulation Script**: Configure a gem5 simulation
script to run in SE mode. This script specifies the binary to execute,
along with any arguments or environment variables needed by the application.

3. **Specify File Inputs/Outputs**: If your application expects to read
from or write to files, you can use gem5's options to map these files
within the simulation environment. This allows your application to interact
with files as if it were running on a real system.

4. **Run the Simulation**: Execute your simulation script with gem5, which
will start the application in SE mode, handle its system calls, and
simulate its execution on the specified architecture.

### Limitations and Considerations

- **Limited Device 

[gem5-users] Re: Limit debug output to certain instruction address range

2024-02-21 Thread Jason Lowe-Power via gem5-users
Hi Hossam,

>  Yet another option is a way to enable/disable debugging in the config
script mid-simulation. This would allow me to exit the simulation using an
m5op before the instructions, enable debugging in the config script,
continue, exit using an m5op after the instructions, disable debugging, etc.

You can definitely do this.

You can use the m5.trace.enable()  and m5.trace.disable() functions in
python to enable and disable the debug output. You can use m5 ops to exit
the simulation as you mentioned as well and then call these functions.

Cheers,
Jason

On Wed, Feb 21, 2024 at 10:46 AM Hossam ElAtali via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I'm currently experimenting with Spectre on gem5, and I'm dumping
> debugging output using the O3PipeView flag. However, I get a lot of output
> for instructions that are not relevant to the attack sequence. I was
> wondering if it's possible to limit the debugging output to a certain
> instruction address range. I know I can limit it to a tick range, but I'd
> like to dump every instance of the attack, not just a specific one. I have
> the instruction addresses for the attack and it would be great if I can
> just use that.
>
> Another option would be to dynamically enable and disable debugging output
> (or the O3PipeView flag, at least) using an m5op.
>
> Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> Any help is greatly appreciated. Thank you.
>
> Best,
> Hossam
> ___
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[gem5-users] Re: How to suspend FS simulation after certain number of ticks

2024-01-16 Thread Jason Lowe-Power via gem5-users
Hello,

Unfortunately, we don't have enough time to answer all questions in depth.
You may be able to find more help on either the gem5 slack
 or the gem5 youtube channel
. If you have access to ChatGPT Plus, you
can also use the gem5 GPT .
In fact, we have found that most of the LLMs do a good job answering
gem5-related questions.

In the meantime, here is the output from the gem5 GPT for your question.
This answer has not been checked for correctness, but our experience is
that the answers from the gem5 GPT at a minimum point in the right
direction.

Suspending and resuming a Full System (FS) simulation in gem5, similar to
what you've described for System-call Emulation (SE) mode, is indeed
possible. In FS mode, you can control the simulation flow using the Python
configuration scripts, just as you do in SE mode. However, there are some
nuances to consider when dealing with FS simulations.

For your specific use case, where you want to suspend the simulation after
a certain number of ticks, retrieve the `stats.txt` file, and then resume,
you can follow these steps:

1. **Modify the Python Script**:
   - Open the `/gem5/configs/example/riscv/fs_linux.py` script.
   - In this script, you can insert a loop that calls `m5.simulate()` for a
specified number of ticks. After each `m5.simulate()` call, the script will
regain control, allowing you to perform operations like dumping statistics.
   - Here's an example of how you might modify the script:

 ```python
 import m5
 from m5.objects import *

 # existing configuration code...

 num_ticks = 1e9  # Example: 1 billion ticks
 while m5.curTick() < num_ticks:
 m5.simulate(100)  # simulate for 1 million ticks at a time
 print("Current tick:", m5.curTick())
 m5.stats.dump()  # dump the stats
 ```

   - This script will now run the simulation in chunks of 1 million ticks,
dumping the statistics after each chunk.

2. **Dumping Statistics**:
   - The `m5.stats.dump()` call will update the `stats.txt` file. Make sure
you have set up your statistics correctly in the simulation configuration
so that they are captured and written to the file.

3. **Resuming the Simulation**:
   - The loop will automatically continue the simulation until it reaches
the specified number of ticks. There's no need for explicit "resume"
commands, as `m5.simulate()` both starts and resumes the simulation.

4. **Periodic Checkpoints (Optional)**:
   - If you want to be able to resume the simulation from a particular
point, not just dump statistics, consider using checkpoints. You can create
a checkpoint at each loop iteration or at

specific intervals. Here's how you can add checkpoint creation:

   ```python
   checkpoint_interval = 1e7  # Example: every 10 million ticks
   next_checkpoint = checkpoint_interval

   while m5.curTick() < num_ticks:
   m5.simulate(min(checkpoint_interval, num_ticks - m5.curTick()))
   print("Current tick:", m5.curTick())
   m5.stats.dump()  # dump the stats

   if m5.curTick() >= next_checkpoint:
   m5.checkpoint('checkpoint%d' % (m5.curTick()))
   next_checkpoint += checkpoint_interval
   ```

   - This will create a checkpoint file every 10 million ticks (or at the
specified interval).

5. **Considerations for FS Mode**:
   - In FS mode, especially with complex simulations, be aware that there
might be additional complications, such as device states and interactions
with the simulated OS. Always test your modified script to ensure that it
behaves as expected.

6. **Running the Modified Script**:
   - Once you've modified your `fs_linux.py` script, run it as you normally
would to start the simulation.

By following these steps, you should be able to achieve your goal of
suspending the FS simulation at specific tick intervals, dumping the stats,
and then resuming the simulation. Remember that gem5 is a complex tool, and
small changes in the simulation script can have significant impacts on the
behavior and performance of your simulation, so careful testing and
validation of your modified script are recommended.

On Tue, Jan 16, 2024 at 1:16 AM elio.vinciguerra--- via gem5-users <
gem5-users@gem5.org> wrote:

> Or, at least, I would need to do it in such a way as to have the
> historical progression of the "stats.txt" file during the simulation. So I
> need to suspend the simulation at a certain tick, get the "stats.txt" file,
> resume the simulation, or I need a solution that allows me to dump at a
> certain tick.
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[gem5-users] Re: Can CloudSuite Run on FullSystem Simulation

2023-12-21 Thread Jason Lowe-Power via gem5-users
Hello,

Note: the output below is from the gem5-GPT. If you have chatGPT Plus you
can access this GPT/bot at https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt.
I've made some inline comments as well.

Hello!

Regarding your queries about running CloudSuite on gem5 in Full System (FS)
mode with x86 ISA:

### Q1: Simulating CloudSuite in Full System Simulation

Yes, gem5 can simulate the CloudSuite benchmark suite in Full System
simulation mode. Here's what you need to know:

- **Full System (FS) Simulation**: In FS mode, gem5 simulates an entire
machine including the processor, memory system, and I/O devices. This mode
is more comprehensive and suitable for complex benchmarks like CloudSuite.

- **x86 ISA Support**: gem5 supports various ISAs, including x86. Ensure
you have the correct configuration for x86 to accurately simulate the
environment CloudSuite expects.

- **Benchmark Compatibility**: CloudSuite, being a collection of
applications designed to mimic cloud computing workloads, should be
compatible with gem5's FS mode. However, the complexity of these benchmarks
might require specific configurations in gem5, especially regarding the
system's memory, network, and I/O setups.

- **Preparation**: You'll need to prepare disk images with the CloudSuite
software installed. This step is crucial as gem5 simulates from the booting
of an OS. Ensure your disk image has everything needed for CloudSuite to
run.

### Q2: Using Docker in Simulated System in FS Mode

Running Docker inside a simulated system in gem5's FS mode presents
additional complexity:

- **Feasibility**: Technically, it's feasible to run Docker inside gem5's
FS mode as long as the simulated system meets Docker's requirements. This
includes kernel compatibility, necessary kernel modules, and sufficient
system resources.

- **Performance Considerations**: Be aware that running Docker, which adds
additional layers of abstraction and resource requirements, might
significantly slow down the simulation. gem5 models systems at a very
detailed level, and the added complexity of Docker containers could impact
performance. [Editor's note: Running your app in docker shouldn't slow the
simulation down much if at all]

- **Configuration and Limitations**: Ensure that the simulated environment
(including the kernel and hardware configurations) supports Docker. Some
features used by Docker, like certain network configurations or specific
kernel modules, might not be fully supported in gem5's simulated
environment.

- **Debugging and Troubleshooting**: If you encounter issues, utilize
debugging techniques like `DPRINTF` in C++ or `print()` in Python within
gem5 to diagnose problems. Be prepared for a potentially complex debugging
process given the intricacies of both Docker and FS simulation.

 Recommendations:

1. **Start Simple**: Before attempting to run CloudSuite with Docker in FS
mode, start with simpler benchmarks to ensure your gem5 setup is correctly
configured.

2. **Documentation and Community Support**: Utilize gem5 documentation and
community forums for specific guidance on complex setups like yours.

3. **Incremental Approach**: Gradually build your simulation complexity.
Start with basic FS simulation, then introduce CloudSuite, and finally
attempt Docker integration.

Feel free to ask more specific questions if you encounter particular issues
or need guidance on specific aspects of setting up or running your
simulation!

On Thu, Dec 21, 2023 at 3:35 AM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to run CloudSuite on FullSystem Simulation using x86 ISA.
>
> Q1) I would like to know if gem5 can simulate such a benchmark suite
> (CloudSuite) in Full System simulation.
>
> Q2) Also, I would like to know if starting/using Docker inside the
> simulated system in the FS mode is supported.
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Adding 9p support to the riscv-fs platform not working

2023-10-04 Thread Jason Lowe-Power via gem5-users
Hi Thilo,

My guess is that you need to add a node to the device tree. I would look at
the device tree generated for Arm and see if you can pattern match what you
need to add for RISC-V.

Cheers,
Jason

On Mon, Oct 2, 2023 at 1:12 AM Thilo Voertler via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
>
>
> I’m trying to add support for 9p to the riscv-fs platform
> (configs/example/gem5_library/riscv-fs.py) similar to the way it was done
> for arm systems using the def attach_9p function
> (configs/common/FSConfig.py).
>
> Summary:
>
>
>
> When trying to mount on the guest I get an error
>
> mount -t 9p -o
> trans=virtio,version=9p2000.L,aname=/gem5rundir/m5out/9p/share gem5 /mnt/9p
>
> mount: mounting gem5 on /mnt/9p failed: No such file or directory
>
>
>
> The reason seems to be that VirtIO9PDiod device is not set up correctly
> under my Platform or Linux so that Linux can find the gem5 tag used for
> sharing.
>
>
>
> Details:
>
> I created my own board, which derives from the RiscvBoard and overwrites
> the function:
>
>
>
> class COSRiscvBoard(RiscvBoard):
>
> @overrides(AbstractSystemBoard)
>
> def _setup_io_devices(self) -> None:
>
> super()._setup_io_devices()
>
> self.add_riscv_9p()
>
> def add_riscv_9p(self):
>
> print(f"Function _setup_board Adding 9p device to platform")
>
> self.viopci = PciVirtIO(pci_bus=0, pci_dev=1, # Hardcoded for the
> platform, Ethernet in RiscV Board is 0
>
>pci_func=0, InterruptPin=1,
>
>InterruptLine=1)
>
> self.viopci.vio = VirtIO9PDiod()
>
> viodir = os.path.realpath(os.path.join(m5.options.outdir, "9p"))
>
> self.viopci.vio.root = os.path.join(viodir, "share")
>
> self.viopci.vio.socketPath = os.path.join(viodir, "socket")
>
> os.makedirs(self.viopci.vio.root, exist_ok=True)
>
> if os.path.exists(self.viopci.vio.socketPath):
>
> os.remove(self.viopci.vio.socketPath)
>
>
>
> self.viopci.host = self.platform.pci_host
>
> self.viopci.pio = self.iobus.mem_side_ports
>
> self.viopci.dma = self.iobus.cpu_side_ports
>
>
>
> I rebuilt the Linux with virtio9p support as described in
> http://old.gem5.org/WA-gem5.html under guest system requirements. During
> boot I see the new attached virtio-pci device (in Addition to the Ethernet
> device of the platfrom).
>
> [1.824575] pci-host-generic 3000.pci: host bridge /soc/pci ranges:
>
> [1.825257] pci-host-generic 3000.pci:   No bus range found for
> /soc/pci, using [bus 00-ff]
>
> [1.826709] pci-host-generic 3000.pci:   IO
> 0x002f00..0x002f00 -> 0x00
>
> [1.827637] pci-host-generic 3000.pci:  MEM
> 0x004000..0x007fff -> 0x00
>
> [1.899228] pci-host-generic 3000.pci: ECAM at [mem
> 0x3000-0x3fff] for [bus 00-ff]
>
> [1.902419] pci-host-generic 3000.pci: PCI host bridge to bus
> :00
>
> [1.902923] pci_bus :00: root bus resource [bus 00-ff]
>
> [1.903470] pci_bus :00: root bus resource [io  0x-0x]
>
> [1.904121] pci_bus :00: root bus resource [mem
> 0x4000-0x7fff] (bus address [0x-0x3fff])
>
> [1.905119] pci :00:00.0: [8086:1075] type 00 class 0x02
>
> [1.906011] pci :00:00.0: reg 0x10: [mem 0x4000-0x4001]
>
> [1.906941] pci :00:00.0: reg 0x30: [mem 0x4000-0x47ff pref]
>
> *[1.911587] pci :00:01.0: [1af4:1000] type 00 class 0xff*
>
> *[1.912321] pci :00:01.0: reg 0x10: [io  0x-0x001f]*
>
> [1.913207] pci :00:01.0: reg 0x30: [mem 0x4000-0x47ff pref]
>
> [1.923427] pci :00:00.0: BAR 0: assigned [mem
> 0x4000-0x4001]
>
> [1.924118] pci :00:00.0: BAR 6: assigned [mem
> 0x4002-0x400207ff pref]
>
> [1.924809] pci :00:01.0: BAR 6: assigned [mem
> 0x40020800-0x40020fff pref]
>
> [1.925486] pci :00:01.0: BAR 0: assigned [io  0x-0x001f]
>
>
>
> However I get an error when loading the virtio-pci driver
>
> [1.939684] virtio-pci :00:01.0: enabling device ( -> 0001)
>
> [1.940263] virtio-pci :00:01.0: virtio_pci: leaving for legacy
> driver
>
> [1.940742] virtio-pci: probe of :00:01.0 failed with error -12
>
> There is also no device that provides the gem5 tag under
> /sys/bus/virtio/drivers/9pnet_virtio/virtio/mount_tag files (
> https://www.kernel.org/doc/Documentation/filesystems/9p.txt)
>
> root@UCanLinux:~ # ls /sys/bus/virtio/drivers/9pnet_virtio/
>
> bindmodule  uevent  unbind
>
> I also checked that diod is in the path and I get message that it was
> started.
>
>
>
> Anyone an idea why it is not working or what I can try to run it again
>
>
>
> Best Regards,
>
>
>
> Thilo
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[gem5-users] Re: Sharing cache lines at memory level

2023-09-18 Thread Jason Lowe-Power via gem5-users
Hi Arteen,

This is dependent on the Ruby coherence protocol you are using. It sounds
like you're using MESI_Three_Level or MESI_Two_Level in which the LLC is a
single logical cache that is banked between different instances. If you
want something more like "cluster-private" LLC slices, then you'll have to
use a different coherence protocol. CHI may be the most flexible for your
use case.

See the following documentation for more information
https://www.gem5.org/documentation/general_docs/ruby/
https://www.gem5.org/documentation/general_docs/ruby/CHI/

In the sidebar you can find descriptions of each of the other protocols as
well.

Cheers,
Jason

On Sun, Sep 17, 2023 at 11:32 AM Arteen Abrishami via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I’m an undergraduate student working on a project where I am to evaluate a
> hardware accelerator my PhD student is working on in a chiplet-based
> system. We are running garnet2.0, and it would be infeasible to port it to
> garnet3.0.
>
> So far, I’ve had success configuring a chiplet configuration in Python and
> I’ve also been able to achieve a 1:n (n chiplets) memory to LLC mapping.
> Unfortunately, we found that there was deadlock under certain workloads.
> This led to the discovery that cache lines were not able to be shared
> across multiple chiplets (from memory -> cache).
>
> To simulate accurately, this is a requirement. I’ve been attempting to
> look into this issue, but I wanted to ask here for insight. I was able to
> find success with creating “cluster-private” LLC chiplets with built-in
> gem5 configurations. It doesn’t seem likely this feature would be provided
> without also allowing cache lines to be shared across the clusters.
>
> Could anyone point me in the right direction?
>
> Thanks,
> Arteen
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[gem5-users] Re: Libthreads for Gem5

2023-09-14 Thread Jason Lowe-Power via gem5-users
Hi George,

You can use pthreads. There's no need for m5threads anymore. The only
wrinkle is that you have to make sure the cross-compiled dynamic libraries
are in the right place. You can use the "redirect paths" option to map a
path on the host to a different location in the guest (like volumes in
docker).

Cheers,
Jason

On Thu, Sep 14, 2023 at 10:29 AM George Michelogiannakis via gem5-users <
gem5-users@gem5.org> wrote:

> Good morning everyone,
>
> Does anyone know if "m5threads" is available for RISC-V? I'm trying to
> compile an OpenMP code for RISC-V, hopefully avoiding FS.
>
> Thank you
>
>
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[gem5-users] Re: Generate Multiple Trace Files for Multi-Threaded Workloads on FS

2023-09-12 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,

Thank you for your questions on the mailing list. I will try to answer them
as best as I can.

- The trace CPU model was not designed to support multithreaded
applications or multiple cores. It was only tested with single-threaded
benchmarks in both SE and FS mode. Therefore, generating multiple trace
files for different threads/cores may not work as expected or may cause
errors.
- The O3 CPU is capable of traces, but I don't know if/how that will work
with multiple cores. You'll have to dig in and modify the code, most likely.
- Instructions should already have that information (i.e., the StaticInst
class). You can extend the trace formats as well by modifying that code.

Cheers,
Jason

On Fri, Sep 8, 2023 at 5:19 PM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I am seeking to generate multiple trace files for multi-threaded workloads
> that run in FS (Full-System simulation mode). My plan is to configure the
> simulation to have multiple cores, boot the image, run the workload, and
> record the traces of instructions that run on each core, such that each
> core/thread has its own trace file. My end goal is to have a number of
> trace files, each represent a core or a thread.
>
> Questions:
>
>- Is gem5 capable of generating multiple trace files?
>- I am checking the Trace CPU Model page on gem5
>
>website. It has this statement "The traces have been developed for
>single-threaded benchmarks simulating in both SE and FS mode". Does this
>mean generating multiple trace files for different threads/cores
>is unsupported by gem5?
>- Is the O3 CPU capable of recording such traces? The goal is to
>generate traces using an Out-of-Order superscalar CPU.
>- I may have to add a few more fields to the instruction class, such
>as a boolean variable to check if the instruction is a branch for example.
>which file(s) should I look at?
>
>
> Looking forward to your answer.
>
> Thanks,
> ~Abdelrahman
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: can't run riscv simulation with any CPU model except Atomic

2023-08-23 Thread Jason Lowe-Power via gem5-users
Hello,

These scripts are tested nightly, so they should be working. How long did
you wait for the terminal output? It can take 15-30 minutes before you see
any output.

Cheers,
Jason

On Wed, Aug 23, 2023 at 5:00 AM oe-fans via gem5-users 
wrote:

> hi, all
>
> I built gem5 v23.0.1.0, I can run configs/example/lupv/run_lupv.py with
> atomic CPU model successful. But when I run it with TIMING model, there is
> nothing appear in m5term.
> I try configs/example/gem5_library/riscv-fs.py or riscvmatched-fs.py,
> neither of them can boot.
>
> What's wrong with my gem5 build? Are there anything I missing?
>
>
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[gem5-users] Re: Memory allocation when using heterogeneous memory controllers

2023-08-21 Thread Jason Lowe-Power via gem5-users
Hi Jaeyong,

No, there's no way to distinguish the memory types in SE mode. You will
have to modify the memory allocator or use `Process.map` (
https://github.com/gem5/gem5/blob/develop/src/sim/Process.py#L39) to map
specific virtual addresses to physical addresses. If you use `map` you can
then use `mmap` in your guest application to map specific virtual addresses.

In FS mode, you would have to somehow declare different NUMA nodes for the
different memory types (e.g., via the device tree). Then, you could use
`numactrl` or `libnuma` to allocate in specific NUMA nodes.

Cheers,
Jason

On Sun, Aug 20, 2023 at 11:12 PM 이재용 via gem5-users 
wrote:

> As far as I know, gem5 supports heterogeneous memory controllers
> (src/mem/hetero_mem_ctrl.cc), which can have both DRAM and NVM devices
> attached to them.
>
> Let's say I allocate 0-512-MiB of physical addresses for DRAM and
> 512-MiB-1024-MiB for NVM.
>
> Is there a way to distinguish between DRAM and NVM regions when running a
> program in SE-Mode?
> For example, I want to keep my program code and stack in DRAM and dynamic
> memory (allocated via malloc) in NVM. Do I need to modify gem5's memory
> allocator to do this?
>
>
>
> Best,
> Jaeyong Lee
>
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[gem5-users] Re: How to solve "AttributeError: Can't resolve proxy" error when l1icache is replaced with new module

2023-08-17 Thread Jason Lowe-Power via gem5-users
Hi Shaikhul,

I think that you have somehow unset the `assoc` parameter (or set it to
None) in the cache. Can you provide us the exact script you're running, the
command line that you use to run, the information about the gem5 build
(variant used), the version of gem5 you're using, and any modifications you
have made to gem5?

Thanks,
Jason

On Wed, Aug 16, 2023 at 1:13 PM Khan Shaikhul Hadi via gem5-users <
gem5-users@gem5.org> wrote:

> I have my dedicated controller module that have L1Icache as member
> function (I want to interfere with all incoming and outgoing request and
> response from cache and may modify based on some algorithm) with similler
> parameter and port structure.  In PrivateL1SharedL2CacheHierarchy cache
> hierarchy, I wanted to change the L1Cache with This Controller module. When
> I run my configuration, I encountered this error:
>
> Error in unproxying param 'assoc' of board.cache_hierarchy.l1icaches0.tags
> AttributeError: Can't resolve proxy 'assoc' of type 'Int' from
> 'board.cache_hierarchy.l1icaches0.tags'
>
> Anyone have any idea how I could solve this?
>
> Note: To me it seems like, gem5 trying to create the structure of the
> system where the board trying to find the l1icaches0 directory and trying
> to get tag value from there. I could not find where it was happening. Also,
> I have found some questions where others faced the same type of error ( not
> exactly the same error) and creating a subsystem may resolve it. But I
> could not find any resources on how this subsystem structure works in gem5
> and how to make your own subsystem. Any known resources on that?
>
> Best
> Shaikhul
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[gem5-users] Re: Prefetching during instruction decode

2023-08-16 Thread Jason Lowe-Power via gem5-users
Hi Pedro,

On quick suggestion: It may make sense to put the prefetcher in the CPU
model code (e.g., during the decode stage in the O3CPU) instead of in the
decode logic of the ISA. After you get the `StaticInst` from the decoder,
you should be able to push prefetch requests into the instruction cache
from there. Hopefully this helps some.

Cheers,
Jason

On Wed, Aug 16, 2023 at 11:21 AM Pedro Corrêa Rigotto via gem5-users <
gem5-users@gem5.org> wrote:

> For my research, I need to do some instruction prefetching during the
> decoding step of specific instructions, which are not memory access
> instructions. I am using Syscall Emulation mode, and I'm studying the x86,
> ARM and RISC-V ISAs, however I will use whichever one works for this
> purpose. I tried looking into the gem5 code to figure out how to do this,
> however I encountered a big roadblock, since most of the code which deals
> with instruction decoding and execution is generated by the compiler. I was
> wondering if anyone knows a way to do this, or knows some reference of
> someone who did prefetching research on gem5. Any help would be much
> appreciated.
>
> Best regards,
> Pedro Corrêa Rigotto
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[gem5-users] Re: RISCV Vector Extension in gem5

2023-08-04 Thread Jason Lowe-Power via gem5-users
Hello,

No, we don't have any explicit documentation on this. I think that the
fault-only-first are the few instructions that are not implemented.

Cheers,
Jason

On Thu, Aug 3, 2023 at 10:25 PM X BJ  wrote:

> Hello,
>
> Thank you very much, it is exactly what I need !
>
> BTW, is there a instruction list that supported ? Because I notice that
> vector load unit-stride fault-only-first is not supported, I'm wondering if
> there is a list/site/doc about instructions and other stuff in RVV 1.0.
> Thanks again !
>
> Best regards
> xbj
>
> ------
> *发件人:* Jason Lowe-Power 
> *发送时间:* 2023年8月3日 22:33
> *收件人:* The gem5 Users mailing list 
> *抄送:* 谢 佰杰 
> *主题:* Re: [gem5-users] RISCV Vector Extension in gem5
>
> Hello,
>
> Initial RVV support was just merged today! See
> https://github.com/gem5/gem5/pull/83
>
> On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users 
> wrote:
>
> Hi all,
> I found that both rivosInc and RALC888 used to work on  RISC-V Vector
> Extension in gem5, but both of them seem to be busy with other things,
> leaving  gem5-rvv 1.0 undone.
> I'm wondering what is the status/plan about RISCV-V Vector Extension in
> gem5 ?
>
> Thanks + regards
> xbj
>
>
>
>- [GEM5-1212] Add RISC-V vector support (RVV) version 1.0 - Jira
>(atlassian.net) <https://gem5.atlassian.net/browse/GEM5-1212>
>
>
>- RALC88/gem5: This is an read-only mirror of the gem5 simulator. The
>upstream repository is stored in https://gem5.googlesource.com, code
>reviews should be submitted to https://gem5-review.googlesource.com/. The
>mirrors are synchronized every 15 minutes. (github.com)
><https://github.com/RALC88/gem5>
>
>
>
>
>
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[gem5-users] Re: RISCV Vector Extension in gem5

2023-08-03 Thread Jason Lowe-Power via gem5-users
Hello,

Initial RVV support was just merged today! See
https://github.com/gem5/gem5/pull/83

On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users 
wrote:

> Hi all,
> I found that both rivosInc and RALC888 used to work on  RISC-V Vector
> Extension in gem5, but both of them seem to be busy with other things,
> leaving  gem5-rvv 1.0 undone.
> I'm wondering what is the status/plan about RISCV-V Vector Extension in
> gem5 ?
>
> Thanks + regards
> xbj
>
>
>
>- [GEM5-1212] Add RISC-V vector support (RVV) version 1.0 - Jira
>(atlassian.net) 
>
>
>- RALC88/gem5: This is an read-only mirror of the gem5 simulator. The
>upstream repository is stored in https://gem5.googlesource.com, code
>reviews should be submitted to https://gem5-review.googlesource.com/. The
>mirrors are synchronized every 15 minutes. (github.com)
>
>
>
>
>
>
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[gem5-users] Re: ARM KVM Switch + Restoration

2023-08-01 Thread Jason Lowe-Power via gem5-users
This should work... can you provide an example script and specific commands
to reproduce the error?

Thanks,
Jason

On Tue, Aug 1, 2023 at 11:24 AM AbdelQader AlKilany via gem5-users <
gem5-users@gem5.org> wrote:

> Hello gem5 users,
>
>
>
> I was wondering if it is possible to start a FS ARM simulation using KVM,
> switch to another CPU type such as Atomic, then restore the CPU
> type(Atomic), and maybe even switch again to O3.
>
>
>
> I have tried to do this using the standard library but I have encountered
> some errors such as:
>
>
>
> build/ALL/sim/serialize.hh:379: fatal: fatal condition !paramInImpl(cp,
> name, param) occurred: Can't unserialize 'board.processor.start.core:_pid'
>
>
>
>
>
> I am using:
>
> platform VExpress_Gem5_V1 (since it’s the only one I found to work with
> KVM)
>
> release ArmRelease.for_kvm()
>
>
>
> I used this for both the checkpointing and restoring simulations (I found
> the release worked for non KVM CPUs when not restoring).
>
> Thank you for any help!
>
> Abdal
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[gem5-users] Re: Unable to boot Linux in FS mode

2023-07-28 Thread Jason Lowe-Power via gem5-users
Hi Zhenwen,

The actual error is one line higher in the kernel output:
`/lib/x86_64-linux-gnu/libc.so.6: CPU ISA level is lower than required`

I believe we fixed the incompatibility of gem5-x86 with newer kernels in
gem5-v22.1, but it is definitely fixed in gem5-v23.0. I suggest either
updating gem5 or downgrading your kernel and Ubuntu image to something
older.

See https://gem5-review.googlesource.com/c/public/gem5/+/64831 and
https://gem5-review.googlesource.com/c/public/gem5/+/65492

Cheers,
Jason

On Thu, Jul 27, 2023 at 9:40 PM Zhewen Hu via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> My OS is Ubuntu 22 and I am using gem5 v22.0.0.1, when I boot a Ubuntu 22
> image I got error:
> *Kernel panic - not syncing: Attempted to kill init! exitcode=0x7f00*
>
> Attached are the logs, could anyone help to find the problem?
>
> Thanks in advance.
>
> Best regards,
> Zhenwen Hu
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[gem5-users] Re: Using Traffic Generators with Ruby

2023-07-27 Thread Jason Lowe-Power via gem5-users
Hi Vishnu,

I do not believe there is any way to direct traffic to a particular message
buffer (e.g, `requestToDir`). Ruby is in some sense a "black box" that only
has port inputs (which are directed to a sequencer) and port output (via
`requestToMemory`).

That said, this is a cool idea! I would encourage you to develop this
support if it's something that you would find useful for your work. In
fact, I think this support could be very useful upstream for testing!

Cheers,
Jason

On Wed, Jul 26, 2023 at 5:52 AM VISHNU RAMADAS via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I have a few traces that I recorded at the input port of the directory
> (CHI protocol). I would like to replay these by injecting them directly
> into the Ruby network/directory. Requests in these traces contain
> information about the type of coherent request/snoop response they send and
> I want to inject traffic that includes this. Looking around, I found that
> the Garnet standalone protocol does something similar since all it does is
> inject traffic into the network. Is combining the Garnet standalone
> protocol with the CHI model the only way to send messages to the
> directory? Or are there other approaches that directly inject coherent
> traffic into the directory (without the need for a sequencer or dummy
> cache)?
>
> Thanks,
> Vishnu
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[gem5-users] Re: stopping simulation via ThreadContext::halt()

2023-07-27 Thread Jason Lowe-Power via gem5-users
Hi David,

I think you want to call the function `exitSimLoopNow` or `exitSimLoop`.
You can call this function from an instruction implementation, (e.g.,
halt), I believe.

See https://github.com/search?q=repo%3Agem5%2Fgem5+exitSimLoop+=code

Cheers,
Jason

On Wed, Jul 26, 2023 at 9:39 AM David Bears via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to create a fault which will stop the simulation. I tried
> calling ThreadContext::halt from within FaultBase::invoke (or rather a
> subclass of FaultBase). This successfully stops simulation of the CPU,
> but then it endlessly simulates memory refreshes.
>
> So how should I properly shut down the simulated system so that the
> gem5.opt process finishes? Do I have to do something in addition to
> calling ThreadContext::halt? Is ThreadContext::halt the wrong tool for
> the job? Or perhaps do I have something else set up wrong?
>
> For context, I implemented most of the NIOS II ISA in gem5, and I am
> running an executable which is designed to run on bare metal. There is a
> particular 'magic' instruction which signals that the executable is
> finished, and I want to stop the simulation sometime after committing
> such an instruction.
>
> Thanks is advance,
> David
>
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[gem5-users] Re: Facing issue while trying to use PARSEC benchmark using Gem5

2023-07-27 Thread Jason Lowe-Power via gem5-users
Hi Abhinav,

I would suggest using the most recent version of gem5 (v23.0) and use the
gem5-resources version of parsec. See
https://resources.gem5.org/resources/x86-parsec/example?database=gem5-resources=1.0.0
for an example using parsec.

Cheers,
Jason

On Thu, Jul 27, 2023 at 2:14 AM Abhinav Kumar via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
> I'm trying to run the PARSEC benchmark using gem5. I followed the tutorial
> on the site. But, currently I'm facing one issue, the simerr file  contains
> the following:
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 457, in main
>   File "configs-parsec-tests/run_parsec.py", line 49, in 
> from system import *
>   File "/home/user-name/parsec-tests/configs-parsec-tests/system.py", line
> 37, in 
> class MySystem(LinuxX86System):
> NameError: name 'LinuxX86System' is not defined"
> I have downloaded the system configuration file from
> https://github.com/darchr/gem5art/tree/master/docs/gem5-configs/configs-parsec-tests/system
>  .
> Can you guys please help me with this?
>
> Regards,
> Abhinav
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[gem5-users] Re: Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5

2023-07-27 Thread Jason Lowe-Power via gem5-users
Hi Zitai,

You should be able to use any CPU model with the TLM interface. You can
write your own configuration file / run script that creates a
TimingSimpleCPU and connects the I/D ports to the TLM interface.

Cheers,
Jason

On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users 
wrote:

> Hi:
>
> I am a Gem5 user and currently working on system-level modeling and
> simulation using Gem5. I have encountered an issue and would greatly
> appreciate your assistance and advice.
>
> Currently, I am *using tlm_slave.py to connect with TLM memory
> successfully*. However, I noticed that when using tlm_slave.py, it
> requires pairing with the _TrafficGen CPU which is not a conventional CPU
> model; instead, it is a special module used for generating memory system
> stimuli. I would like to use the traditional processor simulator 
> *RiscvTimingSimpleCPU
> instead of the _TrafficGen CPU* to conduct more realistic
> instruction-level simulation.
>
> I am not familiar with the method of connecting RiscvTimingSimpleCPU with
> TLM memory and would like to inquire whether it is possible to achieve this
> configuration and what specific steps need to be taken.
>
> During the configuration process, would I need to modify the interface of
> RiscvTimingSimpleCPU or perform other customizations? Is the workload
> significant?
>
> Thank you very much for your help and guidance!
>
> Best regards,
>
> Zitai
>
>
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[gem5-users] Re: potential error in gem5 simulation?

2023-07-24 Thread Jason Lowe-Power via gem5-users
There's a lot of information missing in your email, but I'll make some
guesses and try to help.

If you're using x86 and you compiled lbm on your host, then most likely it
is using SSE/AVX/vector instructions that may not be implemented or
implemented incorrectly in gem5. I would expect to see warnings about
unimplemented instructions, but I don't see them in your output.

One possible way to check is to recompile without vector instructions and
try that binary.

Finally, there are a number of warnings about unimplemented syscalls. I
don't think any of those would cause a problem, but using FS mode could
improve the fidelity of your simulation.

Cheers,
Jason

On Sat, Jul 22, 2023 at 5:59 AM An Chow Lai via gem5-users <
gem5-users@gem5.org> wrote:

> To whom it may concern,
>
> I'm new to gem5, I just downloaded gem5 to simulate some spec benchmarks,
> but I encountered something which seems not making sense;
> basically, the outcome of the program simulated by gem5 does not match the
> outcome of the same program run directly on the machine. The results of two
> runs are shown below.
> I hope I can get help/corrections from you guys. Thank you.
>
> Sincerely yours,
> An-Chow
>
> direct run (which is expected and looks correct to me):
> -
> ../../exe/lbm_r_base.mytest-m64 30 reference.dat 0 0 100_100_130_ldc.of
> MAIN_printInfo:
>grid size  : 100 x 100 x 130 = 1.30 * 10^6 Cells
>nTimeSteps : 30
>result file: reference.dat
>action : nothing
>simulation type: lid-driven cavity
>obstacle file  : 100_100_130_ldc.of
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 1.00 maxRho: 1.00 Mass: 1.30e+06
>minU  : 0.00 maxU  : 0.00
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.998947 maxRho: 1.001139 Mass: 1.30e+06
>minU  : 0.00 maxU  : 0.003548
>
> gem5 simulated run (which does not match the direct run above):
> --
> ~/Work/gem5/build/X86/gem5.opt
> ~/Work/gem5/configs/deprecated/example/se.py
> --cmd="../../exe/lbm_r_base.mytest-m64" --option="30  reference.dat 0 0
> 100_100_130_ldc.of" --mem-size=8GB
> gem5 Simulator System.  https://www.gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 23.0.0.1
> gem5 compiled Jul 22 2023 09:57:33
> gem5 started Jul 22 2023 12:50:00
> gem5 executing on Oreo-II, pid 62021
>
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
> warn: The se.py script is deprecated. It will be removed in future
> releases of  gem5.
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> src/base/statistics.hh:279: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
> system.remote_gdb: Listening for connections on port 7000
>  REAL SIMULATION 
> src/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> src/sim/mem_state.cc:443: info: Increasing stack size by one page.
> src/sim/syscall_emul.cc:74: warn: ignoring syscall set_robust_list(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall rseq(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> MAIN_printInfo:
>grid size  : 100 x 100 x 130 = 1.30 * 10^6 Cells
>nTimeSteps : 30
>result file: reference.dat
>action : nothing
>simulation type: lid-driven cavity
>obstacle file  : 100_100_130_ldc.of
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.00 maxRho: 0.00 Mass: 0.00e+00
>minU  : 0.17 maxU  : 0.235702
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.00 maxRho: 0.00 Mass: 0.00e+00
>minU  : -nan maxU  :  inf
>
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[gem5-users] Re: Question about pulling in the latest version of gem5 with the bootcamp 2022 files.

2023-07-24 Thread Jason Lowe-Power via gem5-users
Hi Nick,

You should be able to `cd` to the gem5 directory, set up a remote to the
new github location (`git remote add upstream https://github.com/gem5/gem5`)
then checkout stable (`git checkout upstream/stable`). (Note: commands off
the top of my head and may have mistakes.)

That said, be careful as some of the python/stdlib APIs will have changed.
So, some of the examples may need to be updated.

Cheers,
Jason

On Sat, Jul 22, 2023 at 12:55 PM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I am using the bootcamp examples to teach my computer architecture class
> about gem5. I would like to pull in the latest version of gem5 from the
> github location. The command I am using is:
>
>
>
> git clone --recursive
> https://github.com/gem5bootcamp/gem5-bootcamp-env.git
>
>
>
> When I compile gem5, Instead of version 23, I am getting gem5 version
> 22.0.0.0. Is there a recommended way of getting the latest version?
>
>
>
> Nick
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[gem5-users] Re: Meltdown simulation & analysis in FS mode using fs.py

2023-07-20 Thread Jason Lowe-Power via gem5-users
Hi Robin,

This may be helpful:
http://www.lowepower.com/jason/visualizing-spectre-with-gem5.html

For `warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented`, this is an AVX
(or SSE) instruction that gem5 doesn't implement.

Overall, I'm not sure if gem5 is vulnerable to meltdown. I think that the
instruction is squashed when the TLB detects a page table fault and it does
not proceed to memory. You can check the O3 code to be sure, though.

Cheers,
Jason

On Thu, Jul 20, 2023 at 2:52 AM reverent.green--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I am currently working on a meltdown simulation & analysis using the fs.py
> script. Using se.py is not possible, because there is no kernel space
> mapping.
> As for the meltdown test code, I'm using this repo:
> https://github.com/IAIK/meltdown
>
> After playing a bit with the multiple parameter options, my current
> command line call is:
> "./build/X86/gem5.opt configs/example/fs.py --cpu-type=X86O3CPU
> --bp-type=LTAGE --caches --l2cache -n 8 --kernel=fs_stuff/vmlinux-5.4.49
> --disk-image=fs_stuff/x86-ubuntu.img --script=fs_stuff/test"
>
> As you can see here, I am using the X86O3CPU and the branch predictor
> LTAGE (mainly because spectre only works using LTAGE). In theory, this
> should work and the test binary is executed in the simulation, but
> unfortunately the simulation either stops right before the leak or during
> the leakage (not at an exact point everytime, sometimes 1 char, sometimes 4
> chars). The simulation does not abort by itself but looks like it's stuck
> somewhere. I waited for over one hour, but there was no extra char leaked.
> First I thought something is missing to even leak anything here, but after
> some tries do in fact leak some parts of the secret before stopping, there
> should be another problem.
>
> When the meltdown code is executed, the console log is spammed with "warn:
> instruction 'palignr_Vdq_Wdq_Ib' unimplemented"". At first I thought this
> could be the missing piece, but even with these warnings, some parts of the
> secret were leaked in some tries.
> My first goal is to get the complete leak in the result including a normal
> exit of the gem5 simulation.
>
> Does anyone here have an idea or experience at this topic? It would be
> very helpful to discuss possible problems and solutions.
>
> Thank you very much in advance.
>
> Kind regards
> Robin
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[gem5-users] Re: Adding a delay of certain ticks in gem5

2023-07-06 Thread Jason Lowe-Power via gem5-users
Hi John,

The following may be helpful:

https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/
https://www.youtube.com/watch?v=OcXA1D4b1RA=3868s

Cheers,
Jason

On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 7/6/2023 11:12 AM, John Smith via gem5-users wrote:
> > Greetings,
> > If I want to, for example, add a delay of 100 ticks before a line of
> code executes in the function
> > handleTimingReqMiss() in cache.cc, how do I go about doing that?
>
> Generally speaking, you'll have to schedule an event and then do the
> rest of the work in the event handler - something like that.  You can't
> just suspend code in the middle.  You'll probably need to break things
> into two functions to accomplish this.
>
> EM
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[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

2023-06-29 Thread Jason Lowe-Power via gem5-users
Full system mode is fully supported for RISC-V. There should not be any
problems with running pthreads on RISC-V.

(Side note: There could be a small bug in the RISC-V atomic instructions...
we're looking into it, but haven't been able to track it down.)

Cheers,
Jason

On Thu, Jun 29, 2023 at 4:05 AM Srikanta Chaitanya via gem5-users <
gem5-users@gem5.org> wrote:

> Thanks for the reply.
>
> On Thu, Jun 29, 2023, 2:11 PM Víctor Soria  wrote:
>
>> Hi Srikanta,
>>
>> In the past, I've been able to run pthreads mutex with ruby using Arm
>> and FS mode. By default, pthreads use syscalls to the OS to sleep or
>> wake up threads. As far as I know, FS does not work with RISCV.
>> Therefore, you could try to select the pthread mutex type to spinlock to
>> avoid having sleeps and wakes up from the OS. Notice that if you set
>> spinlock, you should never instantiate more threads than cores
>> (oversuscription). Otherwise you can have temporal deadlocks and
>> starvation.
>>
>> Regards,
>>
>> Víctor.
>>
>> On 29/6/23 9:03, Srikanta Chaitanya via gem5-users wrote:
>> > Hi ,
>> > I am running pthreads matmul program for riscv in se mode , but with
>> > lock and unlock instructions I am getting read error in Ruby ..
>> > Do i have to compile with mthreads ..
>> >
>> > Thanks
>> > Chaitanya
>> >
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[gem5-users] Re: simulate a multi-core processor with Gem5

2023-06-20 Thread Jason Lowe-Power via gem5-users
Hello,

You may also find the "Learning gem5" documentation
https://www.gem5.org/documentation/learning_gem5/introduction/ and the
bootcamp videos
https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3
useful.

Cheers,
Jason

On Tue, Jun 20, 2023 at 10:49 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 6/20/2023 10:41 AM, 中国石油大学张天 via gem5-users wrote:
> > How to simulate a multi-core processor with Gem5, such as how to write
> configuration files? For
> > example, in the following form:
>
> You don't write config files.  You write python code that creates
> instances of python classes.  The gem5 system will instantiate the
> corresponding C++ classes and connect everything together as the
> python objects indicate.
>
> Regards - EM
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[gem5-users] Re: About Risc-V custom ISA

2023-06-20 Thread Jason Lowe-Power via gem5-users
Hello,

I believe you would have to modify your compiler to emit the instruction to
avoid using embedded assembly.

Cheers,
Jason

On Tue, Jun 20, 2023 at 10:36 AM 中国石油大学张天 via gem5-users <
gem5-users@gem5.org> wrote:

> When I have customized a RISC-V instruction, I want to know how to make
> the load program execute it naturally, without using embedded assembly? At
> present, I only know how to use embedded assembly to force this custom
> instruction to run.
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[gem5-users] Re: Writing a script to run multiple simulations at once

2023-06-14 Thread Jason Lowe-Power via gem5-users
Hi all,

You can use python multiprocessing with gem5. See
https://github.com/gem5/gem5/tree/develop/src/python/gem5/utils/multiprocessing
for details.

So, in theory, you can create scripts such that you can run `./gem5 run.py`
which will run a set of different experiments. You could potentially even
send a subset of stats back to the main `run.py` script for
post-processing, though I haven't tested that, yet.

We are planning to add extensions to the simulator module to make this more
user friendly in gem5 23.1 (the release after gem5 23.0).

Cheers,
Jason

On Wed, Jun 14, 2023 at 11:01 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 6/14/2023 11:30 AM, Derek Christ wrote:
> > Hello Eliot Moss,  [one ell please]
>
> > a shared Python file with parameter settings sounds useful.
>
> > What I meant with running gem5 without the gem5 executable was to use the
> > compiled library directly from the Python configuration script.
>
> > From what I have seen, the gem5 executable sets up some internal state
> and
> > then directly calls the embedded Python interpreter to launch the
> > user-provided script.
>
> > But as I see it there is no technical reason why it shouldn't be
> possible to
> > call this setup routine directly from Python. This would reduce the
> > complexity to only one single Python script.
>
> Well, there may remain value to having a standard setup/run script that
> invokes a user supplied script.  It helps keep gem5 per se separate from
> the
> user's setup / configuration - a principle of modularity.
>
> A quick look at main.cc suggests you may be right that this *could* be
> done,
> though I have no idea what those various setup functions do and whether
> any of
> that would be hard to do from python.  What I suppose I am missing is the
> motivation - why such a change would be substantially better.  My
> applications
> tend to be quite complex and I find I need the layers of script, for
> various
> reasons.  Maybe this has more to do with preference to write in python vs
> bash
> scripts vs C++ code.
>
> gem5 is not currently packaged as a library, I don't think, though I
> suppose
> it could be.  Given the amount of existing projects and infrastructure, one
> would need to continue to support the current way of doing things as well.
> This might further complicate the system and its maintenance - one hopes by
> not very much.
>
> HTH - EM
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[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

2023-06-12 Thread Jason Lowe-Power via gem5-users
Hi Nick,

I think you have a typo. It's `gcr.io` as in "google *c*ontainer registry."
I believe you have an "e" instead of a "c" in your URL.

Cheers,
Jason

On Sat, Jun 10, 2023 at 7:52 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> Bobby,
>
>
>
> I tried your recommendation for docker and got an error:
>
>
>
> $ docker pull ger.io/gem5-test/gem5-tutorial-env:latestError response
> from daemon: Get "https://ger.io/v2/": tls: failed to verify certificate:
> x509: certificate is valid for *.github.com, github.com, not ger.io
>
>
>
> I have confirmed that I have docker installed and running. Is there a
> certificate procedure for get.io?
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Friday, June 9, 2023 12:00 PM
> *To:* Beser, Nicholas D. 
> *Cc:* The gem5 Users mailing list ; Ayaz Akram <
> yazak...@ucdavis.edu>; Thiago Rodrigues 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Hey Nick,
>
>
>
> The GUI work was basically just a prototype. We had ambitions to properly
> incorporate it into the project but we lacked the resources to do so. It
> should really be archived until someone wants to revive it. So I’m not
> surprised it doesn’t work. We don’t recommend using it.
>
>
>
> The RELEASE-NOTES.md file, in the root of the gem5 repository (
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md)
> should highlight all the major changes introduced in gem5 released. API
> changes should be noted there.
>
>
>
> A VM should work fine, but if you want to try something more light-weight,
> you could use Docker. The Docker image for the container we ran the
> Bootcamp in, via Codespaces, is gcr.io/gem5-test/gem5-tutorial-env:latest.
> So all you need to do is:
>
>
>
> ```
>
> docker pull gcr.io/gem5-test/gem5-tutorial-env:latest
>
> docker run -u $UID:$GID —volume :/gem5 —rm -it
> gcr.io/gem5-test/gem5-tutorial-env:latest
>
> # from here you’re in the docker container and the gem5 repo is mounted to
> “/gem5”
>
> ```
>
>
>
> (The sources for this docker image is in the Bootcamp repo, here:
> https://github.com/gem5bootcamp/gem5-bootcamp-env/tree/main/docker).
>
>
>
> Kind regards,
>
> Bobby
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
>
> On Jun 9, 2023, at 6:08 AM, Beser, Nicholas D. 
> wrote:
>
>
>
> Bobby,
>
>
>
> Thank you for your reply. I am making my way through the Bootcamp 2022
> videos and slides. So far everything seems to be working. I had already
> planned to use visual studio code as a student interface for GPU
> programming with the Jetson Orin Nano systems, so I will try to use that
> with the gem5 programming exercises. I have gem5 running on a VM system for
> my initial checkout, and we try to port it to the Jetson for the class.
>
>
>
> Is there a change document that describes the API changes? I will take a
> look at the Obtain resources to make sure my examples are current. I don’t
> recall seeing anything odd yet.
>
>
>
> I will have a challenge getting a week of viewgraphs down to two lectures,
> but my plan is to have a basic tutorial, a lecture on concurrency and
> coherence. and three discussion forums that will allow the student
> experiment and generate studies. This is an on line class, and I am
> integrating gem5 into a basic outline that follows Patterson and Hennessy’s
> book on Computer Architecture (A quantitative approach).
>
>
>
> I think the only part of Gem5 that I could not get working was the GUI
> work. I don’t think it has been updated.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Thursday, June 8, 2023 9:07 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Ayaz Akram ; Thiago Rodrigues <
> thiagor...@gmail.com>; Beser, Nicholas D. 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Sorry for a very late reply, but for the sake of clarification:
>
>
>
> Yes, I believe you should have cloned the bootcamp 2022 recurisively. I
> think both the issues highlighted in this thread were due to running a
> newer version of gem5 on top of older config scripts and resources which
> used the older API.
>
>
>
> There wasn’t much that went wrong when we used the 2022 Bootcamp repo with
> a class of 50 last year. There may be bugs but I don’t think anything
> should be glaringly broken. I think we did the gem5 Bootcamp with v22.0 of
> gem5, and v22.1 was released in December of last year, so be careful. There
> were quite a few API chances between these released. The “Obtain_resources”
> change was definitely one.
>
>
>
> I’m sorry for all the trouble your having with it. If you run into any
> additional problems please reach out to me 

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

2023-06-09 Thread Jason Lowe-Power via gem5-users
Hi Nick,

For teaching you may be able to get some inspiration from my class
assignments. Specifically, assignment 5 is about coherence:
https://jlpteaching.github.io/comparch/modules/gem5/assignment5/

All of the code for my assignments can be found here under different
branches for each assignment:
https://github.com/jlpteaching/gem5-assignment-template

Cheers,
Jason

On Fri, Jun 9, 2023 at 9:08 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I will take a look at docker. I need to work up getting gem5 running on
> the Jetson Nano. I am not sure if docker works on the Nano.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Friday, June 9, 2023 12:00 PM
> *To:* Beser, Nicholas D. 
> *Cc:* The gem5 Users mailing list ; Ayaz Akram <
> yazak...@ucdavis.edu>; Thiago Rodrigues 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Hey Nick,
>
>
>
> The GUI work was basically just a prototype. We had ambitions to properly
> incorporate it into the project but we lacked the resources to do so. It
> should really be archived until someone wants to revive it. So I’m not
> surprised it doesn’t work. We don’t recommend using it.
>
>
>
> The RELEASE-NOTES.md file, in the root of the gem5 repository (
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md)
> should highlight all the major changes introduced in gem5 released. API
> changes should be noted there.
>
>
>
> A VM should work fine, but if you want to try something more light-weight,
> you could use Docker. The Docker image for the container we ran the
> Bootcamp in, via Codespaces, is gcr.io/gem5-test/gem5-tutorial-env:latest.
> So all you need to do is:
>
>
>
> ```
>
> docker pull gcr.io/gem5-test/gem5-tutorial-env:latest
>
> docker run -u $UID:$GID —volume :/gem5 —rm -it
> gcr.io/gem5-test/gem5-tutorial-env:latest
>
> # from here you’re in the docker container and the gem5 repo is mounted to
> “/gem5”
>
> ```
>
>
>
> (The sources for this docker image is in the Bootcamp repo, here:
> https://github.com/gem5bootcamp/gem5-bootcamp-env/tree/main/docker).
>
>
>
> Kind regards,
>
> Bobby
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
>
> On Jun 9, 2023, at 6:08 AM, Beser, Nicholas D. 
> wrote:
>
>
>
> Bobby,
>
>
>
> Thank you for your reply. I am making my way through the Bootcamp 2022
> videos and slides. So far everything seems to be working. I had already
> planned to use visual studio code as a student interface for GPU
> programming with the Jetson Orin Nano systems, so I will try to use that
> with the gem5 programming exercises. I have gem5 running on a VM system for
> my initial checkout, and we try to port it to the Jetson for the class.
>
>
>
> Is there a change document that describes the API changes? I will take a
> look at the Obtain resources to make sure my examples are current. I don’t
> recall seeing anything odd yet.
>
>
>
> I will have a challenge getting a week of viewgraphs down to two lectures,
> but my plan is to have a basic tutorial, a lecture on concurrency and
> coherence. and three discussion forums that will allow the student
> experiment and generate studies. This is an on line class, and I am
> integrating gem5 into a basic outline that follows Patterson and Hennessy’s
> book on Computer Architecture (A quantitative approach).
>
>
>
> I think the only part of Gem5 that I could not get working was the GUI
> work. I don’t think it has been updated.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Thursday, June 8, 2023 9:07 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Ayaz Akram ; Thiago Rodrigues <
> thiagor...@gmail.com>; Beser, Nicholas D. 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Sorry for a very late reply, but for the sake of clarification:
>
>
>
> Yes, I believe you should have cloned the bootcamp 2022 recurisively. I
> think both the issues highlighted in this thread were due to running a
> newer version of gem5 on top of older config scripts and resources which
> used the older API.
>
>
>
> There wasn’t much that went wrong when we used the 2022 Bootcamp repo with
> a class of 50 last year. There may be bugs but I don’t think anything
> should be glaringly broken. I think we did the gem5 Bootcamp with v22.0 of
> gem5, and v22.1 was released in December of last year, so be careful. There
> were quite a few API chances between these released. The “Obtain_resources”
> change was definitely one.
>
>
>
> I’m sorry for all the trouble your having with it. If you run into any
> additional problems please reach out to me directly.
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> 

[gem5-users] Re: Multi-level TLB is implemented in performance

2023-05-18 Thread Jason Lowe-Power via gem5-users
There is not a multi-level TLB model in mainline gem5.

Cheers,
Jason

On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> Can anyone please tell me whether a multi-level TLB implementation is
> currently available for x86?
>
> Thanks
> Arun
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Yes, this is possible, and I believe it's already implemented for Arm.
>>
>> The best place to start is src/arch//tlb.cc
>>
>> Cheers,
>> Jason
>>
>> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,all. I would like to know if it is possible to implement multi-level
>>> TLB on gem5 performance by modeling the latency of TLB. If so, which files
>>> or functions should I start with?
>>> ___
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>>> To unsubscribe send an email to gem5-users-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>>
>> ___
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>> To unsubscribe send an email to gem5-users-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
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>
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[gem5-users] Re: Full System + external memory

2023-04-26 Thread Jason Lowe-Power via gem5-users
Hi Jonathan,

You can put the bridge wherever you would like. For MMIO things, you can
put it after the point of coherence, which is where we usually put the "I/O
crossbar."

You can poke around in configs/examples and util/systemc for some examples.

Cheers,
Jason

On Wed, Apr 26, 2023 at 4:30 PM Jonathan Kang  wrote:

> Thanks!
>
>
>
> Would you have an example of how to instantiate this bridge? Also, I
> imagine this bridge is right after the CPU I and D side ports and before
> any membus that Gem5 has internally right?
>
>
>
> *From: *Jason Lowe-Power 
> *Date: *Wednesday, April 26, 2023 at 4:27 PM
> *To: *The gem5 Users mailing list 
> *Cc: *Jonathan Kang 
> *Subject: *Re: [gem5-users] Full System + external memory
>
> Hi Jonathan, Absolutely! You can set up a "bridge" which will take a
> subset of addresses and route to a different gem5 port. If you can convert
> from the port interface to the AXI, then it should "just work". Note that
> there
>
> Hi Jonathan,
>
>
>
> Absolutely! You can set up a "bridge" which will take a subset of
> addresses and route to a different gem5 port. If you can convert from the
> port interface to the AXI, then it should "just work". Note that there are
> also already bindings to SystemC/TLM in gem5 as well that could serve as
> good examples.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I’m looking to integrate a Gem5 full system model with some of our
> internal IP. The IP and memory (caches) will be memory mapped. So I’d like
> it if the Gem5 full system could handle some parts of the system (file IO,
> system calls) but route requests to certain memory address regions to an
> external port (I’ve taken care of the conversion from Gem5 port to AXI
> SystemC). Is this possible?
>
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
>
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[gem5-users] Re: Full System + external memory

2023-04-26 Thread Jason Lowe-Power via gem5-users
Hi Jonathan,

Absolutely! You can set up a "bridge" which will take a subset of addresses
and route to a different gem5 port. If you can convert from the port
interface to the AXI, then it should "just work". Note that there are also
already bindings to SystemC/TLM in gem5 as well that could serve as good
examples.

Cheers,
Jason

On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users <
gem5-users@gem5.org> wrote:

> I’m looking to integrate a Gem5 full system model with some of our
> internal IP. The IP and memory (caches) will be memory mapped. So I’d like
> it if the Gem5 full system could handle some parts of the system (file IO,
> system calls) but route requests to certain memory address regions to an
> external port (I’ve taken care of the conversion from Gem5 port to AXI
> SystemC). Is this possible?
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: I really want these files for old x86 gem5

2023-04-25 Thread Jason Lowe-Power via gem5-users
Hi Xiang,

I would advise against using such old resources for current research. Using
an OS from a decade ago may not give you results that are accurate for
today's systems.

For "linux-bigswap2.img", this is just an empty disk image that was used as
swap space. You can probably use an empty file and it will probably work.
If that doesn't work, then you could create an empty disk image that is
formatted to be linux swap with qemu.

Cheers,
Jason

On Tue, Apr 25, 2023 at 7:44 AM Xiang Li via gem5-users 
wrote:

> I have to say thanks to Bobby Bruce! I saw you replied my email yesterday.
> But I didn't see it in my email list, so sorry about that.
> https://www.mail-archive.com/gem5-users@gem5.org/msg21437.html  That's
> the mails.
> I'm trying to use gem-gpu,  https://github.com/gem5-gpu, I don't know
> which version of gem5 they used. But I saw the img they used is  
> `linux-bigswap2.img`.
> I try to build my own ubuntu14 img file, but it always says
>
> Run /sbin/init as init process
> random: fast init done
> Mount failed for selinuxfs on /sys/fs/selinux:  No such file or directory
> random: init: uninitialized urandom read (12 bytes read)
> init: plymouth-upstart-bridge main process (638) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: plymouth-upstart-bridge main process (648) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: ureadahead main process (641) terminated with status 5
> init: plymouth-upstart-bridge main process (651) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: plymouth-upstart-bridge main process (654) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
>
> ``
> So I want to try the linux-bigswap2.img,
> * but the links I found in the Internet are invalid.*
>
> http://www.m5sim.org/dist/current/x86/x86-system.tar.bz2*`*
> http://www.m5sim.org/dist/current/x86/config-x86.tar.bz2
> Do you still have those files? Or do you know how to solve these problems? 
> Thanks a lot!
>
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: Question Regarding L1 Cache Transient States handling Load Hit in Ruby MOESI CMP Directory protocol

2023-03-22 Thread Jason Lowe-Power via gem5-users
Hello,

This is a great question!

The short answer is I believe that the coherence protocol is correct.
(Though, there could always be unexpected bugs.)

The slightly longer answer: You are probably seeing that the store happens
before the load in "real" time. However, in the processors' view (i.e.,
*logical* time), the load is actually happening before the store. As long
as the processors are correctly implementing their consistency models
(e.g., if they are sequentially consistent then they don't allow any
reorderings between load and store instructions within each thread), then
as long as it *appears* that the load completed before the store, then it's
a correct implementation. To put it another way, if the thread doing the
load cannot tell that the load happened after the store (in real time) then
it is safe.

It's something like the Lamport Clock:
https://en.wikipedia.org/wiki/Lamport_timestamp

We have a saying in English: "If a tree falls in a forest and no one is
there to hear it, does it make a sound?" Similarly, if a thread does a
store to an address, but no other thread can tell what the ordering needs
to be, it's OK to reorder it :).

Cheers,
Jason

On Tue, Mar 21, 2023 at 11:50 PM 章志元 via gem5-users 
wrote:

> Hi all,
>   I've been looking into the default MOESI CMP Directory Protocol, and it
> came to my attention that, regarding SM states in L1 Cache (Transient state
> during a Shared to Exclusive Upgrade due to a store miss), when a load
> arrives from the local core (which hits since the Cache is technically
> still in Shared state), the cache will return the old Shared Datablk as its
> load hit result. Will it cause incoherence issues in memory ordering
> between the core and the memory system, since the CPU commits the store
> first and then commit the load returning the old data, but the memory
> system sees the load hit finish first, and then see the GETX finish?
>   Also I already speculate that such loads will probably not arrive at the
> L1 Cache controller, since it would be blocked or forwarded with newer data
> due to outstanding stores in the lsq or the mandatory queue. I'm just
> wondering if the cache protocol itself is solid in terms of request
> ordering.
>   Thanks in advance!
> Zhang Zhiyuan
> 2023.3.22
> --
> 姓名:章志元
> 手机:17717877306
> 邮箱:zhiyuanzhan...@fudan.edu.cn
>
>
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>
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[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

2023-03-09 Thread Jason Lowe-Power via gem5-users
Yes, that's correct.

Cheers,
Jason

On Thu, Mar 9, 2023 at 9:44 AM Jonathan Kang  wrote:

> I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints.
> That’ll allow me to run it on an ARM Cycle Model.
>
>
>
> From the links you sent, it’s still Pin based and the resulting ELFies are
> x86 right? I’d want to do this for ARM.
>
>
>
> *From: *Jason Lowe-Power 
> *Date: *Thursday, March 9, 2023 at 8:15 AM
> *To: *Giacomo Travaglini 
> *Cc: *Jonathan Kang , The gem5 Users mailing list <
> gem5-users@gem5.org>
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan, We just did a tutorial on how to use ELFies with gem5. See
> https: //looppoint. github. io/hpca2023/ for details. We are able to load
> ELFies and run them in gem5. See https: //github.
> com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie. py
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an Untrusted Sender *
>
> You have not previously corresponded with this sender.
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan,
>
>
>
> We just did a tutorial on how to use ELFies with gem5. See
> https://looppoint.github.io/hpca2023/ for details.
>
>
>
> We are able to load ELFies and run them in gem5. See
> https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
> for an example.
>
>
>
> That said, we currently only support ELFies generated by the Sniper
> simulator. If you want details on how to do that, you'll have to check out
> the looppoint documentation above or contact the looppoint/ELFie authors.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, Mar 9, 2023 at 12:31 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi Jonathan,
>
>
>
> On 08/03/2023 17:47, Jonathan Kang wrote:
>
> Thanks Giacomo,
>
>
>
> A few questions:
>
>
>
>1. Who is Jason? So that I can contact him 
>
>
>
> Jason Lowe-Power, here CCed
>
>
>
>
>
>1. Regarding ELFie, I found these:
>
>
>1.
>   
> https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
>   2. https://github.com/intel/pinball2elf
>
>
>
> #2 would seem to be able to generate ELFies from the x86 pinballs that
> were captured. However, I’m unfamiliar with how ELFies work. Do they still
> capture state and thus need to inject processor state prior to simulation?
> In which case the problem still exists that the ARM Cycle Model is
> incompatible….
>
>
>
> The ELFie methodology generates guest bootcode which injects the
> architectural state before the beginning of the SimPoint
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
>
>
> Thanks,
>
>
>
> Jonathan.
>
>
>
> *From: *Giacomo Travaglini 
> 
> *Date: *Wednesday, March 8, 2023 at 6:26 AM
> *To: *The gem5 Users mailing list 
> 
> *Cc: *Jonathan Kang  
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi
> all, I’m attempting to get SPEC 2k17 to run on our performance model that
> uses an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan
>
> On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
>
> Hi all,
>
>
>
> I’m attempting to get SPEC 2k17 to run on our performance model that uses
> an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering if anyone has had experience capturing SimPoints
> using Gem5 and then running the resulting reduced binary on a Cycle Model.
> I know you can do it easily on Gem5 simple CPU in SE mode but I need it to
> work with our more accurate model.
>
>
>
> You can easily generate SimPoints with gem5 as you correctly said. The
> problem is the checkpoint incompatibility between gem5 and Cycle Model.
> (restoring the gem5 checkpoint from the CA simulator).
>
> It would be nice if we could generate an ELFie [1] from a gem5 checkpoint.
> As I have recently seen some commits mentioning ELFies you could ask Jason
> and his group if there's something going on...
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> [1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340
>
>
>
>
>
> Thanks in advance!
>
>
>
> Jonathan Kang.
>
>
>
> ___
>
> gem5-use

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

2023-03-09 Thread Jason Lowe-Power via gem5-users
Hi Jonathan,

We just did a tutorial on how to use ELFies with gem5. See
https://looppoint.github.io/hpca2023/ for details.

We are able to load ELFies and run them in gem5. See
https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
for an example.

That said, we currently only support ELFies generated by the Sniper
simulator. If you want details on how to do that, you'll have to check out
the looppoint documentation above or contact the looppoint/ELFie authors.

Cheers,
Jason

On Thu, Mar 9, 2023 at 12:31 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Jonathan,
>
>
> On 08/03/2023 17:47, Jonathan Kang wrote:
>
> Thanks Giacomo,
>
>
>
> A few questions:
>
>
>
>1. Who is Jason? So that I can contact him 
>
>
> Jason Lowe-Power, here CCed
>
>
>
>
>1. Regarding ELFie, I found these:
>   1.
>   
> https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
>   2. https://github.com/intel/pinball2elf
>
>
>
> #2 would seem to be able to generate ELFies from the x86 pinballs that
> were captured. However, I’m unfamiliar with how ELFies work. Do they still
> capture state and thus need to inject processor state prior to simulation?
> In which case the problem still exists that the ARM Cycle Model is
> incompatible….
>
>
> The ELFie methodology generates guest bootcode which injects the
> architectural state before the beginning of the SimPoint
>
>
> Kind Regards
>
>
> Giacomo
>
>
>
>
> Thanks,
>
>
>
> Jonathan.
>
>
>
> *From: *Giacomo Travaglini 
> 
> *Date: *Wednesday, March 8, 2023 at 6:26 AM
> *To: *The gem5 Users mailing list 
> 
> *Cc: *Jonathan Kang  
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi
> all, I’m attempting to get SPEC 2k17 to run on our performance model that
> uses an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan
>
> On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
>
> Hi all,
>
>
>
> I’m attempting to get SPEC 2k17 to run on our performance model that uses
> an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering if anyone has had experience capturing SimPoints
> using Gem5 and then running the resulting reduced binary on a Cycle Model.
> I know you can do it easily on Gem5 simple CPU in SE mode but I need it to
> work with our more accurate model.
>
>
>
> You can easily generate SimPoints with gem5 as you correctly said. The
> problem is the checkpoint incompatibility between gem5 and Cycle Model.
> (restoring the gem5 checkpoint from the CA simulator).
>
> It would be nice if we could generate an ELFie [1] from a gem5 checkpoint.
> As I have recently seen some commits mentioning ELFies you could ask Jason
> and his group if there's something going on...
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> [1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340
>
>
>
>
>
> Thanks in advance!
>
>
>
> Jonathan Kang.
>
>
>
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>
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>
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> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
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> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
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[gem5-users] Re: Location of gem5 dist

2023-02-17 Thread Jason Lowe-Power via gem5-users
Hi Rajesh,

You can find all of the links in this json file:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/resources.json

It's not very user-friendly, but we're working on it :)

Cheers,
Jason

On Fri, Feb 17, 2023 at 10:15 AM Rajesh Shashi Kumar via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> Where is http://dist.gem5.org/dist hosted now? I can't seem to find a
> working link to get kernels/datasets(eg Pannotia pagerank) that various
> gem5-resources or documentation point to.
>
> Thanks,
> Rajesh
>
>
>
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[gem5-users] Re: Query about Support for Chiplet Architecture

2023-01-17 Thread Jason Lowe-Power via gem5-users
Hi Zhengrong,

On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Our group has been using gem5 for architecture research for a long time,
> and we currently want to explore some ideas on modern multi-chiplet
> architectures, e.g. AMD's EPYC. We want to understand the tradeoffs of NoC
> design and coherence protocol when there are multiple chiplets connected
> together, each chiplet with its own NoC and caches and the LLC can be
> private or shared between chiplets.
>
> To start with, we want to understand the current support in gem5 for such
> systems. Specifically:
>
> 1. Are there existing scripts/configurations modelling an AMD EPYC like
> systems? We couldn't find them in gem5 or gem5 resources. Any pointers
> would be appreciated.
>

I made a WIP a couple of months ago here:
https://gem5-review.googlesource.com/c/public/gem5/+/65612. Note that this
*doesn't work*. I tried to set things up so that the LLC was a victim
cache, but those options seem to have broken the coherence. I haven't had
time to debug.

This is still using the SimpleNetwork, but adding Garnet should be
possible... once it's working ;).

Feel free to pick this up and build on top of it!


>
> 2. If not and we have to model the system by ourselves, what is a good
> starting point? The most reasonable one to us is the CHI protocol, which
> seems to be flexible enough to model the coherence protocol.
>

Yeah, this is exactly what I was thinking as well!


>
> Thanks in advance for any help you can provide.
>
> Bests,
> Zhengrong
>
> *王 钲 荣*
>
> Zhengrong Wang
> Computer Science Department
> University of California, Los Angeles
> California, USA
> 90024
>
> Work Email: seanyukig...@gmail.com
> Mobile :+1 310-447-4568
>
>
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[gem5-users] Re: DerivO3CPU panic: initiateAcc not defined: ROB fills and locks up

2023-01-06 Thread Jason Lowe-Power via gem5-users
Hi Eliot,

Unfortunately, I don't have a direct answer for you. However, I want to say
that I appreciate you keeping the mailing list updated with your progress!

Cheers,
Jason

On Fri, Jan 6, 2023 at 10:07 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 1/4/2023 11:51 PM, Eliot Moss via gem5-users wrote:
> > So, what I have found is that the bad micro-op is coming from trying to
> execute the micro-ops of an
> > INT3 macro-instruction.  The end of the sequence consists of the
> micro-ops:
> >
> > andi t0, t5, 0x1
> > br 0x803d
> > br 0x80b8
> >
> > followed by a bunch of "panic" micro-ops.  t5 holds an m5 register,
> > where the low bit supposedly indicated whether we are in long mode.
> >
> > The br micro-ops branch into long sequences of micro-ops in the "ROM".
>
> I have found out some more things about this issue.
>
> - The macro instruction is INT_I (my mistake in saying INT3), but the
>micro-ops are almost exactly the same.
>
> - My original though about a load instruction *is* connected somehow.
> Here's
>the big-picture sequence of events:
>
>1) A garden flavor load from memory (mov reg <- offset(reg)) gets stuck
> at
>the head of the ROB.  It was originally deferred because a page table
> walk
>was necessary to resolve the virtual address of the load.
>
>2) The ROB fills (all 192) entries.
>
>3) The panic happens.
>
>
> So I tried adjusting the size of the ROB, just to see what would happen.
> When
> I increased it from 192 to 500, a panic still happened.  I guess that if an
> instruction remains stuck at the head of the ROB forever, the ROB fills and
> then somehow causes the panic.
>
> When I *decreased* the ROB size from 192 to 64, the program worked.
>
> I am inclined to infer that there is (was) a bug in the O3 interactions
> that
> would make the load micro-op fully ready and not stuck at the head of the
> ROB.
>
> What I wonder is whether any similar ROB lock-up behavior has been found
> and
> fixed since 21.0.0.0.  There have been a lot of textual changes, but many
> had
> to do with names and such and did not really change what the code *does*.
> I
> am hoping someone out there can confirm one way or another whether this may
> have been found and fixed already if I can manage to move the rest of my
> changes forward to a newer release.
>
> Best - Eliot
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[gem5-users] Re: Command line options to modify the replacement policy in gem5

2022-12-16 Thread Jason Lowe-Power via gem5-users
Hi Vipin,

The interface to gem5 isn't the command line, it's a python runscript. In
your python script, you can add parameters (e.g., with optparse) which are
accessible from the command line, but this shouldn't be considered the main
interface to modifying the parameters of gem5 objects. If you want to
change the replacement policy, I suggest writing your own runscript which
has the replacement policy as an option. See
https://www.gem5.org/documentation/learning_gem5/introduction/ for more
information.

Cheers,
Jason

On Thu, Dec 15, 2022 at 9:21 PM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Dear Gem5-users,
>
> How can we modify the default replacement policy for ruby caches in gem5?
> Is there any command line option for replacement policy similar to
> "--l1d_size", "--l1d_assoc" for changing size and associativity of
> L1D-cahce?
>
> Regards,
> Vipin
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[gem5-users] Re: Panic when running gem5 Full System mode

2022-11-23 Thread Jason Lowe-Power via gem5-users
I believe the problem is with the kernel binary you are passing in. It
needs to be the path to the binary (not a directory), and it must be the
uncompressed kernel binary, not the compressed binary.

Cheers,
Jason

On Tue, Nov 22, 2022 at 11:06 AM JASPINDER KAUR via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> For me compiling attacker code using --static helped on the host machine
> before executing it with Gem5 FS mode worked.
>
> On Wed, Nov 23, 2022 at 12:25 AM William Hua via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello everyone,
>>
>> I am trying to implement a Prime+Probe attack in gem5 full system mode
>> using X86 MESI Two Level architecture. When I run the command line, the
>> process aborts and returns
>> "build/X86_MESI_Two_Level/base/loader/image_file_data.cc:54: panic: panic
>> condition sz != 2 occurred: Couldn't read magic bytes from object file"
>>
>> Can anyone tell me how I can fix this issue?
>>
>> The command line in terminal:
>> ./build/X86_MESI_Two_Level/gem5.opt configs/example/fs.py --disk-image
>> /home/issacnewton/gem5/fsimage/ubuntu-test.img --kernel
>> /home/issacnewton/gem5/linux-6.0.9/
>>
>> The full output:
>> gem5 Simulator System.  https://www.gem5.org
>> gem5 is copyrighted software; use the --copyright option for details.
>>
>> gem5 version 22.0.0.2
>> gem5 compiled Nov 22 2022 12:14:42
>> gem5 started Nov 22 2022 12:45:00
>> gem5 executing on issacnewton-950XDB-951XDB-950XDY, pid 37367
>> command line: ./build/X86_MESI_Two_Level/gem5.opt configs/example/fs.py
>> --disk-image /home/issacnewton/gem5/fsimage/ubuntu-test.img --kernel
>> /home/issacnewton/gem5/linux-6.0.9/
>>
>> Global frequency set at 1 ticks per second
>> warn: system.workload.acpi_description_table_pointer.rsdt adopting orphan
>> SimObject param 'entries'
>> warn: No dot file generated. Please install pydot to generate the dot
>> file and pdf.
>> build/X86_MESI_Two_Level/mem/dram_interface.cc:690: warn: DRAM device
>> capacity (8192 Mbytes) does not match the address range assigned (512
>> Mbytes)
>> build/X86_MESI_Two_Level/base/loader/image_file_data.cc:54: panic: panic
>> condition sz != 2 occurred: Couldn't read magic bytes from object file
>> Memory Usage: 105036 KBytes
>> Program aborted at tick 0
>> --- BEGIN LIBC BACKTRACE ---
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17c08b0)[0x55f56fbf18b0]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17e4d6c)[0x55f56fc15d6c]
>> /lib/x86_64-linux-gnu/libc.so.6(+0x42520)[0x7fe73d52e520]
>> /lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c)[0x7fe73d582a7c]
>> /lib/x86_64-linux-gnu/libc.so.6(raise+0x16)[0x7fe73d52e476]
>> /lib/x86_64-linux-gnu/libc.so.6(abort+0xd3)[0x7fe73d5147f3]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x431405)[0x55f56e862405]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x1910cd1)[0x55f56fd41cd1]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x19119e1)[0x55f56fd429e1]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17e8ea5)[0x55f56fc19ea5]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x449f75)[0x55f56e87af75]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x99bb75)[0x55f56edccb75]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4bbeb6)[0x55f56e8eceb6]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4be104)[0x55f56e8ef104]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4b09d2)[0x55f56e8e19d2]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x12b6d3)[0x7fe73e0526d3]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyObject_MakeTpCall+0x8c)[0x7fe73e00d1ac]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe765a)[0x7fe73e00e65a]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> --- END LIBC BACKTRACE ---
>> Aborted (core dumped)
>>
>> Thanks,
>> William Hua
>> ___
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>>
>
>
> --
> Jaspinder Kaur
>
> *CONFIDENTIALITY NOTICE: The contents of this 

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

2022-11-10 Thread Jason Lowe-Power via gem5-users
There are a couple of examples of using simpoints in the configs directory (
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/checkpoints/).
This will be part of the next gem5 release (coming in a couple of weeks).

We would like to start distributing some of the resources for SimPoints.
This should be coming soon.

Cheers,
Jason

On Thu, Nov 10, 2022 at 9:32 AM Jonathan Kang via gem5-users <
gem5-users@gem5.org> wrote:

> Yes, you use SimPoint with the “fast” model (something simple, with no
> timing) so that the tool knows the activity. It then determines windows of
> importance so that you can run only those windows with the cycle accurate
> model.
>
>
>
> *From: *Markus Bichl via gem5-users 
> *Date: *Wednesday, November 9, 2022 at 3:49 PM
> *To: *gem5-users@gem5.org 
> *Cc: *Markus Bichl 
> *Subject: *[gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
> Hi Jason, hi Jonathan, thanks a lot for pointing out SimPoint! I’m
> currently searching for details on how to use SimPoint with gem5. Is it
> right that I need to run the benchmarks at first using a timing CPU to take
> checkpoints at first? I guess
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jason, hi Jonathan,
>
>
>
> thanks a lot for pointing out SimPoint! I’m currently searching for
> details on how to use SimPoint with gem5. Is it right that I need to run
> the benchmarks at first using a timing CPU to take checkpoints at first? I
> guess (and hope) there is a way to generate the Simpoints in a faster way.
> Can someone give me a hint, or a maybe some kind of guidance on how to use
> Simpoint with gem5 v22? Thanks a lot!
>
>
>
> BR, Markus
>
>
>
> On 08.11.2022, at 20:10, Jonathan Kang  wrote:
>
>
>
> Something as big as Spec typically wouldn’t be simulated as a whole but
> rather, using SimPoint on a cycle-accurate model.
>
>
>
> *From: *Jason Lowe-Power via gem5-users 
> *Date: *Tuesday, November 8, 2022 at 11:05 AM
> *To: *The gem5 Users mailing list 
> *Cc: *Markus Bichl , Jason Lowe-Power <
> ja...@lowepower.com>
> *Subject: *[gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
> Hi Markus, I would expect gem5 to be at least 10,000-100,000x slower than
> your host. So, if it takes 100 seconds on the host, then I would expect
> between 1,000,000 and 10,000,000 seconds or more! That's 277-2770 hours or
> 10-100 days!! ‍
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender*
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Markus,
>
>
>
> I would expect gem5 to be at least 10,000-100,000x slower than your host.
> So, if it takes 100 seconds on the host, then I would
> expect between 1,000,000 and 10,000,000 seconds or more!
>
>
>
> That's 277-2770 hours or 10-100 days!!
>
>
>
> BTW, I actually think a 10-100,000x slowdown is on the low side if you're
> simulating multiple cores and/or using the out-of-order CPU model.
>
>
>
> In other words, running ref in gem5 to completion is not feasible :).
> There are techniques like SimPoint and other sampling methodologies that
> can help, but they come with tradeoffs, too. We're working to get some
> resources available to easily use sampling methodologies as well.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Dear gem5 users,
>
>
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
>
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
>
> I started benchmarks using these commands:
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

2022-11-09 Thread Jason Lowe-Power via gem5-users
Hi Yao,

Long-term, yes, the performance of gem5 is something that is important to
improve! We often hear this as one of our most wanted features. However,
because of the way gem5 was designed and has evolved over time,
*parallelizing* it will be very, very difficult. There are just too many
places where we have pointers between objects to easily apply parallel
discrete event simulation methodology.

Even if we could parallelize gem5, I would not expect more than a 2-4x
performance improvement. I'm not convinced there's that much potential for
independent work (again, because of the underlying design of gem5). So,
even if we could scale gem5 to multiple cores, simulating all of a SPEC CPU
ref run would be unlikely in a reasonable amount of time. Not to mention,
when the next version of SPEC CPU comes out it will be even longer!

Cheers,
Jason

On Tue, Nov 8, 2022 at 5:53 PM yaogang  wrote:

> Hi Jason,
>
>
>
>Is there any roadmap (near future not long term) to take gem5 to multi
> thread accerleration?
>
>
>
> Regards
>
> Yao
>
>
>
> *发件人:* Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:* 2022年11月9日 3:02
> *收件人:* The gem5 Users mailing list 
> *抄送:* Markus Bichl ; Jason Lowe-Power <
> ja...@lowepower.com>
> *主题:* [gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
>
>
> Hi Markus,
>
>
>
> I would expect gem5 to be at least 10,000-100,000x slower than your host.
> So, if it takes 100 seconds on the host, then I would
> expect between 1,000,000 and 10,000,000 seconds or more!
>
>
>
> That's 277-2770 hours or 10-100 days!!
>
>
>
> BTW, I actually think a 10-100,000x slowdown is on the low side if you're
> simulating multiple cores and/or using the out-of-order CPU model.
>
>
>
> In other words, running ref in gem5 to completion is not feasible :).
> There are techniques like SimPoint and other sampling methodologies that
> can help, but they come with tradeoffs, too. We're working to get some
> resources available to easily use sampling methodologies as well.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Dear gem5 users,
>
>
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
>
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
>
> I started benchmarks using these commands:
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 502.gcc_r --size test
>
>
>
> I wanted to have the results as fast as possible, so I used gem5.fast, and
> also tried the gcc benchmark with the test workload.
>
> As  I do not see any progess on the benchmarks yet, I feel there is
> something wrong. Is this a normal simulation time for SPEC CPU 2017
> benchmarks? Is it possible to track the progress of the simulations, even
> with "m5.disableAllListeners()” enabled in the system configuration?
>
> A run of 600.perlbench_s using the ref workload directly on the host
> system (server instance) took 181 seconds.
>
> Thanks a lot for your help!
>
>
>
> BR,
>
> Markus Bichl
>
>
>
> Student, Technische Universität Wien
>
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[gem5-users] Re: SPEC CPU 2017 taking days to simulate

2022-11-08 Thread Jason Lowe-Power via gem5-users
Hi Markus,

I would expect gem5 to be at least 10,000-100,000x slower than your host.
So, if it takes 100 seconds on the host, then I would
expect between 1,000,000 and 10,000,000 seconds or more!

That's 277-2770 hours or 10-100 days!!

BTW, I actually think a 10-100,000x slowdown is on the low side if you're
simulating multiple cores and/or using the out-of-order CPU model.

In other words, running ref in gem5 to completion is not feasible :). There
are techniques like SimPoint and other sampling methodologies that can
help, but they come with tradeoffs, too. We're working to get some
resources available to easily use sampling methodologies as well.

Cheers,
Jason

On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 users,
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
> I started benchmarks using these commands:
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 502.gcc_r --size test
>
> I wanted to have the results as fast as possible, so I used gem5.fast, and
> also tried the gcc benchmark with the test workload.
> As  I do not see any progess on the benchmarks yet, I feel there is
> something wrong. Is this a normal simulation time for SPEC CPU 2017
> benchmarks? Is it possible to track the progress of the simulations, even
> with "m5.disableAllListeners()” enabled in the system configuration?
> A run of 600.perlbench_s using the ref workload directly on the host
> system (server instance) took 181 seconds.
> Thanks a lot for your help!
>
> BR,
> Markus Bichl
>
> Student, Technische Universität Wien
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[gem5-users] Re: Top-down micro arch analysis

2022-10-28 Thread Jason Lowe-Power
I don't think so, but it seems like a fabulous idea! Keep us posted if you
work on it, please!

Cheers,
Jason

On Fri, Oct 28, 2022 at 11:05 AM Majid Jalili  wrote:

> Hi,
> Has anyone developed some script to do top down microarchitecture analysis
> with gem5 stats?
>
>
> https://www.intel.com/content/www/us/en/develop/documentation/vtune-cookbook/top/methodologies/top-down-microarchitecture-analysis-method.html
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[gem5-users] Re: PyGILState_Check() failure

2022-10-19 Thread Jason Lowe-Power
Can you describe what your python run script is doing?

It looks like the error is happening when dumping stats. To do this, gem5
does python->C++->python, which may be causing the problem. Though, that's
just a guess.

Can you create a minimal example that causes the error so we can reproduce
it?

Thanks,
Jason

On Wed, Oct 19, 2022 at 3:18 AM Yuan Yao  wrote:

>
> Hi,
>
>  We encountered the following error when I am using X86KvmCPU and
> TimingSimpleCPU to make checkpoints in FS.
>
>  "pybind11::object_api<>::operator() PyGILState_Check() failure."
>
>  The same problem is reproduced in Ubuntu 20.04 and 22.04.
>
>  My guess is some simobjects grabbed the lock without releasing it.
> But I am not sure.
>  Can someone hint us on how to debug such exceptions?
>
>
> == GDB stack ===
>
> #0  __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50
> #1  0x76bc8859 in __GI_abort () at abort.c:79
> #2  0x76fa0911 in ?? () from /lib/x86_64-linux-gnu/libstdc++.so.6
> #3  0x76fac38c in ?? () from /lib/x86_64-linux-gnu/libstdc++.so.6
> #4  0x76fac3f7 in std::terminate() () from
> /lib/x86_64-linux-gnu/libstdc++.so.6
> #5  0x76fac6a9 in __cxa_throw () from
> /lib/x86_64-linux-gnu/libstdc++.so.6
> #6  0x5577ef75 in pybind11::pybind11_fail (reason=0x5737f9b8
> "pybind11::object_api<>::operator() PyGILState_Check() failure.") at
> ext/pybind11/include/pybind11/detail/common.h:838
> #7  0x5621f640 in
>
> pybind11::detail::object_api
>  >::operator()<(pybind11::return_value_policy)1> (this=0x7fff2f91cb20)
> at ext/pybind11/include/pybind11/cast.h:1397
> #8  0x562175a5 in gem5::statistics::pythonDump () at
> build/X86_MESI_Two_Level/python/pybind11/stats.cc:94
> #9  0x566cf5fa in gem5::statistics::dump () at
> build/X86_MESI_Two_Level/base/statistics.cc:304
> #10 0x567e6355 in gem5::statistics::StatEvent::process
> (this=0x75ed) at build/X86_MESI_Two_Level/sim/stat_control.cc:92
> #11 0x567c64ef in gem5::GlobalEvent::BarrierEvent::process
> (this=0x5b865300) at build/X86_MESI_Two_Level/sim/global_event.cc:134
> #12 0x567bb412 in gem5::EventQueue::serviceOne
> (this=0x58b997a0) at build/X86_MESI_Two_Level/sim/eventq.cc:223
>
>
>
>
>
>
>
>
>
> När du har kontakt med oss på Uppsala universitet med e-post så innebär
> det att vi behandlar dina personuppgifter. För att läsa mer om hur vi gör
> det kan du läsa här: http://www.uu.se/om-uu/dataskydd-personuppgifter/
>
> E-mailing Uppsala University means that we will process your personal
> data. For more information on how this is performed, please read here:
> http://www.uu.se/en/about-uu/data-protection-policy
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[gem5-users] Re: HPCG on RISCV

2022-10-07 Thread Jason Lowe-Power
506572
> >> > ITER: 1 | i: 7 | j: 3 Result(i: 2.645751 | j: 1.732051 | i*j:
> >> > 4.582576): 220.089147
> >> > ITER: 1 | i: 7 | j: 4 Result(i: 2.645751 | j: 2.00 | i*j:
> >> > 5.291503): 225.380650
> >> > ITER: 1 | i: 7 | j: 5 Result(i: 2.645751 | j: 2.236068 | i*j:
> >> > 5.916080): 231.296730
> >> > ITER: 1 | i: 7 | j: 6 Result(i: 2.645751 | j: 2.449490 | i*j:
> >> > 6.480741): 237.777470
> >> > ITER: 1 | i: 7 | j: 7 Result(i: 2.645751 | j: 2.645751 | i*j:
> >> > 7.00): 244.777470
> >> > ITER: 1 | i: 7 | j: 8 Result(i: 2.645751 | j: 2.828427 | i*j:
> >> > 7.483315): 252.260785
> >> > ITER: 1 | i: 7 | j: 9 Result(i: 2.645751 | j: 3.00 | i*j:
> >> > 7.937254): 260.198039
> >> > ITER: 1 | i: 8 | j: 0 Result(i: 2.828427 | j: 0.00 | i*j:
> >> > 0.00): 260.198039
> >> > ITER: 1 | i: 8 | j: 1 Result(i: 2.828427 | j: 1.00 | i*j:
> >> > 2.828427): 263.026466
> >> > ITER: 1 | i: 8 | j: 2 Result(i: 2.828427 | j: 1.414214 | i*j:
> >> > 4.00): 267.026466
> >> > ITER: 1 | i: 8 | j: 3 Result(i: 2.828427 | j: 1.732051 | i*j:
> >> > 4.898979): 271.925446
> >> > ITER: 1 | i: 8 | j: 4 Result(i: 2.828427 | j: 2.00 | i*j:
> >> > 5.656854): 277.582300
> >> > ITER: 1 | i: 8 | j: 5 Result(i: 2.828427 | j: 2.236068 | i*j:
> >> > 6.324555): 283.906855
> >> > ITER: 1 | i: 8 | j: 6 Result(i: 2.828427 | j: 2.449490 | i*j:
> >> > 6.928203): 290.835059
> >> > ITER: 1 | i: 8 | j: 7 Result(i: 2.828427 | j: 2.645751 | i*j:
> >> > 7.483315): 298.318373
> >> > ITER: 1 | i: 8 | j: 8 Result(i: 2.828427 | j: 2.828427 | i*j:
> >> > 8.00): 306.318373
> >> > ITER: 1 | i: 8 | j: 9 Result(i: 2.828427 | j: 3.00 | i*j:
> >> > 8.485281): 314.803655
> >> > ITER: 1 | i: 9 | j: 0 Result(i: 3.000000 | j: 0.00 | i*j:
> >> > 0.00): 314.803655
> >> > ITER: 1 | i: 9 | j: 1 Result(i: 3.00 | j: 1.00 | i*j:
> >> > 3.00): 317.803655
> >> > ITER: 1 | i: 9 | j: 2 Result(i: 3.00 | j: 1.414214 | i*j:
> >> > 4.242641): 322.046295
> >> > ITER: 1 | i: 9 | j: 3 Result(i: 3.00 | j: 1.732051 | i*j:
> >> > 5.196152): 327.242448
> >> > ITER: 1 | i: 9 | j: 4 Result(i: 3.00 | j: 2.00 | i*j:
> >> > 6.00): 333.242448
> >> > ITER: 1 | i: 9 | j: 5 Result(i: 3.00 | j: 2.236068 | i*j:
> >> > 6.708204): 339.950652
> >> > ITER: 1 | i: 9 | j: 6 Result(i: 3.00 | j: 2.449490 | i*j:
> >> > 7.348469): 347.299121
> >> > ITER: 1 | i: 9 | j: 7 Result(i: 3.00 | j: 2.645751 | i*j:
> >> > 7.937254): 355.236375
> >> > ITER: 1 | i: 9 | j: 8 Result(i: 3.00 | j: 2.828427 | i*j:
> >> > 8.485281): 363.721656
> >> > ITER: 1 | i: 9 | j: 9 Result(i: 3.00 | j: 3.00 | i*j:
> >> > 9.00): 372.721656
> >> > Final Result: 372.721656
> >> >
> >> >
> >> >
> >> > As we can see in the following iterations the sqrt(1) as well as the
> >> > result is set to zero for some reason.
> >> >
> >> > ITER: 0 | i: 1 | j: 4 Result(i: 0.00 | j: 2.00 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 5 Result(i: 0.00 | j: 2.236068 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 6 Result(i: 0.00 | j: 2.449490 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 7 Result(i: 0.00 | j: 2.645751 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 8 Result(i: 0.00 | j: 2.828427 | i*j:
> >> > 0.00): 0.00
> >> > ITER: 0 | i: 1 | j: 9 Result(i: 0.00 | j: 3.00 | i*j:
> >> > 0.00): 0.00
> >> >
> >> > Please help me to resolve the accuracy issue! I think that it will
> >> > be very useful for gem5 community.
> >> >
> >> > To be noticed, I find the correct simulated tick in which the
> >> > application started in FS (using m5 dumpstats), and I start the
> >> > --debug-start, but the trace file which is generated is 10x larger
> >> > than SE mode for the same application. How can I compare them?
> >> >
> >> > Thank you in advance!
> >> > Best regards,
> >> > Nikos
> >> >
> >> > Quoting Νικόλαος Ταμπουρατζής :
> >>

[gem5-users] Re: HPCG on RISCV

2022-09-21 Thread Jason Lowe-Power
Hi Nikos,

You can use --debug-start to start the debugging after some number of
ticks. Also, I would expect that the difference should come up quickly, so
no need to run the program to the end.

For the FS mode one, you will want to just start the trace as the
application starts. This could be a bit of a pain.

I'm not really sure what fundamentally could be different. FS and SE mode
use the exact same code for executing instructions, so I don't think that's
the problem. Have you tried running for smaller inputs or just one
iteration?

Jason



On Wed, Sep 21, 2022 at 9:04 AM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> Iam trying to add --debug-flags=Exec (building the gem5 for gem5.opt
> not for gem5.fast which I had) but the debug traces exceed the 20GB
> (and it is not finished yet) for less than 1 simulated second. How can
> I reduce the size of the debug-flags (or set something more specific)?
>
> In contrast I build the HPCG benchmark with DHPCG_DEBUG flag. If you
> want, you can compare these two output files
> (hpcg20010909T014640_SE_Mode & HPCG-Benchmark_3.1_FS_Mode). As you can
> see, something goes wrong with the accuracy of calculations in FS mode
> (benchmark uses double precission). You can find the files here:
> http://kition.mhl.tuc.gr:8000/d/68d82f3533/
>
> Best regards,
> Nikos
>
> Quoting Jason Lowe-Power :
>
> > That's quite odd that it works in SE mode but not FS mode!
> >
> > I would suggest running with --debug-flags=Exec for both and then
> perform a
> > diff to see how they differ.
> >
> > Cheers,
> > Jason
> >
> > On Tue, Sep 20, 2022 at 2:45 PM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >> Dear Bobby,
> >>
> >> In QEMU I get the same (correct) results that I get in SE mode
> >> simulation. I get invalid results in FS simulation (in both
> >> riscv-fs.py and riscv-ubuntu-run.py). I cannot access real RISCV
> >> hardware at this moment, however, if you want you may execute my xhpcg
> >> binary (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the
> >> following configuration:
> >>
> >> ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1
> >>
> >> Please let me know if you have any updates!
> >>
> >> Best regards,
> >> Nikos
> >>
> >>
> >> Quoting Jason Lowe-Power :
> >>
> >> > Hi Nikos,
> >> >
> >> > I notice you said the following in your original email:
> >> >
> >> > In addition, I used the RISCV Ubuntu image
> >> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu
> ),
> >> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> >> wrong results too.
> >> >
> >> >
> >> > Is this saying you get the wrong results is QEMU? If so, the bug is in
> >> GCC
> >> > or the HPCG workload, not in gem5. If not, I would test in QEMU to
> make
> >> > sure the binary works there. Another way you could test to see if the
> >> > problem is your binary or gem5 would be to run it on real hardware. We
> >> have
> >> > access to some RISC-V hardware here at UC Davis, if you don't have
> access
> >> > to it.
> >> >
> >> > Cheers,
> >> > Jason
> >> >
> >> > On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
> >> > ntampourat...@ece.auth.gr> wrote:
> >> >
> >> >> Dear Bobby,
> >> >>
> >> >> 1) I use the original riscv-fs.py which is provided in the latest
> gem5
> >> >> release.
> >> >> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> >> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> >> >> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> >> >> After this I mount the riscv-disk-img (sudo mount -o loop
> >> >> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> >> >> changes in riscv-fs.py to boot the riscv-disk-img with executable:
> >> >>
> >> >> image = CustomDiskImageResource(
> >> >>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> >> >> )
> >> >>
> >> >> # Set the Full System workload.
> >> >> board.set_kernel_disk_workload(
> >> >> kernel=Resource("riscv-bootloader-vmlinux-5.10&qu

[gem5-users] Re: 3D NoC and Routerless NoC support in gem5

2022-09-21 Thread Jason Lowe-Power
Hi Ali,

For a 3D mesh, you'll have to create your own topology. This video should
be helpful in explaining how to do that: https://youtu.be/rZ-AYaKBK4M

For the most recent updates to the network models, you can see information
on HeteroGarnet: https://www.gem5.org/2020/05/27/heterogarnet.html

Cheers,
Jason

On Wed, Sep 21, 2022 at 12:37 AM Ali Karazmoodeh 
wrote:

> Hello,
> I am new to gem5 and I want to simulate a 3D Mesh in Heterogarnet. I was
> wondering if there is a standard 3D Mesh topology file to build upon it and
> continue my work from there, or if each researcher needs to create their 3D
> topology from the 2D counterparts.
> Moreover, in the paper "The gem5 simulator: version 20.0+", it is
> mentioned that work is in progress to include support for routerless NoCs
> in the gem5 simulator. Where can I find this work?
>
> Sincerely yours,
> Ali Karazmoodeh.
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[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
That's quite odd that it works in SE mode but not FS mode!

I would suggest running with --debug-flags=Exec for both and then perform a
diff to see how they differ.

Cheers,
Jason

On Tue, Sep 20, 2022 at 2:45 PM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> In QEMU I get the same (correct) results that I get in SE mode
> simulation. I get invalid results in FS simulation (in both
> riscv-fs.py and riscv-ubuntu-run.py). I cannot access real RISCV
> hardware at this moment, however, if you want you may execute my xhpcg
> binary (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the
> following configuration:
>
> ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1
>
> Please let me know if you have any updates!
>
> Best regards,
> Nikos
>
>
> Quoting Jason Lowe-Power :
>
> > Hi Nikos,
> >
> > I notice you said the following in your original email:
> >
> > In addition, I used the RISCV Ubuntu image
> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> wrong results too.
> >
> >
> > Is this saying you get the wrong results is QEMU? If so, the bug is in
> GCC
> > or the HPCG workload, not in gem5. If not, I would test in QEMU to make
> > sure the binary works there. Another way you could test to see if the
> > problem is your binary or gem5 would be to run it on real hardware. We
> have
> > access to some RISC-V hardware here at UC Davis, if you don't have access
> > to it.
> >
> > Cheers,
> > Jason
> >
> > On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >> Dear Bobby,
> >>
> >> 1) I use the original riscv-fs.py which is provided in the latest gem5
> >> release.
> >> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> >> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> >> After this I mount the riscv-disk-img (sudo mount -o loop
> >> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> >> changes in riscv-fs.py to boot the riscv-disk-img with executable:
> >>
> >> image = CustomDiskImageResource(
> >>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> >> )
> >>
> >> # Set the Full System workload.
> >> board.set_kernel_disk_workload(
> >> kernel=Resource("riscv-bootloader-vmlinux-5.10"),
> >> disk_image=image,
> >> )
> >>
> >> Finally, in the gem5/src/python/gem5/components/boards/riscv_board.py
> >> I change the last line to "return ["console=ttyS0",
> >> "root={root_value}", "rw"]" in order to allow the write permissions in
> >> the image.
> >>
> >>
> >> 2) The HPCG benchmark after some iterations calculates if the results
> >> are valid or not valid. In the case of FS it gives invalid results. As
> >> I see from the results, one (at least) problem is that produces
> >> different results in each HPCG execution (with the same configuration).
> >>
> >> Here is the HPCG output and riscv-fs.py
> >> (http://kition.mhl.tuc.gr:8000/d/68d82f3533/). You may reproduce the
> >> results in the video if you use the xhpcg executable
> >> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/)
> >>
> >> Please help me in order to solve it!
> >>
> >> Finally, I get invalid results in the HPL benchmark in FS mode too.
> >>
> >> Best regards,
> >> Nikos
> >>
> >>
> >> Quoting Bobby Bruce :
> >>
> >> > I'm going to need a bit more information to help:
> >> >
> >> > 1. In what way have you modified
> >> > ./configs/example/gem5_library/riscv-fs.py? Can you attach the script
> >> here?
> >> > 2. What error are you getting or in what way are the results invalid?
> >> >
> >> > -
> >> > Dr. Bobby R. Bruce
> >> > Room 3050,
> >> > Kemper Hall, UC Davis
> >> > Davis,
> >> > CA, 95616
> >> >
> >> > web: https://www.bobbybruce.net
> >> >
> >> >
> >> > On Mon, Sep 19, 2022 at 1:43 PM Νικόλαος Ταμπουρατζής <
> >> > ntampourat...@ece.auth.gr> wrote:
> >> &

[gem5-users] Re: 回复:Re: 回复:Re: Different simulation results on different computers with the same configuration

2022-09-20 Thread Jason Lowe-Power
Hello,

The following two command produce very different gem5 binaries

scons build/Garnet_standalone/gem5.opt

The above command will use the Garnet_standalone "coherence" protocol. I
use quotes around coherence because that protocol is essentially an empty
protocol with no coherence. It's meant for testing networks and nothing
else.

scons build/NULL/gem5.opt

This command will use the MI_example protocol. This is a completely
different coherence protocol than Garnet_standalone. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/build_opts/NULL
for how the protocol is defined in the default build options.

You can specify the exact protocol you want when you build gem5 by using
the scons parameter `--protocol`

Cheers,
Jason

On Tue, Sep 20, 2022 at 8:08 AM 2497597 <2497...@qq.com> wrote:

> The correct result is below:
>
> average_packet_latency = 15.510408
> average_packet_latency = 15.528615
> average_packet_latency = 15.682214
> average_packet_latency = 15.695504
> average_packet_latency = 15.769957
> average_packet_latency = 15.821728
> average_packet_latency = 15.912262
> average_packet_latency = 16.051925
> average_packet_latency = 16.167249
> average_packet_latency = 16.319634
> average_packet_latency = 16.479105
> average_packet_latency = 16.725313
> average_packet_latency = 17.055812
> average_packet_latency = 17.588959
> average_packet_latency = 18.500431
> average_packet_latency = 21.669417
> average_packet_latency = 103.241365
> average_packet_latency = 273.002675
> average_packet_latency = 430.695013
> average_packet_latency = 596.634683
> average_packet_latency = 732.220679
> average_packet_latency = 854.214438
> average_packet_latency = 969.032975
> average_packet_latency = 1087.468352
> average_packet_latency = 1207.588344
>
> 1.gem5 version is v21.2.1.0
>
> 2.build command is ”scons build/NULL/gem5.opt -j 4"
>
> 3.run command is below and the "--injection-rate" is increasing with
> step=0.02
>
> Command to Run:
> ./build/NULL/gem5.opt
> configs/example/garnet_synth_traffic.py \
> --network=garnet2.0 \
> --num-cpus=64 \
> --num-dirs=64 \
> --topology=Mesh_XY \
> --mesh-rows=8 \
> --sim-cycles=1 \
> --inj-vnet=0 \
> --injectionrate=0.02 \
> --synthetic=uniform_random
>
> I find some interesting phenomenons.
> I think I figured out where the problem might be.
> It might be the permission error and the build order.
> I built "X86","ARM","NULL" on my old computer before,so I try to restore
> it all.
> Then I find the miss folder "__pycache__" come out,I think I'm going to
> get close to the root of the problem.
> But I failed.
> I rebuild a same version gem5 on my new computer with the command"”scons
> build/Garnet_standalone/gem5.opt -j 4" under the root state.
> Then I run the same script,I get the correct output.(I can see the
> average_packet_latency is increasing with the --injectionrate)
> Although I get the desired output, I can't figure out why I get the wrong
> output.
>
> -- 原始邮件 --
> *发件人:* "The gem5 Users mailing list" ;
> *发送时间:* 2022年9月20日(星期二) 晚上7:40
> *收件人:* "gem5-users";
> *主题:* [gem5-users] Re: 回复:Re: Different simulation results on different
> computers with the same configuration
>
> Not sure to understand what you mean by “correct result".
>
> Can you please provide us with:
>
>1.
>
>gem5 version (commit SHA)
>2.
>
>build command
>3.
>
>run command
>
>
> Can you please also double-check that you are using supported versions of
> python and gcc/clang. Also check that config.ini is the same in all cases.
>
> Gabriel
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[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
Hi Nikos,

I notice you said the following in your original email:

In addition, I used the RISCV Ubuntu image
> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> I installed the gcc compiler, compile it (through qemu) and I get
> wrong results too.


Is this saying you get the wrong results is QEMU? If so, the bug is in GCC
or the HPCG workload, not in gem5. If not, I would test in QEMU to make
sure the binary works there. Another way you could test to see if the
problem is your binary or gem5 would be to run it on real hardware. We have
access to some RISC-V hardware here at UC Davis, if you don't have access
to it.

Cheers,
Jason

On Tue, Sep 20, 2022 at 12:58 AM Νικόλαος Ταμπουρατζής <
ntampourat...@ece.auth.gr> wrote:

> Dear Bobby,
>
> 1) I use the original riscv-fs.py which is provided in the latest gem5
> release.
> I run the gem5 once (./build/RISCV/gem5.fast -d ./HPCG_FS_results
> ./configs/example/gem5_library/riscv-fs.py) in order to download the
> riscv-bootloader-vmlinux-5.10 and riscv-disk-img.
> After this I mount the riscv-disk-img (sudo mount -o loop
> riscv-disk-img /mnt), put the xhpcg executable and I do the following
> changes in riscv-fs.py to boot the riscv-disk-img with executable:
>
> image = CustomDiskImageResource(
>  local_path = "/home/cossim/.cache/gem5/riscv-disk-img",
> )
>
> # Set the Full System workload.
> board.set_kernel_disk_workload(
> kernel=Resource("riscv-bootloader-vmlinux-5.10"),
> disk_image=image,
> )
>
> Finally, in the gem5/src/python/gem5/components/boards/riscv_board.py
> I change the last line to "return ["console=ttyS0",
> "root={root_value}", "rw"]" in order to allow the write permissions in
> the image.
>
>
> 2) The HPCG benchmark after some iterations calculates if the results
> are valid or not valid. In the case of FS it gives invalid results. As
> I see from the results, one (at least) problem is that produces
> different results in each HPCG execution (with the same configuration).
>
> Here is the HPCG output and riscv-fs.py
> (http://kition.mhl.tuc.gr:8000/d/68d82f3533/). You may reproduce the
> results in the video if you use the xhpcg executable
> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/)
>
> Please help me in order to solve it!
>
> Finally, I get invalid results in the HPL benchmark in FS mode too.
>
> Best regards,
> Nikos
>
>
> Quoting Bobby Bruce :
>
> > I'm going to need a bit more information to help:
> >
> > 1. In what way have you modified
> > ./configs/example/gem5_library/riscv-fs.py? Can you attach the script
> here?
> > 2. What error are you getting or in what way are the results invalid?
> >
> > -
> > Dr. Bobby R. Bruce
> > Room 3050,
> > Kemper Hall, UC Davis
> > Davis,
> > CA, 95616
> >
> > web: https://www.bobbybruce.net
> >
> >
> > On Mon, Sep 19, 2022 at 1:43 PM Νικόλαος Ταμπουρατζής <
> > ntampourat...@ece.auth.gr> wrote:
> >
> >>
> >> Dear gem5 community,
> >>
> >> I have successfully cross-compile the HPCG benchmark for RISCV (Serial
> >> version, without MPI and OpenMP). While it working properly in gem5 SE
> >> mode (./build/RISCV/gem5.fast -d ./HPCG_SE_results
> >> ./configs/example/se.py -c xhpcg --options '--nx=16 --ny=16 --nz=16
> >> --npx=1 --npy=1 --npz=1 --rt=0.1'), I get invalid results in FS
> >> simulation using "./build/RISCV/gem5.fast -d ./HPCG_FS_results
> >> ./configs/example/gem5_library/riscv-fs.py" (I mount the riscv image
> >> and put it).
> >>
> >> Can you help me please?
> >>
> >> In addition, I used the RISCV Ubuntu image
> >> (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu),
> >> I installed the gcc compiler, compile it (through qemu) and I get
> >> wrong results too.
> >>
> >> Here is the Makefile which I use, the hpcg executable for RISCV
> >> (xhpcg), and a video that shows the results
> >> (http://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/).
> >>
> >> P.S. I use the latest gem5 version.
> >>
> >> Thank you in advance! :)
> >>
> >> Best regards,
> >> Nikos
> >> ___
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> >> To unsubscribe send an email to gem5-users-le...@gem5.org
> >>
>
>
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[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
If you apply the relation chain on gerrit, it might work. See
https://gem5-review.googlesource.com/c/public/gem5/+/35836/

That relation chain has not been merged, unfortunately.

Cheers,
Jason

On Thu, Sep 8, 2022 at 1:02 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi Prof,
>
> Thanks a lot for your response. Is there any update regarding this ticket?
> https://gem5.atlassian.net/browse/GEM5-332
>
> Correct me if I'm wrong, but I think your response implies that the
> hyperthreading is implemented by maybe not tested. If so, this is confusing
> me a bit, given the link I included above.
>
> I forgot to mention that I am using x86.
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
>
>
> On Thu, Sep 8, 2022 at 7:51 AM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> In this case "Thread" means hardware context in the CPU (e.g., Intel
>> hyperthreads), not *core*.
>>
>> Have you configured your O3CPU to have 8 hardware contexts?
>>
>> I'll give a few short pointers:
>> 1. SPEC is single threaded (unless running SPEC rate), so there may not
>> be other software threads executing on the system
>> 2. Multithreaded cores are not tested at all in gem5. They may work, or
>> they may not.
>> 3. I have never seen anyone try to use more than two hardware contexts in
>> a core in gem5. I wouldn't be surprised if 8 hardware contexts have never
>> been tested.
>>
>> To debug this, I would probably start by having multiple CPU cores and
>> making sure things work as expected. If so, then I would try 2 threads per
>> core to see if it works, then go to 4 or 8.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Sep 8, 2022 at 2:55 AM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am running a multithreaded workload on the O3 CPU in Full System Mode.
>>> The workload is SPEC OMP. I am running from a checkpoint that was taken in
>>> the middle of running the benchmark. I am using the following debugging
>>> flags to monitor the system
>>> Thread,Faults,Fetch,O3CPU
>>>
>>> However, looking at the debugging file, I always see that the fetcher
>>> only fetches from tid: 0, which means the CPU does not switch to any other
>>> Thread at all. I am sure that my workload runs on 8 threads (cooperating
>>> threads).
>>>
>>> So, does this mean that gem5 does not support running multithreaded
>>> workloads? Or, am I missing something or watching the wrong debug prints?
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> ___
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>>>
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[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
Hello,

In this case "Thread" means hardware context in the CPU (e.g., Intel
hyperthreads), not *core*.

Have you configured your O3CPU to have 8 hardware contexts?

I'll give a few short pointers:
1. SPEC is single threaded (unless running SPEC rate), so there may not be
other software threads executing on the system
2. Multithreaded cores are not tested at all in gem5. They may work, or
they may not.
3. I have never seen anyone try to use more than two hardware contexts in a
core in gem5. I wouldn't be surprised if 8 hardware contexts have never
been tested.

To debug this, I would probably start by having multiple CPU cores and
making sure things work as expected. If so, then I would try 2 threads per
core to see if it works, then go to 4 or 8.

Cheers,
Jason

On Thu, Sep 8, 2022 at 2:55 AM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am running a multithreaded workload on the O3 CPU in Full System Mode.
> The workload is SPEC OMP. I am running from a checkpoint that was taken in
> the middle of running the benchmark. I am using the following debugging
> flags to monitor the system
> Thread,Faults,Fetch,O3CPU
>
> However, looking at the debugging file, I always see that the fetcher only
> fetches from tid: 0, which means the CPU does not switch to any other
> Thread at all. I am sure that my workload runs on 8 threads (cooperating
> threads).
>
> So, does this mean that gem5 does not support running multithreaded
> workloads? Or, am I missing something or watching the wrong debug prints?
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
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[gem5-users] Re: Trying to add barrier to threads example

2022-09-06 Thread Jason Lowe-Power
Hi Gautam,

There are a number of limitations of SE mode including with respect to
multithreading as I described above. You may be able to get around the
functional access issue by extending the protocol to support functional
accesses better (e.g., improving the implementation of `functionalRead` and
`functionalWrite` in the cache controller). Otherwise, you can probably use
the MI_example or MESI protocols as a good example of how to implement
DMAs. Other than DMA, things *should* work in FS mode. As always, using the
Ruby random tester is faster than waiting for linux boot to run into an
error.

Cheers,
Jason

On Sat, Sep 3, 2022 at 1:10 PM Gautam Pathak 
wrote:

> Hi Prof. Jason,
>
> Thank you for the clarification. I further wanted to ask whether there is
> any other way to do multithreaded application tests correctly in SE+ruby
> mode? If not, then we'll be forced to use FS mode which afaik does not work
> currently with MSI (our modified protocol will have to be changed again
> because FS mode requires (?) DMA support). Do you have any advice for
> things to watch out for while testing our multithreaded applications in
> Full System mode?
>
> Thanks and Regards,
> Gautam Pathak
> ------
> *From:* Jason Lowe-Power 
> *Sent:* Friday, September 2, 2022 10:51 AM
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: Trying to add barrier to threads example
>
> Hi Gautam,
>
> Functional accesses (i.e., fake/debug accesses that bypass all timing) and
> Ruby do not play well together. Fundamentally, it is hard to know what is
> the most up to date value or which value(s) you have to update when a cache
> block is in an intermediate state. With MI_example and MESI, these
> protocols probably have more support for functional reads than MSI, but
> you're also just getting lucky with those. At some point, if you're doing
> functional accesses, it's going to fail.
>
> In SE mode, to implement the fake system calls which execute *in the
> simulator* instead of via the guest kernel executing on the simulated CPU,
> we must use the fake/unrealistic/magic functional accesses. So, this is why
> SE mode + multithreading + Ruby will almost always run into a problem at
> some point. FS mode will not have this issue because it does not use
> functional accesses (almost none at all) and nothing is "faked." The
> simulated CPU executes all of the kernel system calls.
>
> Hopefully this answers your question. Let me know if I can provide more
> info :)
>
> Cheers,
> Jason
>
> On Thu, Sep 1, 2022 at 3:58 PM Gautam Pathak 
> wrote:
>
> Hi All,
>
> I'm trying to add a custom thread barrier to the array_add function by
> using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE
> mode. When I run this, I get the following error:
> build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read
> failed for address 0x15b918.
> Till now I have observed that there is an open issue which mentions that
> Ruby+multithreading+SE is not supported. The exact fault occurs in Futex
> syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I
> have tested the same for MI_Example protocol (using simple_ruby.py) and
> MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me
> wonder whether this is an MSI protocol bug. Any suggestions on how I should
> go on about this issue would be appreciated! Otherwise, is Full System mode
> the recommended option for Ruby+custom coherence protocol+multithreading
> (possibly using atomics)?
>
> Thanks and Regards,
> Gautam Pathak
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[gem5-users] Re: Trying to add barrier to threads example

2022-09-02 Thread Jason Lowe-Power
Hi Gautam,

Functional accesses (i.e., fake/debug accesses that bypass all timing) and
Ruby do not play well together. Fundamentally, it is hard to know what is
the most up to date value or which value(s) you have to update when a cache
block is in an intermediate state. With MI_example and MESI, these
protocols probably have more support for functional reads than MSI, but
you're also just getting lucky with those. At some point, if you're doing
functional accesses, it's going to fail.

In SE mode, to implement the fake system calls which execute *in the
simulator* instead of via the guest kernel executing on the simulated CPU,
we must use the fake/unrealistic/magic functional accesses. So, this is why
SE mode + multithreading + Ruby will almost always run into a problem at
some point. FS mode will not have this issue because it does not use
functional accesses (almost none at all) and nothing is "faked." The
simulated CPU executes all of the kernel system calls.

Hopefully this answers your question. Let me know if I can provide more
info :)

Cheers,
Jason

On Thu, Sep 1, 2022 at 3:58 PM Gautam Pathak 
wrote:

> Hi All,
>
> I'm trying to add a custom thread barrier to the array_add function by
> using __sync_fetch_and_add. The system I'm using is MSI using Ruby in SE
> mode. When I run this, I get the following error:
> build/X86/mem/ruby/system/RubyPort.cc:434: fatal: Ruby functional read
> failed for address 0x15b918.
> Till now I have observed that there is an open issue which mentions that
> Ruby+multithreading+SE is not supported. The exact fault occurs in Futex
> syscall. (Ref. https://gem5.atlassian.net/browse/GEM5-676). However, I
> have tested the same for MI_Example protocol (using simple_ruby.py) and
> MESI_Two_Level (using se.py) upto 30+ threads and it works. This makes me
> wonder whether this is an MSI protocol bug. Any suggestions on how I should
> go on about this issue would be appreciated! Otherwise, is Full System mode
> the recommended option for Ruby+custom coherence protocol+multithreading
> (possibly using atomics)?
>
> Thanks and Regards,
> Gautam Pathak
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[gem5-users] Re: Is there a dev branch with 2 level TLB in X86 Full System

2022-08-31 Thread Jason Lowe-Power
Hi Arun,

There's no mainline changes which implement a two level TLB in x86. This
would be a welcome contribution, though!

Cheers,
Jason

On Wed, Aug 31, 2022 at 12:14 AM Arun Kavumkal 
wrote:

> Hi All,
> I would like to know whether there is any ongoing work to implement 2
> level TLB in X86 FS. I understand that ARM has 2 level TLB implementation.
> I was wondering if there is an ongoing development activity for 2 level
> TLB in X86, I can use that for the time being
>
> Thanks
> Arun KP
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[gem5-users] Re: Linux not booting on x86 (timing cpu, single core) after pulling latest stable branch

2022-08-08 Thread Jason Lowe-Power
Hi Arun,

Can you give us some details on the error that you're experiencing?

Thanks,
Jason

On Sun, Aug 7, 2022 at 7:48 AM Arun Kavumkal 
wrote:

> Dear All,
> I was able to boot Linux v5.2.3 on x86 system (timing cpu, single core)
> and execute benchmarks using gem5art (https://github.com/darchr/gem5art),
> but after pulling latest changes in stable branch (till Commits on Jul 29,
> 2022), I am not able to boot linux using gem5art.
>
> Arun KP
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[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-28 Thread Jason Lowe-Power
Hello,

No, I would not count on all of the instructions being fully implemented.
However, every time gem5 encounters an unimplemented instruction it will
print a warning. You can use those warnings to decide if the unimplemented
instructions are important for your workload or not.

Cheers,
Jason

On Wed, Jul 27, 2022 at 5:02 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi,
>
> Thanks a lot for your reply.
>
> I got the CPU info by printing the /proc/cpuinfo file on the image while
> on full system mode on gem5. Can we safely assume that the following flags
> are fully implemented and functional? For example, as per this page from
> gem5 documentation
> <https://www.gem5.org/documentation/general_docs/architecture_support/>,
> only SSE is implemented and x87 is partially implemented, however, the
> following flags say something a bit different that SSE2 is supported.
>
> So, again, my question is: Can I safely rely on these flags being fully
> implemented?
>
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat
>> pse36 clflush acpi mmx fxsr sse sse2 ss tm ia64 pbe syscall nx mmxext
>> fxsr_opt rdtscp lm 3dnowext 3dnow nopl cpuid pni monitor ssse3 lahf_lm cpb
>> proc_feedback pti clflushopt clwb overflow_recov
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
>
>
> On Tue, Jul 26, 2022 at 7:53 AM Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> We support some of those instructions, but not all of them. I suggest
>> running your workloads and watching out for unimplemented instruction
>> warnings.
>>
>> Cheers,
>> Jason
>>
>> On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am trying to run SPEC OMP 2012 in Full System mode on gem5. When I try
>>> to run it, I get the following error:
>>>
>>> Please verify that both the operating system and the processor support
>>>> Intel(R) X87, CMOV, MMX, FXSAVE, SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2 and
>>>> POPCNT instructions.
>>>>
>>>
>>> The image has Ubuntu 18 and the kernel is vmlinux-5.4.49 downloaded
>>> from gem5 website. CPU is AtomicCPU and all the implementation is for x86.
>>>
>>> My question is: does gem5 support the above Intel extensions  for SIMD
>>> and Vectorization? I tried to look into the gem5 resources, but I couldn't
>>> find something clear on this.
>>>
>>> Thanks!
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> --
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>> MSc. Student -- Graduate RA/TA
>>> School of Computing Sciences
>>> Simon Fraser University, Canada
>>> ___
>>> gem5-users mailing list -- gem5-users@gem5.org
>>> To unsubscribe send an email to gem5-users-le...@gem5.org
>>>
>> ___
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>>
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[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-26 Thread Jason Lowe-Power
Hello,

We support some of those instructions, but not all of them. I suggest
running your workloads and watching out for unimplemented instruction
warnings.

Cheers,
Jason

On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am trying to run SPEC OMP 2012 in Full System mode on gem5. When I try
> to run it, I get the following error:
>
> Please verify that both the operating system and the processor support
>> Intel(R) X87, CMOV, MMX, FXSAVE, SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2 and
>> POPCNT instructions.
>>
>
> The image has Ubuntu 18 and the kernel is vmlinux-5.4.49 downloaded from
> gem5 website. CPU is AtomicCPU and all the implementation is for x86.
>
> My question is: does gem5 support the above Intel extensions  for SIMD and
> Vectorization? I tried to look into the gem5 resources, but I couldn't find
> something clear on this.
>
> Thanks!
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
> --
>
> --
>
> *Best,Abdelrahman Hussein*
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: Running gem5 with DRAMsim3

2022-07-25 Thread Jason Lowe-Power
Hello,

We can only support the official gem5 repository found at
https://gem5.googlesource.com/. You can find the information on how to use
DRAMSim3 in the README
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/ext/dramsim3/README

Cheers,
Jason

On Sat, Jul 23, 2022 at 9:49 AM Thomas Copper 
wrote:

> Hi, Mahyar, what if I am using gem5 version in this url:
> https://github.com/umd-memsys/gem5 ?
> How can I integrate dramsim3 and gem5 together?
> ___
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>
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[gem5-users] Re: turn off gem5 mailing list

2022-07-07 Thread Jason Lowe-Power
Hello,

At the end of all messages it says "To unsubscribe send an email to
gem5-users-le...@gem5.org"

You can also manage your subscription at
https://harmonylists.io/list/gem5-users.gem5.org by creating an account and
logging in.

Cheers,
Jason

On Thu, Jul 7, 2022 at 7:14 AM Zhipeng Cao  wrote:

>
> How can I turn off gem5 mailing list?
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
Hi Zehan,

I wouldn't say it converts the timing request to atomic. Instead, I would
say that for the *functional access* (sorry for the overloaded term here...
I mean functional as in the place it does the "execution" part of the
model) it uses the same C++ function for both timing and atomic. The timing
should be handled in the delay when the sendTimingReq or sendTimingResp
events are scheduled.

Cheers,
Jason

On Wed, Jul 6, 2022 at 8:21 AM Zehan Gao  wrote:

> Thanks for your advice. My guess is that it's the ports connected to the
> atomic-only port converts a timing request to atomic, and calls the
> recvAtomic function. In this case it's the XBar. I will try to measure how
> it's delayed.
>
> ------
> *From:* Jason Lowe-Power 
> *Sent:* Wednesday, July 6, 2022, 11:09 a.m.
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: What happens when a atomic only port is
> accessed in Timing simulation?
>
> Hi Zehan,
>
> Atomic memory accesses should not be used during the same simulation loop
> as timing accesses. I.e., you should not call "sendAtomic" on a port during
> the same simulation loop that you call "sendTiming". If there isn't a panic
> in that case, there probably should be.
>
> If you want to get a value out of memory in 0 time (e.g., for debugging or
> to model a "perfect" hardware component) you can use *functional* accesses
> during the timing simulation. You can also exit the simulation loop and
> switch between timing and atomic modes.
>
> Cheers,
> Jason
>
> On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:
>
>> Hi All,
>>
>>   I am building a simulated system with a control registers
>> port that only implemented recvAtomic function. The control port is
>> connected to the IOBridge, and the system is running in timing mode. There
>> is no problem to access the registers from CPU, but I wonder what the
>> system does with the delay? I believe the atomic port would be treated as a
>> timing port that has no delays. But is the delay of IOBridge and other
>> system buses counted?
>>
>>
>>
>> Thanks,
>>
>> Zehan
>>
>>
>> ___
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>>
>
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[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
Hi Zehan,

Atomic memory accesses should not be used during the same simulation loop
as timing accesses. I.e., you should not call "sendAtomic" on a port during
the same simulation loop that you call "sendTiming". If there isn't a panic
in that case, there probably should be.

If you want to get a value out of memory in 0 time (e.g., for debugging or
to model a "perfect" hardware component) you can use *functional* accesses
during the timing simulation. You can also exit the simulation loop and
switch between timing and atomic modes.

Cheers,
Jason

On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao  wrote:

> Hi All,
>
>   I am building a simulated system with a control registers
> port that only implemented recvAtomic function. The control port is
> connected to the IOBridge, and the system is running in timing mode. There
> is no problem to access the registers from CPU, but I wonder what the
> system does with the delay? I believe the atomic port would be treated as a
> timing port that has no delays. But is the delay of IOBridge and other
> system buses counted?
>
>
>
> Thanks,
>
> Zehan
>
>
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>
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[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-27 Thread Jason Lowe-Power
Hi Syam,

In a much older version of gem5, maybe. It's been at least 2+ years since
we required the PID to be specified in SE mode.

Cheers,
Jason

On Mon, Jun 27, 2022 at 5:37 AM Syam Sankar  wrote:

> Dear Dr. Jason
>
> Thank you for your kind reply.
> I think this worked fine with the older version of gem5, right?
>
> Regards
> Syam
>
> On Fri, 24 Jun 2022, 12:43 am Jason Lowe-Power, 
> wrote:
>
>> Hi Syam,
>>
>> The error is that in *SE mode* you have to manually specify the PID for
>> each process when you are creating the processes in Python. However, I
>> think you're going to run into many problems trying to simulate such a
>> large system/workload in SE mode. For instance, I seriously doubt 3GB is
>> enough RAM for 64 copies of namd.
>>
>> We are working towards deprecating se/fs.py because they do not support
>> the flexibility required for different kinds of simulations. I would
>> suggest looking into extending the standard library with a new board to
>> model your system. Right now, we don't have any prebuilt boards at this
>> scale, but adding one is relatively straightforward. You can find
>> documentation on the standard library on the website, in our recent ISCA
>> tutorial (see our youtube channel), and we'll have more in a couple of
>> weeks.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Jun 23, 2022 at 9:01 AM Syam Sankar 
>> wrote:
>>
>>> Hi all
>>>
>>>
>>> I downloaded a new version of gem5 repo*(gem5 version 22.0.0.1)*
>>> I could build it with the following command:
>>>
>>> *python3 `which scons` build/X86/gem5.fast RUBY=true
>>> PROTOCOL=MESI_Two_Level  -j 8*
>>>
>>> I was trying to execute a *CPU2017 Benchmark* program on an 8X8 Core
>>> system with the command as follows:
>>>
>>>
>>> build/X86/gem5.fast configs/example/se.py  --num-cpus=64 --num-dirs=64
>>>  --sys-clock=2GHz --topology=Mesh_XY --mesh-rows=8 --ruby --num-l2caches=64
>>> --network=garnet   --caches --mem-type=DDR3_1600_8x8 --mem-size=3GB
>>>  --routing-algorithm=1 -F 1000 -W 1000 -I 5000
>>> --bench=namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd
>>>
>>>
>>>  But, the execution is ended with an error:
>>>
>>>
>>> *build/X86/sim/process.cc:141: fatal: fatal condition !ret_pair.second
>>> occurred: _pid 100 is already used*
>>>
>>> ...
>>> ..
>>> ..
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (64 Mbytes)
>>> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
>>> Mbytes) does not match the ad

[gem5-users] Re: O3CPU "panic: Is stalled should have been cleared by stalling load!" when simulating for >5Billion insts, SE and FS, AARCH64

2022-06-23 Thread Jason Lowe-Power
Hi Norbert,

This is going to be a tough bug to track down! I would suggest enabling the
Exec debug flag (and maybe some others for the O3CPU) and using
--debug-start and starting the debug dumping a billion ticks or so before
the error happens. Hopefully, you can then trace back what is causing the
error. My bet is that there is some specific sequence of instructions which
is causing this.

This isn't an error I've seen before, so it's going to take some digging :).

Cheers,
Jason

On Thu, Jun 23, 2022 at 5:52 AM Norbertas Kremeris <
norbertas.kreme...@huawei.com> wrote:

> Hello all,
>
>
>
> I’m looking for some help regarding failing simulations. My host system is
> running Ubuntu 20.04 x86, and the gem5 source version is v21.2.1.1
>
>
>
> I have started running long simulations, and ran into a problem with the
> O3CPU model. I seem to have no issues running up to around 5 Billion
> instructions, some binaries up to 10 Billion, but not a single binary up to
> 20Billion, because the O3CPU model terminates the gem5 simulations with the
> following error:
>
>
>
> build/ARM/cpu/o3/lsq_unit.cc:1018: panic: Is stalled should have been
> cleared by stalling load!
>
>
>
> This happens both in full system and in syscall emulation. I am using
> aarch64. This does not happen with atomic or timing cpu variants.
>
>
>
> I am trying to run a select number of spec2017 benchmarks, namely
>
> 507.cactuBSSN_r, 607.cactuBSSN_s, 638.imagick_s, 500.perlbench_r_param3,
> 502.gcc_r_param4, 641.leela_s
>
>
>
> Out of all of the above benchmarks, all successfully run up to 5B, image
> magic is the only one that runs up to 10B, and none of them run up to 20B
> instructions, and this is the same case for both FS and SE simulations.
>
>
>
> The O3 model code in question is in src/cpu/o3/lsq_unit.cc, but I don’t
> know enough to try and debug this issue:
>
>
>
> 1014 // I don't think this can happen.  It should have been cleared
>
> 1015 // by the stalling load.
>
> 1016 if (isStalled() &&
>
> 1017 storeQueue.back().instruction()->seqNum ==
> stallingStoreIsn) {
>
> 1018 panic("Is stalled should have been cleared by stalling
> load!\n");
>
> 1019 stalled = false;
>
> 1020 stallingStoreIsn = 0;
>
> 1021 }
>
>
>
> Below are the details of some example simulation runs that fail, alongside
> the full stderr output.
>
>
>
> Aarch64 Full System (restoring from checkpoint made with atomic cpu):
>
> Config: configs/example/fs.py
>
> System args:
>
>--mem-size="8000MB" \
>
> --cpu-type="O3CPU" \
>
> --restore-with-cpu="O3CPU" \
>
> --caches \
>
> --l2cache \
>
> -I="100" \
>
>
>
> Error:
>
> build/ARM/cpu/o3/lsq_unit.cc:1018: panic: Is stalled should have been
> cleared by stalling load!
>
> Memory Usage: 8979848 KBytes
>
> Program aborted at tick 5929446216500
>
> --- BEGIN LIBC BACKTRACE ---
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1a94570)[0x55a0cd625570]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1aa8f4e)[0x55a0cd639f4e]
>
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x143c0)[0x7f70b6d913c0]
>
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7f70b5f3703b]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7f70b5f16859]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x576a35)[0x55a0cc107a35]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb2c153)[0x55a0cc6bd153]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0dd36)[0x55a0cc69ed36]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0eaa3)[0x55a0cc69faa3]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb0ffbe)[0x55a0cc6a0fbe]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xaedc7f)[0x55a0cc67ec7f]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1a9ca68)[0x55a0cd62da68]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1abf564)[0x55a0cd650564]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0x1ac022e)[0x55a0cd65122e]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xb92c22)[0x55a0cc723c22]
>
>
> /work/a00558011/gem5-internal/build/ARM/gem5.fast(+0xa6a1cd)[0x55a0cc5fb1cd]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8738)[0x7f70b7048738]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7f70b6e1df48]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f70b6f6ae3b]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7f70b7048114]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f70b6e14d6d]
>
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f70b6e1cef6]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x8006b)[0x7f70b6e2006b]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f70b6e14d6d]
>
>
> 

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-23 Thread Jason Lowe-Power
Hi Syam,

The error is that in *SE mode* you have to manually specify the PID for
each process when you are creating the processes in Python. However, I
think you're going to run into many problems trying to simulate such a
large system/workload in SE mode. For instance, I seriously doubt 3GB is
enough RAM for 64 copies of namd.

We are working towards deprecating se/fs.py because they do not support the
flexibility required for different kinds of simulations. I would suggest
looking into extending the standard library with a new board to model your
system. Right now, we don't have any prebuilt boards at this scale, but
adding one is relatively straightforward. You can find documentation on the
standard library on the website, in our recent ISCA tutorial (see our
youtube channel), and we'll have more in a couple of weeks.

Cheers,
Jason

On Thu, Jun 23, 2022 at 9:01 AM Syam Sankar  wrote:

> Hi all
>
>
> I downloaded a new version of gem5 repo*(gem5 version 22.0.0.1)*
> I could build it with the following command:
>
> *python3 `which scons` build/X86/gem5.fast RUBY=true
> PROTOCOL=MESI_Two_Level  -j 8*
>
> I was trying to execute a *CPU2017 Benchmark* program on an 8X8 Core
> system with the command as follows:
>
>
> build/X86/gem5.fast configs/example/se.py  --num-cpus=64 --num-dirs=64
>  --sys-clock=2GHz --topology=Mesh_XY --mesh-rows=8 --ruby --num-l2caches=64
> --network=garnet   --caches --mem-type=DDR3_1600_8x8 --mem-size=3GB
>  --routing-algorithm=1 -F 1000 -W 1000 -I 5000
> --bench=namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd-namd
>
>
>  But, the execution is ended with an error:
>
>
> *build/X86/sim/process.cc:141: fatal: fatal condition !ret_pair.second
> occurred: _pid 100 is already used*
>
> ...
> ..
> ..
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (64 Mbytes)
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned 

[gem5-users] Re: Gem5 segfaults in build/X86/cpu/o3/fetch.cc

2022-06-13 Thread Jason Lowe-Power
Hi Gagan,

The problem is that the CPU doesn't have an ISA object as a child. Most
likely, the function `createThreads()` wasn't called on the CPU instance.
You need to set all of this up *in the python configuration*, not in the
C++ models.

Solving this problem is difficult if you're using the (soon to be)
deprecated fs.py script. This script tries to do everything for everyone
and ends up doing nothing well. I suggest looking into the new gem5
standard library and working to create a board which suits your needs. See
https://www.gem5.org/documentation/gem5-stdlib/overview

Cheers,
Jason

On Sun, Jun 12, 2022 at 11:11 PM Gagan Panwar  wrote:

> Hi everyone,
>
> I'm trying to run the latest version of Gem5 under X86 and it segfaults at
> the following line:
>
> build/X86/cpu/o3/fetch.cc:139
> > decoder[tid] = params.decoder[tid];
>
> gdb says params.decoder is a "vector of length 0". Looks like it has not
> been initialized.
>
> Any idea how to correctly initialize this?
>
> Here is my command line:
>
> ./build/X86/gem5.opt -r -d sim_output/stride/benchmark
> configs/example/fs.py --mem-size=16GB -n 4 -r 1
> --disk-image=/hdd0/newCPTs/ubuntu-server-16.04.6.img --checkpoint-dir=
> /hdd0/newCPTs/bench_1 --cpu-type=DerivO3CPU --rel-max-tick=20
> --l2-hwp-type=StridePrefetcher --caches --l2cache --kernel=vmlinux-5.4.49
>
> I have also tried assigning decoder[tid] to a new TheISA::Decoder() object
> in fetch.cc like it used to be in older versions but this leads to build
> issues.
>
> To reiterate, I have not modified a single line of code. I was able to
> take checkpoints under KVM mode successfully, however.
>
> Thank you,
> Gagan
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[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason,

To be honest, the mailman server isn't great at providing search/archiving.
I would search on mail-archive (link in previous email below) and/or use
google :).

Cheers,
Jason

On Mon, Jun 6, 2022 at 4:48 PM  wrote:

> Hi Jason,
>
>
> Thank you for your reply, I am using the “Search this list” box on the
> harmonylists.io website that says “EMPATHY” at the top left:
> https://harmonylists.io/empathy/list/gem5-users.gem5.org
>
>
> Is this the correct website to search? I allowed me to post a new thread
> question from here, but when I try to search it, it gives me the error
> described earlier. I had trouble finding where to look after the change to
> the new website, so I’m not sure if I’m using the correct one or not.
>
>
> Thank you for your time!
>
>
> Respectfully,
>
>
> Jason Z.
>
>
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[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason,

I'm not sure where you were trying to search. However, mail archive (
https://www.mail-archive.com/gem5-users@gem5.org/) is usually pretty
reliable. If that's not working for you, you may be able to reach out to
their support.

Cheers,
Jason

On Mon, Jun 6, 2022 at 4:13 PM  wrote:

> Hi everyone,
>
>
> I was trying to search the gem5-users discussion forum for a question I
> had to see if it was already addressed, but it keeps giving me an error
> with “No alive nodes found in your cluster” and says
> “NoNodesAvailableException”, so is this an issue with the discussion forum?
>
>
> Thank you for your time!
>
>
> Respectfully,
>
>
> Jason Z.
>
>
>
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>
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[gem5-users] Re: mail sent to mailing list not visible in gem5-users Mail archive

2022-05-31 Thread Jason Lowe-Power
Hi Javed,

I received that message. No idea why it doesn't show up on mail archive..

Cheers,
Jason

On Tue, May 31, 2022 at 3:33 AM Javed Osmany 
wrote:

> Hello
>
>
>
> I sent an email the gem5-users mailing list on the 27th May 2022, titled
> “CHI compilation error when trying to add L3$ between L2$ and LLC”, but I
> don’t see that email listed in the gem5-users Mail archive (
> https://www.mail-archive.com/gem5-users@gem5.org/index.html).
>
>
>
> Am I posting to the wrong email or has it just got lost?
>
>
>
> Tks
>
> JO
>
>
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>
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[gem5-users] Re: How to make _addr version of m5 ops work on x86+syscall emulation?

2022-05-12 Thread Jason Lowe-Power
Hello,

In the first case, since you're using SE mode, gem5 is trying to use
/dev/mem *on your host*, not on the guest. The addr interface for the m5
ops is really meant for FS mode, not SE mode.

In the second case, this is probably because KVM + SE mode is rarely, if
ever, tested. I'm not surprised there's a bug, though you could try the
most recent release of gem5, 21.2.

Cheers,
Jason

On Thu, May 12, 2022 at 7:26 AM  wrote:

> Hi all,
>
> I'm trying to run *_addr* *m5ops*. I need the _addr version because I
> want to implement a pseudo instruction that works in all gem5 cpu types,
> including KVM, which only supports _addr pseudo instructions.
>
> If I use this code (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2/src/simple/m5_exit_addr.c
> )
>
> as example:
>
> #include 
> #include 
> #include 
> int main(void) {
> #if defined(__aarch64__)
> m5op_addr = 0x1001;
> #endif
> map_m5_mem();
> m5_exit_addr(0);
> }
>
> I built m5ops following
> https://www.gem5.org/documentation/general_docs/m5ops/
>
> I compile the test application with:
>
> gcc test.c -o test -L ~/Projects/gem5/util/m5/build/x86/out -lm5 -I
> ~/Projects/gem5/include -I ~/Projects/gem5/util/m5/src -static
>
> If I run with AtomicSimpleCPU I get
>
> ./build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/pedro-test/test --cpu-type AtomicSimpleCPU
>
>  REAL SIMULATION 
> build/X86/sim/simulate.cc:107: info: Entering event queue @ 0. Starting
> simulation...
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/sim/syscall_emul.cc:73: warn: ignoring syscall mprotect(...)
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> Can't open /dev/mem: Permission denied
> Exiting @ tick 11031000 because exiting with last active thread context
> Simulated exit code not 0! Exit code is 1
>
> If I run with KvmCPU
>
> ./build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/pedro-test/test --cpu-type X86KvmCPU
>
> [...]
>
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0x491) unsupported
> by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0xc0010015)
> unsupported by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:1556: warn: kvm-x86: MSR (0x4b564d05)
> unsupported by gem5. Skipping.
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/cpu/kvm/x86_cpu.cc:450: warn: Illegal SS type: 1
> build/X86/cpu/kvm/x86_cpu.cc:491: warn: ss: S flag not set
> build/X86/cpu/kvm/x86_cpu.cc:517: warn: ss: P flag not set
> build/X86/sim/syscall_emul.cc:73: warn: ignoring syscall mprotect(...)
> build/X86/arch/x86/linux/se_workload.cc:162: panic: Page fault at addr 0
> Interrupt handler stack:
> ss: 0x1b
> rsp: 0x7fffed18
> rflags: 0x10006
> cs: 0x23
> rip: 0x45ca46
> err_code: 0x4
> Memory Usage: 636056 KBytes
> Program aborted at tick 441533000
> --- BEGIN LIBC BACKTRACE ---
> ./build/X86/gem5.opt(+0x883420)[0x560e0d238420]
> ./build/X86/gem5.opt(+0x8a4ade)[0x560e0d259ade]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x143c0)[0x7f7c671cb3c0]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7f7c6637103b]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7f7c66350859]
> ./build/X86/gem5.opt(+0x30b5e5)[0x560e0ccc05e5]
> ./build/X86/gem5.opt(+0xd6109c)[0x560e0d71609c]
> ./build/X86/gem5.opt(+0xd611db)[0x560e0d7161db]
> ./build/X86/gem5.opt(+0x913645)[0x560e0d2c8645]
> ./build/X86/gem5.opt(+0x9827ee)[0x560e0d3377ee]
> ./build/X86/gem5.opt(+0x983a1a)[0x560e0d338a1a]
> ./build/X86/gem5.opt(+0x9811c1)[0x560e0d3361c1]
> ./build/X86/gem5.opt(+0x552ba6)[0x560e0cf07ba6]
> ./build/X86/gem5.opt(+0x5530ae)[0x560e0cf080ae]
> ./build/X86/gem5.opt(+0x551b91)[0x560e0cf06b91]
> ./build/X86/gem5.opt(+0x892796)[0x560e0d247796]
> ./build/X86/gem5.opt(+0x8c14f4)[0x560e0d2764f4]
> ./build/X86/gem5.opt(+0x8c1d42)[0x560e0d276d42]
> ./build/X86/gem5.opt(+0xe1ec92)[0x560e0d7d3c92]
> ./build/X86/gem5.opt(+0x5bfef1)[0x560e0cf74ef1]
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8738)[0x7f7c67482738]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7f7c67257f48]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f7c673a4e3b]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7f7c67482114]
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f7c6724ed6d]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f7c67256ef6]
> 

[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
Hi Sindhuja,

I'm not sure exactly what you're looking for when you say "base and
offset." I believe you can query the base page size from the ISA (I forget
the exact function). With that you can divide and use modulo to compute the
VPN/PPN and the offset. You can also look at the TLB code to see how it
computes these things.

Cheers,
Jason

On Mon, May 9, 2022 at 2:54 PM Sindhuja Gopalakrishnan Elango <
sindhuja.gopalakrishnanela...@synopsys.com> wrote:

> Hi Jason,
>
> Thanks for the reply.
>
> I had managed to get both physical address and virtual address of the
> memory address through the request
>
> object like this.
>
> req->getPaddr();
>
> req->getVaddr();
>
> But I would like to extract the base and offset component of the virtual
> address as separate entities. Is that also possible?
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
> *From:* Jason Lowe-Power 
> *Sent:* Monday, May 9, 2022 1:34 PM
> *To:* The gem5 Users mailing list 
> *Subject:* [gem5-users] Re: virtual address -> base + offset
>
>
>
> Hi Sindhuja,
>
>
>
> The WholeTranslationState object should have all of the virtual and
> physical address information. In fact, the Request object (a member of the
> Packet) should also have both virtual and physical addresses.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango <
> sindhuja.gopalakrishnanela...@synopsys.com> wrote:
>
> Hi,
>
> Is it possible to get the base and offset components of the virtual memory
> address in the CPU model?
>
> Appreciate your comments.
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
>
>
>
>
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>
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[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
Hi Sindhuja,

The WholeTranslationState object should have all of the virtual and
physical address information. In fact, the Request object (a member of the
Packet) should also have both virtual and physical addresses.

Cheers,
Jason

On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango <
sindhuja.gopalakrishnanela...@synopsys.com> wrote:

> Hi,
>
> Is it possible to get the base and offset components of the virtual memory
> address in the CPU model?
>
> Appreciate your comments.
>
>
>
> Thanks,
>
> Sindhuja
>
>
>
>
>
>
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[gem5-users] Re: fatal: Syscall 278 out of range (ARM) - can i skip/supress syscall unimplemeted errors

2022-05-09 Thread Jason Lowe-Power
Hi Tom,

My guess is that you're using a newer version of GLIBC which calles
different syscalls than the versions of GLIBC that have been tested with
gem5. I believe 278 is mq_notify. You can try to update the syscall
implementation to ignore the syscall and see if the application still
works. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/arm/linux/se_workload.cc#404

Another possibility is that you're using a 32-bit emulated process with a
64-bit binary, or something has gone wrong with whether it's detected as
Arm32 or Arm64. In the 64-bit version, 278 is getRandom, which is
implemented. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/arm/linux/se_workload.cc#762

Hope this helps!

Cheers,
Jason

On Fri, May 6, 2022 at 6:33 PM  wrote:

> Hi All,
>
> I am trying to run dhrystone benchmark on ARM and i get the following:
>
> ./build/ARM/gem5.opt --debug-flags=Exec
> --debug-file=dhrystone_10k_a77_trace ./configs/example/arm/starter_se.py
> --cpu minor --cpu-freq 3.0GHz --mem-type DDR4_2400_8x8
> ./tests/dhrystone_10k
>
> gem5 Simulator System. http://gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.2.1.0
>
> gem5 compiled Apr 27 2022 18:13:35
>
> gem5 started May 7 2022 01:55:59
>
> gem5 executing on eden, pid 4723
>
> command line: ./build/ARM/gem5.opt --debug-flags=Exec
> --debug-file=dhrystone_10k_a77_trace ./configs/example/arm/starter_se.py
> --cpu minor --cpu-freq 3.0GHz --mem-type DDR4_2400_8x8 ./tests/dhrystone_10k
>
> info: 1. command and arguments: ['./tests/dhrystone_10k']
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (16384
> Mbytes) does not match the address range assigned (1024 Mbytes)
>
> build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (16384
> Mbytes) does not match the address range assigned (1024 Mbytes)
>
> build/ARM/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
>
> build/ARM/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
> build/ARM/sim/simulate.cc:194: info: Entering event queue @ 0. Starting
> simulation...
>
> build/ARM/sim/syscall_emul.cc:74: warn: ignoring syscall
> set_robust_list(...)
>
> build/ARM/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/ARM/sim/syscall_emul.hh:1014: warn: readlink() called on
> '/proc/self/exe' may yield unexpected results in various settings.
>
> Returning '/home/tom/Documents/gem5/tests/dhrystone_10k'
>
> build/ARM/sim/syscall_desc.hh:209: fatal: Syscall 278 out of range
>
> Memory Usage: 2237648 KBytes
>
>
> This is my new install on a new machine. In my older machine, i had run
> the dhrystone for loop count of 1 million without any error. The new
> install uses the latest stable patch.
>
> Any help is appreciated.
>
> Regards,
>
> Tom
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[gem5-users] Re: Adding DmaDevice leads to TypeError: No constructor defined

2022-04-28 Thread Jason Lowe-Power
Hello,

The `DMADevice` is also abstract. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/dev/Device.py#82

Maybe what you're trying to do would be best accomplished by adding a new
SimObject which inherits from DMADevice.

Cheers,
Jason

On Wed, Apr 27, 2022 at 9:45 AM  wrote:

> Jason,
>
>
>
> Thanks for again for the fix related to PioDevice & your guidance to use
> DmaDevice
>
>
>
> DmaDevice also provides same “No Constructor TypeError” which checking the
> dma_device.cc – the constructor is empty
>
>
>
>
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec (filecode, scope)
>   File "/home/raghu/gem5/configs/learning_gem5/part1/test.py", line 187,
> in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
> for obj in root.descendants(): obj.createCCObject()
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_DmaDevice.DmaDeviceParams: No constructor defined!
>
>
>
> *Dma_device.cc*
>
> DmaDevice::DmaDevice(const Params )
>
>  : PioDevice(p), dmaPort(this, sys, p.sid, p.ssid)
>
> { }
>
>
>
> *From:* Jason Lowe-Power via gem5-users 
> *Sent:* Friday, April 22, 2022 11:16 AM
> *To:* gem5 users mailing list 
> *Cc:* rshank...@austin.rr.com; Jason Lowe-Power 
> *Subject:* [gem5-users] Re: Adding PioDevice leads to TypeError: No
> constructor defined
>
>
>
> I just pushed a change that will make this error message better.
>
>
>
> "fatal: Cannot instantiate an abstract SimObject (system.dev)" is what
> the error now says :).
>
>
>
> See https://gem5-review.googlesource.com/c/public/gem5/+/59049
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power 
> wrote:
>
> Hello,
>
>
>
> I believe the problem is that gem5 tries to do too much automatically for
> you! gem5 automatically creates a lot of the constructor/destructor codes.
> Given all of this hidden/automatic code generation, it's difficult to know
> exactly what's going wrong (for both you and for us).
>
>
>
> That said, I think the problem is that `PioDevice` is an abstract
> SimObject, not a concrete SimObject. This may work if you instead use the
> `DmaDevice`.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
> gem5-users@gem5.org> wrote:
>
> By adding a PioDevice() to my version of two_level.py configuration
> script, I get this error
>
>
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
> And checking io_device.cc the constructor looks empty
>
>
>
> Any help please? Thanks
>
>
>
> *Details:*
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec(filecode, scope)
>
>
>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
> 187, in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
>
>
>
>
> *Io_device.cc*
>
> include "dev/io_device.hh"
>
> #include "base/trace.hh"
> #include "debug/AddrRanges.hh"
> #include "sim/system.hh"
>
> namespace gem5
> {
>
> PioDevice::PioDevice(const Params )
> : ClockedObject(p), sys(p.system), pioPort(this)
> {}
>
> PioDevice::~PioDevice()
> {
> }
>
>
>
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[gem5-users] Test email please ignore

2022-04-26 Thread Jason Lowe-Power
Sorry for the spam.

We're working to fix the issues that some people have been having with our
mailing list. I hope this will be the last test email for a while!

Cheers,
Jason
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[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

2022-04-23 Thread Jason Lowe-Power via gem5-users
Majid,

These are all great suggestions! Do you have a configuration file that you
would be willing to share? It would be a huge benefit to the community if
we had some better default configurations in the "examples" for gem5
configuration files.

We're also trying to use the new standard library for these kinds of "good"
configurations. We can work with you to create a "prebuilt board" with all
of these parameters and even run nightly/weekly tests to make sure there
are no performance regressions.

Thanks!
Jason

On Fri, Apr 22, 2022 at 7:52 PM Majid Jalili  wrote:

> I think it is hard to get to a real machine level in terms of BW. But By
> looking at your stats, I found the lsqFullEvents is high.
> You can go after the CPU to make it more aggressive, increasing Load/Store
> queue size, and ROB depth are the minimal changes you can make. I
> usually do at least ROB sizes of 256 or 320. With that, you may set the LSQ
> size to at least 1/4  of ROB size.
> For MSHRs, your numbers are good now, 10 is too little even in intel
> machines, I found recently they increased that to 16-20.
> The other thing you can try to st is the cache latencies, make sure that
> they are reasonable.
> For prefetcher, you can use IMPPrefetcher in addition to DCPT, it has a
> pretty aggressive stream prefetcher inside.
> Also, DRAM memory mapping is important, I do not remember what is the
> default for the the mem type you are using
>
> Majid
>
>
>
> On Sat, Apr 16, 2022 at 2:12 AM 王子聪  wrote:
>
>> Hi Majid,
>>
>> Thanks for your suggestion! I check the default number of MSHRs (in
>> configs/common/Caches.py), and found the default #MSHR of L1/L2 are 4 and
>> 20 respectively.
>>
>> According to the PACT’18 paper "Cimple: Instruction and Memory Level
>> Parallelism: A DSL for Uncovering ILP and MLP”,  it says that "Modern
>> processors typically have 6–10 L1 cache MSHRs”, and "Intel’s Haswell
>> microarchitecture uses 10 L1 MSHRs (Line Fill Buffers) for
>> handling outstanding L1 misses”. So I change to L1 #MSHRs to 16 and L2
>> #MSHRs to 32 (which I think it’s enough to handling outstanding misses),
>> and then change the L1/L2 prefetcher type to DCPT. Then I got the STREAM
>> output as shown in below:
>>
>> ./build/X86/gem5.opt configs/example/se.py --cpu-type=O3CPU --caches
>> --l1d_size=256kB --l1i_size=256kB
>> --param="system.cpu[0].dcache.mshrs=16;system.cpu[0].icache.mshrs=16;system.l2.mshrs=32"
>> --l2cache --l2_size=8MB --l1i-hwp-type=DCPTPrefetcher
>> --l1d-hwp-type=DCPTPrefetcher --l2-hwp-type=DCPTPrefetcher
>> --mem-type=DDR3_1600_8x8 -c ../stream/stream
>> -
>> FunctionBest Rate MB/s  Avg time Min time Max time
>> Copy:3479.8 0.004598 0.004598 0.004598
>> Scale:   3554.0 0.004502 0.004502 0.004502
>> Add: 4595.0 0.005223 0.005223 0.005223
>> Triad:   4705.9 0.005100 0.005100 0.005100
>> -
>>
>> The busutil of DRAM also improved:
>> -
>> system.mem_ctrls.dram.bytesRead  239947840  # Total bytes read
>> (Byte)
>> system.mem_ctrls.dram.bytesWritten   121160640  # Total bytes written
>> (Byte)
>> system.mem_ctrls.dram.avgRdBW  1611.266685  # Average DRAM read
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.avgWrBW   813.602251  # Average DRAM write
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.peakBW  12800.00  # Theoretical peak
>> bandwidth in MiByte/s ((Byte/Second))
>> system.mem_ctrls.dram.busUtil18.94  # Data bus
>> utilization in percentage (Ratio)
>> system.mem_ctrls.dram.busUtilRead12.59  # Data bus
>> utilization in percentage for reads (Ratio)
>> system.mem_ctrls.dram.busUtilWrite6.36  # Data bus
>> utilization in percentage for writes (Ratio)
>> system.mem_ctrls.dram.pageHitRate89.16  # Row buffer hit
>> rate, read and write combined (Ratio)
>> -
>>
>> It’s indeed improving the achieved bandwidth, but still a little far away
>> from the peak bandwidth of DDR3_1600 (12800 MiB/s). stats.txt is uploaded
>> for reference (
>> https://gist.github.com/wzc314/cf29275f853ee0b2fcd865f9b492c355)
>>
>> Any idea is appreciated!
>> Thank you in advance!
>>
>> Bests,
>> Zicong
>>
>>
>>
>> 2022年4月16日 00:08,Majid Jalili  写道:
>>
>> Hi,
>> Make sure your system has enough MSHRs, out of the box, L1, and L2 are
>> set to have a few MSHR entries.
>> Also, stride prefetcher is not the best, you may try something better:
>> DCPT gives me better numbers.
>>
>> On Fri, Apr 15, 2022 at 4:57 AM Zicong Wang via gem5-users <
>> gem5-users@gem5.org> wrote:
>> Hi Jason,
>>
>>   We are testing the memory bandwidth program STREAM ​(
>> https://www.cs.virginia.edu/stream/)​, 

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
I just pushed a change that will make this error message better.

"fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the
error now says :).

See https://gem5-review.googlesource.com/c/public/gem5/+/59049

Cheers,
Jason

On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power 
wrote:

> Hello,
>
> I believe the problem is that gem5 tries to do too much automatically for
> you! gem5 automatically creates a lot of the constructor/destructor codes.
> Given all of this hidden/automatic code generation, it's difficult to know
> exactly what's going wrong (for both you and for us).
>
> That said, I think the problem is that `PioDevice` is an abstract
> SimObject, not a concrete SimObject. This may work if you instead use the
> `DmaDevice`.
>
> Cheers,
> Jason
>
> On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> By adding a PioDevice() to my version of two_level.py configuration
>> script, I get this error
>>
>>
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>> And checking io_device.cc the constructor looks empty
>>
>>
>>
>> Any help please? Thanks
>>
>>
>>
>> *Details:*
>>
>>
>>
>> Traceback (most recent call last):
>>   File "", line 1, in 
>>   File "build/X86/python/m5/main.py", line 455, in main
>> exec(filecode, scope)
>>
>>
>>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
>> 187, in 
>> m5.instantiate()
>>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>>
>>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
>> self.getCCParams()
>>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
>> cc_params = cc_params_struct()
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>>
>>
>>
>>
>> *Io_device.cc*
>>
>> include "dev/io_device.hh"
>>
>> #include "base/trace.hh"
>> #include "debug/AddrRanges.hh"
>> #include "sim/system.hh"
>>
>> namespace gem5
>> {
>>
>> PioDevice::PioDevice(const Params )
>> : ClockedObject(p), sys(p.system), pioPort(this)
>> {}
>>
>> PioDevice::~PioDevice()
>> {
>> }
>>
>>
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[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hello,

I believe the problem is that gem5 tries to do too much automatically for
you! gem5 automatically creates a lot of the constructor/destructor codes.
Given all of this hidden/automatic code generation, it's difficult to know
exactly what's going wrong (for both you and for us).

That said, I think the problem is that `PioDevice` is an abstract
SimObject, not a concrete SimObject. This may work if you instead use the
`DmaDevice`.

Cheers,
Jason

On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
gem5-users@gem5.org> wrote:

> By adding a PioDevice() to my version of two_level.py configuration
> script, I get this error
>
>
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
> And checking io_device.cc the constructor looks empty
>
>
>
> Any help please? Thanks
>
>
>
> *Details:*
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec(filecode, scope)
>
>
>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
> 187, in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
>
>
>
>
> *Io_device.cc*
>
> include "dev/io_device.hh"
>
> #include "base/trace.hh"
> #include "debug/AddrRanges.hh"
> #include "sim/system.hh"
>
> namespace gem5
> {
>
> PioDevice::PioDevice(const Params )
> : ClockedObject(p), sys(p.system), pioPort(this)
> {}
>
> PioDevice::~PioDevice()
> {
> }
>
>
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[gem5-users] Re: Integrating MCPAT with gem5

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hi Vipin,

McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it
cannot be integrated in the same way. It's not really a timing simulator at
all. You can use gem5's statistics output as the "activity rate" which is
one of the inputs to McPAT. However, the other inputs (e.g., the relative
energy cost of different activations) is not something that you can get
from gem5.

There have been a few scripts created to convert gem5 stats to McPAT files
in the past. However, I do not think that there are any that work with the
current version (21.2) of gem5. You may be able to find one and update it
for your needs.

Cheers,
Jason

On Thu, Apr 21, 2022 at 3:49 AM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Simulators like SST, DRAMSim, SystemC can be integrated with gem5.
> Can we integrate the McPAT with gem5 ? Are there any pointers available
> for doing this?
>
> Thanks in advance.
>
> Regards,
> Vipin Patel
> Ph.D. CSE
> IIT Kanpur
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[gem5-users] Re: How to set the Cache replacement policy

2022-04-12 Thread Jason Lowe-Power via gem5-users
Hi Ankit,

I would suggest modifying your python runscript instead of using command
line parameters.
https://www.gem5.org/documentation/learning_gem5/introduction/ may help
explain how to set parameters on SimObjects.

Cheers,
Jason

On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde  wrote:

> Hi Gem5 Team,
>
> Could you please guide us on how to set the replacement policy to a
> certain value. We are trying to simulate Cache Replacement policies, and
> whichever argument we provide as "--repl_policy==FIFORP()", it by default
> calls LRURP.
>
> Could you please help us on this
>
> Thanks,
> Ankit
>
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[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

2022-03-29 Thread Jason Lowe-Power via gem5-users
Hi Tom,

On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi ,
> This may sound very generic, but i want to try some experiments with the
> out of order implementation. I came across few scenarios, which are listed
> below (any input would be helpful):
> 1. lets consider the following set of instructions (an example which was
> made up):
> Address instr  Operands
> 4357136cmp {"x1", "#16"}
> 4357140cmp {"x2", "#16"}
> 4357144bhi   {"4387895"}
>
> So if we have two execution units which can execute integer instructions,
> then both "cmp" instruction (4357136 and 4357140) could be issued to the
> execution unit. But an "cmp" instruction will update N,Z,C,V flags which
> inturn are used for evaluating conditional flags (eq_ne, hi_ls, cs_cc etc).
> So, can these two cmp be issued to execution units in the same cycle? If
> so, are the N,Z,C,V for each cmp only updated after inorder commit? How is
> it handled ? (do we use temp registers for holding each N,Z,C,V value?)
>

If I remember correctly, we rename all of the flag registers on each
instruction, and we increase the number of physical registers such that
this renaming is not a bottleneck. In a real processor, I don't think it
would work this way, but it should be OK performance-wise.


>
> 2. In speculative execution, how are stores implemented? do we place them
> into a store buffer and write it to memory once its commited?
>

I think that's correct, at least for x86. In Arm/RISC-V the stores could go
out of order to memory as well. You can check the code in the lsq_unit
files in src/cpu/o3 and poke around for "tso" to see exactly how it's
handled. Someone else may remember better than I do :).

Cheers,
Jason


>
> Any input would be appreciated.
> Regards,
> Tom
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[gem5-users] Re: Problem with SimObject

2022-03-28 Thread Jason Lowe-Power via gem5-users
Hi Artyom,

You're absolutely right that the tutorial needs to be updated! The
website is also open source and managed via a git repo:
https://gem5.googlesource.com/public/gem5-website/. Updating this would be
a good way to get started contributing to gem5 :).

By the way, for the namespace, you can also wrap the file in the following
so you don't have to explicitly use namespaces everywhere:

```
namespace gem5
{

}
```

Cheers,
Jason

On Sat, Mar 26, 2022 at 10:57 PM Artyom Liu via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> The problem is solved by literally adding a new parameter `sim_objects`.
>
>  > SimObject("HelloObject.py", sim_objects = ["HelloObject"])
>
> But I find yet another problem with the tutorial: the code that use
> classes from gem5 is missing namespace declaration. For example, the
> class `SimObject` is under namespace `gem5`, but the tutorial is using
> it directly. It makes the compiler unable to find the class.
>
> ```
> #ifndef __LEARNING_GEM5_HELLO_OBJECT_HH__
> #define __LEARNING_GEM5_HELLO_OBJECT_HH__
>
> #include "params/HelloObject.hh"
> #include "sim/sim_object.hh"
>
> class HelloObject : public SimObject
> {
>public:
>  HelloObject(const HelloObjectParams );
> };
>
> #endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
> ```
>
> For the compiler to work, we should use `gem5::SimObject` instead. And
> `gem5::HelloObjectParams` for the same reason.
>
> None of the problems are mentioned in the tutorial. I wonder if it is
> necessary to *update* the tutorial?
>
> Artyom
> artyom...@hust.edu.cn
>
> On 3/27/22 10:05, Artyom Liu wrote:
> > Hi,
> >
> > I'm new to gem5 and just start learning by following the tutorial on
> > gem5.org. However, there's a problem when I try to create my custom
> > object[1].
> >
> > [1]: https://www.gem5.org/documentation/learning_gem5/part2/helloobject/
> >
> > I follow exactly the guide, but I fail to re-compile with scons. The
> > error message as below.
> >
> >  > Error: SimObject(HelloObject.py...) must list c++ sim_objects or
> > enums > (set either to [] if there are none).
> >
> > My gem5 version is Version 21.2.1.0, and I noticed that there's an *API
> > change* about SimObject declaration in Version 21.2.0.0, requiring that
> > sim_object parameter of SimObject declaration "should list all SimObject
> > classes which have a type attribute defined".
> >
> > It matches the error message. So I wonder how could I change my
> > SConscript to fit this change? My current SConscript is from the
> tutorial.
> >
> > ```
> > Import("*")
> >
> > SimObject("HelloObject.py")
> > Source("hello_object.py")
> > ```
> >
> > Artyom
> > artyom...@hust.edu.cn
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[gem5-users] Re: gem5 and non volatile memory

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hello Taiyu,

I would suggest reaching out to the VANS authors. Since this project is not
part of the gem5 repository, we have little control over the integration.

Cheers,
Jason

On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:

> Could you give me some advise to integrate VANS with new version gem5?
> VANS is interrogated to commit id dde093b2 .
> However the newer version of gem5 breaks a lot of old Python interfaces,
> making it unable to run with VANS GEM5 wrapper, although compilation is
> fine.
> When I run VANS with new version gem5.
> The respond pkt can not sent via port.sendTimingResp.
>
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[gem5-users] Re: CXL protocol/model implementation

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hi Zicong,

1. I personally don't believe that CXL in SE mode would be very
interesting. From  my point of view, CXL would be interesting only to
capture the OS and system-level effects. That said, you may be able to test
CXL.cache in SE mode.

2.
To implement the different protocols:
CXL.io: This would be extending the PCI devices in gem5/src/dev. This part
of the protocol will need to be implemented functionally to get the OS
drivers to work correctly.
CXL.mem: This should be quite straightforward to implement without any
changes to any coherence protocols. This part of CXL would just be setting
up the memory ranges correctly and hooking it into CXL.io. I would start
with this one.
CXL.cache: To model the coherence in CXL.cache, you will need to add and/or
modify a new Ruby coherence protocol. To get this to work, you'll first
have to have CXL.io and be able to figure out how to communicate the memory
ranges (like CXL.mem).

3.
CXLDevice would most likely inherit from PciDevice. The other devices would
be whatever you want them to be (e.g., a GPU which speaks CXL.cache or a
memory device that speaks CXL.mem). Then these devices would "register"
with the CXLDevice and through the configuration file you will hook up the
other devices in the protocol.

The most complex part of all of this will be the configuration. I would
suggest trying to make the configuration as modular as possible. The
examples in the standard library should help.

I've given this some thought, but I haven't started implementing anything.
I'm sure that the process I outlined above will change as you start diving
into things.

Cheers,
Jason

On Fri, Mar 25, 2022 at 1:35 AM Zicong Wang via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>  We are planning to implement and test CXL protocol/model with gem5, and
> I've seen your reply about CXL implementation (
> https://www.mail-archive.com/gem5-users@gem5.org/msg18881.html). Before
> diving into the code, I have some questions about implementation. Could you
> please provide some tips? Thanks!​
>
>  1. Could it be implemented in SE mode? It seems to be complicated with
> the OS layer and driver layer in FS mode, and we want to firstly implement
> an initial model (e.g., a type 1 (cxl.io + cxl.cache) or type 3 (cxl.io +
> cxl.mem) device) as simple as possible.
>
>  2. Could the cxl.cache/mem sub-protocol ​be implemented in SLICC? How to
> treat and implement the cxl.io sub-protocol (which is PCIe-like)?
>
>  3. What kind of SimObject should be implemented roughly (CXLDevice,
> CXLController, etc.)?​ Should the CXLDevice be inherited from PciDevice
> class?
>
>  Thank you very much!
>
>
> Best Regards,
>
> Zicong Wang
>
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[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Tom,

I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags
which may help figure it out. It's possible that's the address of a
dynamically-loaded library as well.

Also, this trace looks like it came from Arm instead of x86. I don't
have as much experience looking at Arm addresses and guessing the meaning
:).

Cheers,
Jason

On Tue, Mar 22, 2022 at 8:32 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
> I have one doubt.
> The following is some selected parts of Exec trace:
> If we look at lines:
> line 4:   ldr   x1, [sp]: MemRead :
> D=0x0001
> A=0x7efe70
> line 74  :   ldr   x1, [x0]: MemRead :
> D=0x0010
> A=0x7efe90
> line 88  :   ldr   x3, [x8, #3840]: MemRead :  D=0x0001
> A=0x498f00
> line 92  :   ldr   x7, [x10, #3896]  : MemRead :  D=0x0001
> A=0x499f38
> line 152:   ldr   x28, [x0, #8]: MemRead :  D=0x004471e3
> A=0x7efe98
>
> Prior to these lines, there was no MemWrite to the corresponding address.
> Is this also related to Stack addresses?Could you please provide an insight
> on how these addresses are loaded with these data?
>
> Any information on the same would hugely help.
>
> Regards,
> Tom
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[gem5-users] Re: Building Old gem5 error

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hello Abdelrahman,

Unfortunately, it's incredibly difficult to keep the development
environment for older versions of gem5 working. You may be able to find an
old dockerfile in those gem5 repositories that could help to recreate the
build environment. (I'm not sure if we were using docker at the time or
not.)

Another thing you can try is specifying a python version when running
scons. You can use
```
python2 `which scons` build/X86_MESI_Two_Level/gem5.opt
```
That should force scons to use python2. However, you might find that the
scons version that you installed only works with python3. Again, it's
really hard to get these older gem5's to build on modern systems.

If those two ideas don't work, a final suggestion would be to create a
docker container (or install) Ubuntu 16.04 and try with that. 16.04
should have everything python2 by default.

Good luck!

Cheers,
Jason

On Tue, Mar 22, 2022 at 3:19 AM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to build older version(s) of gem5 (specifically, the ones used
> for InvisiSpec and STT). I understand that this version of gem5 requires
> python2, thus, I build a virtual environment based on python2 and
> re-installed scons. However, when I run this command:
> scons build/X86_MESI_Two_Level/gem5.opt -j16
>
> I got the following error:
>
> AttributeError: 'NoneType' object has no attribute 'group':
>   File "stt/SConstruct", line 435:
> *if not as_version or compareVersions(as_version, "2.23") < 0:*
>   File "stt/src/python/m5/util/__init__.py", line 133:
> v1 = make_version_list(v1)
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>
> Same with InvisiSpec.
>
> Before line 435@stt/SConstruct, which is underlined above, line 433 has
> the following:
> as_version = as_version_raw[-1].split('-')[0] if as_version_raw else None
>
> When I printed as_version, its value was:
> same
>
> How can I solve this problem? Or, what further information do you need me
> to share?
>
> Thank you!
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Liyan,

This looks like a stack address to me, so it won't appear in the objdump.

Since you're using SE mode, gem5 is controlling the physical address
mappings (not the OS). You can use the "Vma" debug flag to see all of the
virtual memory areas that gem5 creates/assigns. the "SyscallVerbose" flag
could also be useful.

Cheers,
Jason

On Mon, Mar 21, 2022 at 12:46 AM liyan.chen--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I used the following command to view the virtual address translation
> process.
>
>   build/X86/gem5.opt --debug-flags=Exec,TLB
> --debug-file=/home/liyan/Desktop/gem5/m5out/debug.txt configs/example/se.py
> --cpu-type=TimingSimpleCPU --caches --l2cache --mem-type=DRAMsim3
> --num-cpus=1 -c "tests/test-progs/hello/bin/x86/linux/hello"
>
> However, I found some strange virtual address such as 0x7fffee20
>
>   56500: system.cpu.dtb: Translating vaddr 0x7fffee20.
>   56500: system.cpu.dtb: In protected mode.
>   56500: system.cpu.dtb: Paging enabled.
>   56500: system.cpu.dtb: Handling a TLB miss for address 0x7fffee20 at
> pc 0x400a55.
>   56500: system.cpu.dtb: Mapping 0x7fffe000 to 0xbd000
>   56500: system.cpu.dtb: Miss was serviced.
>   56500: system.cpu.dtb: Entry found with paddr 0xbd000, doing protection
> checks.
>   56500: system.cpu.dtb: Translated 0x7fffee20 -> 0xbde20.
>
> And it(0x7fffee20) also appears here(I don't know whether there is any
> relationship)
>
>   56500: system.cpu T0 : @_start+5: pop rsi
>   56500: system.cpu T0 : @_start+5.0  :   POP_R : ldis   t1, SS:[rsp] :
> MemRead :  D=0x0001 A=0x7fffee20
>  110500: system.cpu T0 : @_start+5.1  :   POP_R : addi   rsp, rsp, 0x8 :
> IntAlu :  D=0x7fffee28
>  110500: system.cpu T0 : @_start+5.2  :   POP_R : mov   rsi, rsi, t1 :
> IntAlu :  D=0x0001
>
> Then I used following command to check the address in hello.dump file but
> didn't find such address.
>
>   objdump -D hello > hello.dump
>
> I'm not familiar with the compilation process and work flow of the core.
> Does anyone know why these address exist?
>
> Any ideas are appreciated! Please reply if you have some advice. Thanks in
> advance!
>
> Liyan Chen
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[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

2022-03-17 Thread Jason Lowe-Power via gem5-users
Hello,

I don't believe there's a way to do that right now. However, in atomic
mode, many stats *are* skipped as they are only accessed in the "timing"
functions. I doubt it would make much performance difference. However,
that's just a guess, and I could be wrong.

Cheers,
Jason

On Wed, Mar 16, 2022 at 6:25 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  In the Atomic CPU, only a function simulation is performed for
> enabling or debugging applications. The performance statistics of the
> architecture are not concerned. Therefore, only a small items are required,
> e.g. number of instructions or cycles.
>
>
>
> According to my understanding, each performance measurement item in the
> code may affect the simulation speed. If we can disable statistics items
> that are not concerned in most functional models, the simulation speed may
> be greatly improved. I do not know whether my understanding is correct. If
> so, does GEM5 consider the performance statistics switch?
>
>
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[gem5-users] Re: Is thread lock not working under both SE and FS mode?

2022-03-14 Thread Jason Lowe-Power via gem5-users
Hi Meng,

It depends on the ISA you're using and the configuration of the system. For
instance, x86+classic caches is known to have some synchronization issues.
The transactional memory support only works with Arm, and I'm not sure
which memory system it requires.

What system are you trying to simulate?

Cheers,
Jason

On Sat, Mar 12, 2022 at 11:45 PM Chen Meng via gem5-users <
gem5-users@gem5.org> wrote:

> Hi!
>
> I was trying to run a multi-threaded program with thread locks, I tried
> many methods but only to result in failure. I borrowed the program code
> with thread lock from the following page:
> https://www.gem5.org/project/2020/10/27/tme.html , and it turns out to be
> unstable when I run it with FS mode.
>
> My gem5 version is v21.1.0.2, and my script is borrowed from
> gem5_resources also at v21.1.0.2 (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2),
> everything is stick to the SPEC-2017 tutorial (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2/src/spec-2017/README.md),
> except that I substitute the SPEC benchmarks with my own program.
>
> Any ideas are appreciated! Please reply if you have some advice or
> face/have faced the same problem. Thanks!
>
> Best Regards,
> Meng
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,


> Is there a better way you can suggest using SPEC2017 in FS mode to
> evaluate my system on gem5?
>

No, there's not a better way, as far as I know :).


> My understanding is that the FS simulation is significantly slow. Any
> guidelines on how to make it as fast as possible?


You can use sampling methodologies, but there are tradeoffs there. You can
run different simulation configurations in parallel as well. Generally,
there's nothing easy to do to improve simulation speed.

Jason

On Thu, Mar 10, 2022 at 7:17 AM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Thank you so much.
>
> There were some questions that you missed at the end of the email. I list
> them below again for convenience:
>
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>- My understanding is that the FS simulation is significantly slow.
>Any guidelines on how to make it as fast as possible?
>
> Above all, thanks a lot for taking time helping us. Much appreciated!
>
>
>
>
> On Thu, Mar 10, 2022 at 7:01 AM Jason Lowe-Power 
> wrote:
>
>> Hi Abdelrahman,
>>
>> From the get error message, it says:
>> "This error may be caused by a too restrictive setting
>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>   The default value was changed to 2 in kernel 4.6
>>   A value greater than 1 prevents gem5 from making
>>   the syscall to perf_event_open"
>>
>> If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
>> work.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am trying to run gem5 in FS mode using the following command (I am
>>> using gem5 v21.2):
>>>
>>> gem5/build/X86/gem5.opt
>>> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
>>> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
>>> 503.bwaves_r --size test
>>>
>>> However, I got the following error (There are details after the error,
>>> please continue reading after you check the error):
>>>
>>> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>>> simulation...
>>> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach
>>> recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
>>> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> ./spec_fs_run.sh: line 16: 1648681 Aborted
>>>
>>> I have done some checking:
>>>
>>>- Ran kvm-ok to make sure that KVM is working:
>>>$kvm-ok
>>>INFO: /dev/kvm exists
>>>KVM acceleration can be used
>>>
>>>- Also, I checked the value
>>>inside /proc/sys/kernel/perf_event_paranoid
>>>$cat /proc/sys/kernel/perf_event_paranoid
>>>3
>>>
>>>- The SPEC17 is created by following the instructions in:
>>>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>>>
>>>
>>> Questions:
>>>
>>>- How to solve this error?
>>>
>>>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of
>>>the linux running on my host machine to 1, in case this solves the 
>>> problem?
>>>
>>>- Is there a better way you can suggest using SPEC2017 in FS mode to
>>>evaluate my system on gem5?
>>>
>>>
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>>
>> --
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman,

>From the get error message, it says:
"This error may be caused by a too restrictive setting
  in the file '/proc/sys/kernel/perf_event_paranoid'
  The default value was changed to 2 in kernel 4.6
  A value greater than 1 prevents gem5 from making
  the syscall to perf_event_open"

If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
work.

Cheers,
Jason

On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am trying to run gem5 in FS mode using the following command (I am using
> gem5 v21.2):
>
> gem5/build/X86/gem5.opt
> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
> 503.bwaves_r --size test
>
> However, I got the following error (There are details after the error,
> please continue reading after you check the error):
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach recieved
> error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> ./spec_fs_run.sh: line 16: 1648681 Aborted
>
> I have done some checking:
>
>- Ran kvm-ok to make sure that KVM is working:
>$kvm-ok
>INFO: /dev/kvm exists
>KVM acceleration can be used
>
>- Also, I checked the value inside /proc/sys/kernel/perf_event_paranoid
>$cat /proc/sys/kernel/perf_event_paranoid
>3
>
>- The SPEC17 is created by following the instructions in:
>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>
>
> Questions:
>
>- How to solve this error?
>
>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of the
>linux running on my host machine to 1, in case this solves the problem?
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
Great question!

Since KVM is executing using the host's hardware, you can't use the magic
instructions! However, we have another interface (called `m5_addr` or
`m5-addr` in the code, IIRC) that will work with KVM. If you compile using
-DM5_ADDR=, it should work in KVM. For x86, we usually
use 0x. Then, I believe you need to call a function to map
the memory (not sure what it's called, it's not in the documentation)
before calling any m5 functions.

See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for an example.
Also see
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/Makefile.shared#9
for how we compile the parsec hooks with m5 addr.

Note: it looks like either parsec is a bit out of date with current gem5
develop or the README.md in util/m5 is out of date. I'm not sure which.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:47 PM George Michelogiannakis <
mixelog...@yahoo.co.uk> wrote:

> Hello Jason and everyone,
>
> I'll add the fix to my todo list :)
>
> But before then, I'm confused by something. Thanks for the link to hooks
> and indeed I "m5_work_begin(0,0);. I recompiled the benchmarks I had with
> work begin and end. It's just adding "m5_work_begin(0,0)" and 
> "m5_work_end(0,0)"
> at the right spots, without anything else fancy. It compiles and links
> fine. When I try to run natively as expected they terminate due to an
> illegal instruction ("./run: line 1:  1161 Illegal instruction").
> However, the exact same error happens if I run the same binary in FS mode.
> Note that I'm running first in KVM mode on a x86 host hoping to switch CPUs
> once the work start event happens. Are magic ops unsupported in KVM mode?
>
> Thanks!
>
>
> On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via
> gem5-users  wrote:
>
>
> Hi George,
>
> For workbegin/workend, they can be called from within applications if you
> link to the libm5 library. For instance, in the parsec resource here:
> https://resources.gem5.org/resources/parsec we use the m5_workbegin()
> function in the ROI hooks. See
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
> for the code.
>
> This works in both SE mode and FS mode. I have no idea why those functions
> are not available in the m5 binary. This seems like an oversight, and it
> should be a simple fix. If you want to make the fix, we'd appreciate it,
> otherwise, we'll put it on the to do list :).
>
> If you require using the m5 binary without any changes, then you can use
> `m5 exit` and modify your run script to "understand" that the first exit is
> to reset the stats, the second exit means to dump the stats, etc.
>
> Cheers,
> Jason
>
> On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi George,
>
>
>
> Thanks for reporting this, I noticed the same issue. When we transitioned
> from the old m5 subsystem (assembly based) to the new C based one we forgot
> to provide an implementation for workbegin and workend I suppose. Putting
> Gabe on CC
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *George Michelogiannakis via gem5-users 
> *Date: *Wednesday, 9 March 2022 at 06:54
> *To: *gem5-users@gem5.org 
> *Cc: *George Michelogiannakis 
> *Subject: *[gem5-users] M5 Fs utility workbegin
>
> Hello Gem5 community,
>
>
>
> I'm trying to use the M5 utility meant for full system mode to signal work
> begin and end. I see in the documentation that the utility supports these
> parameters:
>
>
>
>-

[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
Hi George,

For workbegin/workend, they can be called from within applications if you
link to the libm5 library. For instance, in the parsec resource here:
https://resources.gem5.org/resources/parsec we use the m5_workbegin()
function in the ROI hooks. See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for the code.

This works in both SE mode and FS mode. I have no idea why those functions
are not available in the m5 binary. This seems like an oversight, and it
should be a simple fix. If you want to make the fix, we'd appreciate it,
otherwise, we'll put it on the to do list :).

If you require using the m5 binary without any changes, then you can use
`m5 exit` and modify your run script to "understand" that the first exit is
to reset the stats, the second exit means to dump the stats, etc.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
gem5-users@gem5.org> wrote:

> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
>> Hi George,
>>
>>
>>
>> Thanks for reporting this, I noticed the same issue. When we transitioned
>> from the old m5 subsystem (assembly based) to the new C based one we forgot
>> to provide an implementation for workbegin and workend I suppose. Putting
>> Gabe on CC
>>
>>
>>
>> Kind Regards
>>
>>
>>
>> Giacomo
>>
>>
>>
>> *From: *George Michelogiannakis via gem5-users 
>> *Date: *Wednesday, 9 March 2022 at 06:54
>> *To: *gem5-users@gem5.org 
>> *Cc: *George Michelogiannakis 
>> *Subject: *[gem5-users] M5 Fs utility workbegin
>>
>> Hello Gem5 community,
>>
>>
>>
>> I'm trying to use the M5 utility meant for full system mode to signal
>> work begin and end. I see in the documentation that the utility supports
>> these parameters:
>>
>>
>>
>>- workbegin: Cause an exit evet of type, “workbegin”, that could be
>>used to mark the begining of an ROI.
>>- workend: Cause an exit event of type, “workend”, that could be used
>>to mark the termination of an ROI.
>>
>> But when I run the utility in X86 after compiling it for X86 those two
>> options aren't available as commands. There is a "fail" option with a
>> parameter that isn't mentioned in the documentation. Is that the way to
>> simulate workbegin and workend?
>>
>>
>>
>> Thanks in advance,
>>
>>   George M
>>
>>
>>
>>
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