Re: [Intel-gfx] [PATCH] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

[Mika Kuoppala]

Michel Thierry  writes:

> A previous commit resets the Context Status Buffer (CSB) read pointer in
> ring init
> commit c0a03a2e4c4e ("drm/i915: Reset CSB read pointer in ring init")
>
> This is generally correct, but this pointer is not reset after
> suspend/resume in some platforms (cht). In this case, the driver should
> read the register value instead of resetting the sw read counter to 0.
> Otherwise we process old events, leading to unwanted pre-emptions or
> something worse.
>
> But in other platforms (bdw) and also during GPU reset or power up, the
> CSBWP is reset to 0x7 (an invalid number), and in this case the read
> pointer should be set to 0.
>
> Signed-off-by: Lei Shen 
> Signed-off-by: Deepak S 
> Signed-off-by: Michel Thierry 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 24 +++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index ff9a481..dd87812 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1479,6 +1479,7 @@ static int gen8_init_common_ring(struct intel_engine_cs 
> *ring)
>  {
>   struct drm_device *dev = ring->dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
> + u8 next_context_status_buffer_hw;
>  
>   lrc_setup_hardware_status_page(ring,
>   ring->default_context->engine[ring->id].state);
> @@ -1496,7 +1497,28 @@ static int gen8_init_common_ring(struct 
> intel_engine_cs *ring)
>  _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
>  _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>   POSTING_READ(RING_MODE_GEN7(ring));
> - ring->next_context_status_buffer = 0;
> +
> + /*
> +  * Instead of resetting the Context Status Buffer (CSB) read pointer to
> +  * zero, we need to read the write pointer from hardware and use its
> +  * value because "this register is power context save restored".
> +  * Effectively, these states have been observed:
> +  *
> +  *  | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
> +  * BDW  | CSB regs not reset   | CSB regs reset   |
> +  * CHT  | CSB regs not reset   | CSB regs not reset   |
> +  */
> + next_context_status_buffer_hw = 
> I915_READ(RING_CONTEXT_STATUS_PTR(ring)) & 0x07;
> +
> + /*
> +  * When the CSB registers are reset (also after power-up / gpu reset),
> +  * CSB write pointer is set to all 1's, which is not valid, use 0 in
> +  * this special case.
> +  */
> + if (next_context_status_buffer_hw == 0x7)
> + next_context_status_buffer_hw = 0;


If hardware has been reset and we have b111 here, I assume
the first write will be at index zero.

If we look at the interrupt code there is while (read_pointer <
write_pointer). Initializing next status buffer to zero
would mean that you miss the first write to csb[0].

If b111 is found, I think the correct value is 5.

-Mika


> +
> + ring->next_context_status_buffer = next_context_status_buffer_hw;
>   DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
>  
>   memset(>hangcheck, 0, sizeof(ring->hangcheck));
> -- 
> 2.5.3
>
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Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

[Vivi, Rodrigo]

On Fri, 2015-09-25 at 13:52 +0300, Jani Nikula wrote:
> On Wed, 23 Sep 2015, Rodrigo Vivi  wrote:
> > In case something goes wrong with power well initialization we were
> > calling
> > intel_prepare_ddi during boot while encoder list isnt't initilized.
> 
> Broken record, is this a regression, what is the regressing commit,
> or
> if this was always broken, which commit introduced the broken
> feature?

I believe it is broken since this call was introduced, but when
everything goes as expected it isn't executed.
Only in rare cases where power well initialization didn't go well and
post call is called during init it will trigger this case.
I don't believe this is something that a regular user of stables
platforms should worrie though... but it is always good to protect to
be on the safe side.

> 
> BR,
> Jani.
> 
> 
> > 
> > [9.618747] i915 :00:02.0: Invalid ROM contents
> > [9.631446] [drm] failed to find VBIOS tables
> > [9.720036] BUG: unable to handle kernel NULL pointer
> > dereference at 
> > 0058
> > [9.721986] IP: []
> > ddi_get_encoder_port+0x82/0x190 [i915]
> > [9.723736] PGD 0
> > [9.724286] Oops:  [#1] PREEMPT SMP
> > [9.725386] Modules linked in: intel_powerclamp snd_hda_intel(+)
> > coretemp crc
> > 32c_intel snd_hda_codec snd_hda_core serio_raw snd_pcm snd_timer
> > i915(+) parport
> > _pc parport pinctrl_sunrisepoint pinctrl_intel nfsd nfs_acl
> > [9.730635] CPU: 0 PID: 497 Comm: systemd-udevd Not tainted
> > 4.3.0-rc2-eywa-10
> > 967-g72de2cfd-dirty #2
> > [9.732785] Hardware name: Intel Corporation Cannonlake Client
> > platform/Skyla
> > ke DT DDR4 RVP8, BIOS CNLSE2R1.R00.X021.B00.1508040310 08/04/2015
> > [9.735785] task: 88008a704700 ti: 88016a1ac000 task.ti:
> > 88016a1a
> > c000
> > [9.737584] RIP: 0010:[]  []
> > ddi_get_enco
> > der_port+0x82/0x190 [i915]
> > [9.739934] RSP: :88016a1af710  EFLAGS: 00010296
> > [9.741184] RAX: 004e RBX: 88008a9edc98 RCX:
> > 0001
> > [9.742934] RDX: 004e RSI: 81fc1e82 RDI:
> > 
> > [9.744634] RBP: 88016a1af730 R08:  R09:
> > 0578
> > [9.746333] R10: 1065 R11: 0578 R12:
> > fff8
> > [9.748033] R13: 88016a1af7a8 R14: 88016a1af794 R15:
> > 
> > [9.749733] FS:  7eff2e1e07c0()
> > GS:88016fc0() knlGS:0
> > 000
> > [9.751683] CS:  0010 DS:  ES:  CR0: 80050033
> > [9.753083] CR2: 0058 CR3: 00016922b000 CR4:
> > 003406f0
> > [9.754782] Stack:
> > [9.755332]  88008a9edc98 88008a9ed800 a01d07b0
> > fffb9
> > 09e
> > [9.757232]  88016a1af7d8 a0154ea7 0246
> > 88016a370
> > 080
> > [9.759182]  88016a370080 88008a9ed800 0246
> > 88008a9ed
> > c98
> > [9.761132] Call Trace:
> > [9.761782]  [] intel_prepare_ddi+0x67/0x860
> > [i915]
> > [9.763332]  [] ?
> > _raw_spin_unlock_irqrestore+0x26/0x40
> > [9.765031]  [] ? gen9_read32+0x141/0x360
> > [i915]
> > [9.766531]  [] skl_set_power_well+0x431/0xa80
> > [i915]
> > [9.768181]  []
> > skl_power_well_enable+0x13/0x20 [i915]
> > [9.769781]  []
> > intel_power_well_enable+0x28/0x50 [i915]
> > [9.771481]  []
> > intel_display_power_get+0x92/0xc0 [i915]
> > [9.773180]  []
> > intel_display_set_init_power+0x3b/0x40 [i91
> > 5]
> > [9.774980]  []
> > intel_power_domains_init_hw+0x120/0x520 [i9
> > 15]
> > [9.776780]  [] i915_driver_load+0xb21/0xf40
> > [i915]
> > 
> > So let's protect this case.
> > 
> > My first attempt was to remove the intel_prepare_ddi, but Daniel
> > had pointed out
> > this is really needed to restore those registers values. And Imre
> > pointed out
> > that this case was without the flag protection and this was
> > actually where things
> > were going bad. So I've just checked and this indeed solves my
> > issue.
> > 
> > Cc: Imre Deak 
> > Cc: Daniel Vetter 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 85c35fd..d194492 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -246,7 +246,8 @@ static void skl_power_well_post_enable(struct
> > drm_i915_private *dev_priv,
> > }
> >  
> > if (power_well->data == SKL_DISP_PW_1) {
> > -   intel_prepare_ddi(dev);
> > +   if (!dev_priv->power_domains.initializing)
> > +   intel_prepare_ddi(dev);
> > gen8_irq_power_well_post_enable(dev_priv, 1 <<
> > PIPE_A);
> > }
> 

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Add GuC css header parser

[Jani Nikula]

On Thu, 24 Sep 2015, Yu Dai  wrote:
> On 09/24/2015 12:04 PM, Dave Gordon wrote:
>> On 24/09/15 19:34, Yu Dai wrote:
>> >
>> >
>> > On 09/24/2015 07:23 AM, Dave Gordon wrote:
>> >> On 22/09/15 21:48, yu@intel.com wrote:
>> >> > From: Alex Dai 
>> >> >
>> >> > By using information from GuC css header, we can eliminate some
>> >> > hard code w.r.t size of some components of firmware.
>> >> >
>> >> > v2: Add indent into DOC to make fixed-width format rather than
>> >> > change the tmpl.
>> >> >
>> >> > v1: 1) guc_css_header is defined as __packed now
>> >> >  2) Add and correct GuC related topics in kernel/Doc
>> >> >
>> >> > Signed-off-by: Alex Dai 
>> >> > ---
>> >> >   Documentation/DocBook/drm.tmpl  |   9 ++-
>> >> >   drivers/gpu/drm/i915/intel_guc.h|   2 +-
>> >> >   drivers/gpu/drm/i915/intel_guc_fwif.h   |  36 +++
>> >> >   drivers/gpu/drm/i915/intel_guc_loader.c | 107
>> >> ++--
>> >> >   4 files changed, 117 insertions(+), 37 deletions(-)
>> >> >
>> >> > diff --git a/Documentation/DocBook/drm.tmpl
>> >> b/Documentation/DocBook/drm.tmpl
>> >> > index 66bc646..116332f 100644
>> >> > --- a/Documentation/DocBook/drm.tmpl
>> >> > +++ b/Documentation/DocBook/drm.tmpl
>> >> > @@ -4155,14 +4155,19 @@ int num_ioctls;
>> >> > GuC-based Command Submission
>> >> > 
>> >> > ../linux-image-4.3.0-rc2-dsg-11022-g9765caf-dsg-intel-nightly_4.3.0-rc2-dsg-11022-g9765caf-dsg-intel-nightly-7_amd64.deb
>> >> >   GuC
>> >> > -!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader
>> >> > +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC
>> >> >   !Idrivers/gpu/drm/i915/intel_guc_loader.c
>> >> > 
>> >> > 
>> >> >   GuC Client
>> >> > -!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command
>> >> submissison
>> >> > +!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC Client
>> >> >   !Idrivers/gpu/drm/i915/i915_guc_submission.c
>> >> > 
>> >> > +  
>> >> > +GuC Firmware Layout
>> >> > +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC Firmware Layout
>> >> > +!Idrivers/gpu/drm/i915/intel_guc_loader.c
>> >> > +  
>> >> >   
>> >> >
>> >> >   
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc.h
>> >> b/drivers/gpu/drm/i915/intel_guc.h
>> >> > index 4ec2d27..e1389fc 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc.h
>> >> > +++ b/drivers/gpu/drm/i915/intel_guc.h
>> >> > @@ -71,6 +71,7 @@ struct intel_guc_fw {
>> >> >   struct drm_i915_gem_object *guc_fw_obj;
>> >> >   enum intel_guc_fw_statusguc_fw_fetch_status;
>> >> >   enum intel_guc_fw_statusguc_fw_load_status;
>> >> > +struct guc_css_headerguc_fw_header;
>> >> >
>> >> >   uint16_tguc_fw_major_wanted;
>> >> >   uint16_tguc_fw_minor_wanted;
>> >> > @@ -80,7 +81,6 @@ struct intel_guc_fw {
>> >> >
>> >> >   struct intel_guc {
>> >> >   struct intel_guc_fw guc_fw;
>> >> > -
>> >> >   uint32_t log_flags;
>> >> >   struct drm_i915_gem_object *log_obj;
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > index e1f47ba..006dc0d 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > @@ -122,6 +122,42 @@
>> >> >
>> >> >   #define GUC_CTL_MAX_DWORDS(GUC_CTL_RSRVD + 1)
>> >> >
>> >> > +struct guc_css_header {
>> >> > +uint32_t module_type;
>> >> > +uint32_t header_len; /* header length plus size of all other
>> >> keys */
>> >> > +uint32_t header_version;
>> >> > +uint32_t module_id;
>> >> > +uint32_t module_vendor;
>> >> > +union {
>> >> > +struct {
>> >> > +uint8_t day;
>> >> > +uint8_t month;
>> >> > +uint16_t year;
>> >> > +};
>> >> > +uint32_t date;
>> >> > +};
>> >> > +uint32_t size; /* uCode size plus header_len */
>> >> > +uint32_t key_size;
>> >> > +uint32_t modulus_size;
>> >> > +uint32_t exponent_size;
>> >> > +union {
>> >> > +struct {
>> >> > +uint8_t hour;
>> >> > +uint8_t min;
>> >> > +uint16_t sec;
>> >> > +};
>> >> > +uint32_t time;
>> >> > +};
>> >> > +
>> >> > +char username[8];
>> >> > +char buildnumber[12];
>> >> > +uint32_t device_id;
>> >> > +uint32_t guc_sw_version;
>> >> > +uint32_t prod_preprod_fw;
>> >> > +uint32_t reserved[12];
>> >> > +uint32_t header_info;
>> >> > +} __packed;
>> >> > +
>> >> >   struct guc_doorbell_info {
>> >> >   u32 db_status;
>> >> >   u32 cookie;
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> > index 40241f3..a6703b4 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> 

Re: [Intel-gfx] [PATCH] drm/i915: Detect virtual south bridge

[Jesse Barnes]

On 09/24/2015 08:41 PM, Tian, Kevin wrote:
>> From: Jesse Barnes [mailto:jbar...@virtuousgeek.org]
>> Sent: Friday, September 25, 2015 12:41 AM
>>
>> On 08/28/2015 05:10 AM, robert.beck...@intel.com wrote:
>>> From: Robert Beckett 
>>>
>>> Virtualized systems often use a virtual P2X4 south bridge.
>>> Detect this in intel_detect_pch and make a best guess as to which PCH
>>> we should be using.
>>>
>>> This was seen on vmware esxi hypervisor. When passing the graphics device
>>> through to a guest, it can not pass through the PCH. Instead it simulates
>>> a P2X4 southbridge.
>>>
>>> Signed-off-by: Robert Beckett 
>>> ---
>>>  drivers/gpu/drm/i915/i915_drv.c |   30
>> ++
>>>  drivers/gpu/drm/i915/i915_drv.h |1 +
>>>  2 files changed, 31 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index ce3bd0c..8e158b3 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -443,6 +443,34 @@ static const struct pci_device_id pciidlist[] = {  
>>> /* aka
>> */
>>>
>>>  MODULE_DEVICE_TABLE(pci, pciidlist);
>>>
>>> +static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
>>> +{
>>> +   enum intel_pch ret = PCH_NOP;
>>> +
>>> +   /*
>>> +* In a virtualized passthrough environment we can be in a
>>> +* setup where the ISA bridge is not able to be passed through.
>>> +* In this case, a south bridge can be emulated and we have to
>>> +* make an educated guess as to which PCH is really there.
>>> +*/
>>> +
>>> +   if (IS_GEN5(dev)) {
>>> +   ret = PCH_IBX;
>>> +   DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
>>> +   } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
>>> +   ret = PCH_CPT;
>>> +   DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
>>> +   } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
>>> +   ret = PCH_LPT;
>>> +   DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
>>> +   } else if (IS_SKYLAKE(dev)) {
>>> +   ret = PCH_SPT;
>>> +   DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
>>> +   }
>>> +
>>> +   return ret;
>>> +}
>>> +
>>>  void intel_detect_pch(struct drm_device *dev)
>>>  {
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> @@ -503,6 +531,8 @@ void intel_detect_pch(struct drm_device *dev)
>>> dev_priv->pch_type = PCH_SPT;
>>> DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
>>> WARN_ON(!IS_SKYLAKE(dev));
>>> +   } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {
>>> +   dev_priv->pch_type = intel_virt_detect_pch(dev);
>>> } else
>>> continue;
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 8c93845..6eb0230 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2584,6 +2584,7 @@ struct drm_i915_cmd_table {
>>>  #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE0x9c00
>>>  #define INTEL_PCH_SPT_DEVICE_ID_TYPE   0xA100
>>>  #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE0x9D00
>>> +#define INTEL_PCH_P2X_DEVICE_ID_TYPE   0x7100
>>>
>>>  #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
>>>  #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
>>>
>>
>> Assuming Kevin is ok with this:
>> Reviewed-by: Jesse Barnes 
> 
> Yes, I'm OK with this change. Just one comment. Does it make
> sense to always have the guess as the fallback, instead of only
> for P2X? If native side is OK with this, it will remove the need 
> to add more IDs for different hypervisors in the future...

Yeah, at this point I don't think we have mix & match cases to worry
about, so we could guess based on the GPU type across the board.

Jesse

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[Intel-gfx] [PATCH v2] drm/i915: Add CD and pixel clock information

[Mika Kahola]

This patch adds information of current and maximum CD clock
frequency and pixel clock frequency information on 'i915_debugfs.c'.

v2:
- combined seperate patches for current CD clock, maximum CD clock
  and maximum pixel clock
- space added between the frequency value and the unit

Signed-off-by: Mika Kahola 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..3832699 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1309,6 +1309,10 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_puts(m, "no P-state info available\n");
}
 
+   seq_printf(m, "Current CD clock frequency: %d kHz\n", 
dev_priv->cdclk_freq);
+   seq_printf(m, "Max CD clock frequency: %d kHz\n", 
dev_priv->max_cdclk_freq);
+   seq_printf(m, "Max pixel clock frequency: %d kHz\n", 
dev_priv->max_dotclk_freq);
+
 out:
intel_runtime_pm_put(dev_priv);
return ret;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix primary_get_hw_state for gen9+.

[Jani Nikula]

On Wed, 23 Sep 2015, Maarten Lankhorst  
wrote:
> On skylake and broxton the old registers are no longer in use.
> Instead it uses universal planes, fix primary_get_hw to use the
> correct registers.
>
> Signed-off-by: Maarten Lankhorst 
> Cc: sta...@vger.kernel.org #v4.2+

SKL/BXT have only preliminary support in v4.2, so I'm not queuing
SKL/BXT specific fixes there. v4.3 is another matter.

BR,
Jani.



> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 854896e4794e..92c96c34085d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15097,7 +15097,10 @@ static bool primary_get_hw_state(struct intel_plane 
> *plane)
>  {
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  
> - return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
> + if (INTEL_INFO(dev_priv)->gen >= 9)
> + return I915_READ(PLANE_CTL(plane->plane, 0)) & PLANE_CTL_ENABLE;
> + else
> + return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
>  }
>  
>  /* FIXME read out full plane state for all planes */
> -- 
> 2.1.0
>
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add primary plane to mask if it's visible

[Jani Nikula]

On Wed, 23 Sep 2015, Maarten Lankhorst  
wrote:
> This fixes the warnings like
>
> "plane A assertion failure, should be disabled but not"
>
> that on the initial modeset during boot. This can happen if
> the primary plane is enabled by the firmware, but inheriting
> it fails because the DMAR is active or for other reasons.
>
> Most likely caused by
>
> commit 36750f284b3a4f19b304fda1bb7d6e9e1275ea8d
> Author: Maarten Lankhorst 
> Date:   Mon Jun 1 12:49:54 2015 +0200
>
> drm/i915: update plane state during init
>
> Reported-by: Andreas Reis 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91429
> Reported-and-tested-by: Emil Renner Berthing 
> Tested-by: Andreas Reis 
> Reviewed-by: Daniel Vetter 
> Signed-off-by: Jani Nikula 

Daniel, this one is for you. Another version of this is already
upstream:

commit 721a09f7393de6c28a07516dccd654c6e995944a
Author: Maarten Lankhorst 
Date:   Tue Sep 15 14:28:54 2015 +0200

drm/i915: Add primary plane to mask if it's visible



> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index c5366b9ff809..854896e4794e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15103,11 +15103,15 @@ static bool primary_get_hw_state(struct intel_plane 
> *plane)
>  /* FIXME read out full plane state for all planes */
>  static void readout_plane_state(struct intel_crtc *crtc)
>  {
> + struct drm_plane *primary = crtc->base.primary;
>   struct intel_plane_state *plane_state =
> - to_intel_plane_state(crtc->base.primary->state);
> + to_intel_plane_state(primary->state);
>  
>   plane_state->visible =
> - primary_get_hw_state(to_intel_plane(crtc->base.primary));
> + primary_get_hw_state(to_intel_plane(primary));
> +
> + if (plane_state->visible)
> + crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
>  }
>  
>  static void intel_modeset_readout_hw_state(struct drm_device *dev)
> -- 
> 2.1.0
>

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Re: [Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

[Jani Nikula]

On Fri, 25 Sep 2015, Geliang Tang  wrote:
> Leak a task reference in i915_ppgtt_info(), add put_task_struct()
> to fix it.

Introduced by

commit 1c60fef535d143860d5bf6593e24ab6417f5227c
Author: Ben Widawsky 
Date:   Fri Dec 6 14:11:30 2013 -0800

drm/i915: Dump all ppgtt


>
> Signed-off-by: Geliang Tang 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5615d3d..8797717 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2288,9 +2288,13 @@ static int i915_ppgtt_info(struct seq_file *m, void 
> *data)
>  
>   list_for_each_entry_reverse(file, >filelist, lhead) {
>   struct drm_i915_file_private *file_priv = file->driver_priv;
> + struct task_struct *task;
>  
> - seq_printf(m, "\nproc: %s\n",
> -get_pid_task(file->pid, PIDTYPE_PID)->comm);
> + task = get_pid_task(file->pid, PIDTYPE_PID);
> + if (!task)
> + return -ESRCH;
> + seq_printf(m, "\nproc: %s\n", task->comm);
> + put_task_struct(task);
>   idr_for_each(_priv->context_idr, per_file_ctx,
>(void *)(unsigned long)m);
>   }
> -- 
> 1.9.1
>
>

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[Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

[Geliang Tang]

Leak a task reference in i915_ppgtt_info(), add put_task_struct()
to fix it.

Signed-off-by: Geliang Tang 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..8797717 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2288,9 +2288,13 @@ static int i915_ppgtt_info(struct seq_file *m, void 
*data)
 
list_for_each_entry_reverse(file, >filelist, lhead) {
struct drm_i915_file_private *file_priv = file->driver_priv;
+   struct task_struct *task;
 
-   seq_printf(m, "\nproc: %s\n",
-  get_pid_task(file->pid, PIDTYPE_PID)->comm);
+   task = get_pid_task(file->pid, PIDTYPE_PID);
+   if (!task)
+   return -ESRCH;
+   seq_printf(m, "\nproc: %s\n", task->comm);
+   put_task_struct(task);
idr_for_each(_priv->context_idr, per_file_ctx,
 (void *)(unsigned long)m);
}
-- 
1.9.1


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Re: [Intel-gfx] [PATCH v2] drm/i915: Add CD and pixel clock information

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:00:32PM +0300, Mika Kahola wrote:
> This patch adds information of current and maximum CD clock
> frequency and pixel clock frequency information on 'i915_debugfs.c'.
> 
> v2:
> - combined seperate patches for current CD clock, maximum CD clock
>   and maximum pixel clock
> - space added between the frequency value and the unit
> 
> Signed-off-by: Mika Kahola 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5615d3d..3832699 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1309,6 +1309,10 @@ static int i915_frequency_info(struct seq_file *m, 
> void *unused)
>   seq_puts(m, "no P-state info available\n");
>   }
>  
> + seq_printf(m, "Current CD clock frequency: %d kHz\n", 
> dev_priv->cdclk_freq);
> + seq_printf(m, "Max CD clock frequency: %d kHz\n", 
> dev_priv->max_cdclk_freq);
> + seq_printf(m, "Max pixel clock frequency: %d kHz\n", 
> dev_priv->max_dotclk_freq);
> +
>  out:
>   intel_runtime_pm_put(dev_priv);
>   return ret;
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 10:44:44AM +0100, Tvrtko Ursulin wrote:
> 
> On 09/24/2015 05:35 PM, Ville Syrjälä wrote:
> > On Mon, Sep 21, 2015 at 10:45:34AM +0100, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin 
> >>
> >> Just adding the rotated UV plane at the end of the rotated Y plane.
> >>
> >> v2: Rebase.
> >>
> >> Signed-off-by: Tvrtko Ursulin 
> >> ---
> >>   drivers/gpu/drm/i915/i915_gem_gtt.c  | 37 
> >> ++--
> >>   drivers/gpu/drm/i915/i915_gem_gtt.h  |  3 +++
> >>   drivers/gpu/drm/i915/intel_display.c | 12 
> >>   3 files changed, 46 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> >> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index 59c934fb9230..2df9d16dcefd 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -3272,10 +3272,13 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
> >> *ggtt_view,
> >>   {
> >>struct intel_rotation_info *rot_info = _view->rotation_info;
> >>unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
> >> +  unsigned int size_pages_uv;
> >>struct sg_page_iter sg_iter;
> >>unsigned long i;
> >>dma_addr_t *page_addr_list;
> >>struct sg_table *st;
> >> +  unsigned int uv_start_page;
> >> +  struct scatterlist *sg;
> >>int ret = -ENOMEM;
> >>
> >>/* Allocate a temporary list of source pages for random access. */
> >> @@ -3284,12 +3287,18 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
> >> *ggtt_view,
> >>if (!page_addr_list)
> >>return ERR_PTR(ret);
> >>
> >> +  /* Account for UV plane with NV12. */
> >> +  if (rot_info->pixel_format == DRM_FORMAT_NV12)
> >> +  size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
> >> +  else
> >> +  size_pages_uv = 0;
> >> +
> >>/* Allocate target SG list. */
> >>st = kmalloc(sizeof(*st), GFP_KERNEL);
> >>if (!st)
> >>goto err_st_alloc;
> >>
> >> -  ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
> >> +  ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
> >>if (ret)
> >>goto err_sg_alloc;
> >>
> >> @@ -3301,15 +3310,30 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
> >> *ggtt_view,
> >>}
> >>
> >>/* Rotate the pages. */
> >> -  rotate_pages(page_addr_list, 0,
> >> +  sg = rotate_pages(page_addr_list, 0,
> >> rot_info->width_pages, rot_info->height_pages,
> >> st, NULL);
> >>
> >> +  /* Append the UV plane if NV12. */
> >> +  if (rot_info->pixel_format == DRM_FORMAT_NV12) {
> >> +  uv_start_page = size_pages;
> >> +
> >> +  /* Check for tile-row un-alignment. */
> >> +  if (offset_in_page(rot_info->uv_offset))
> >> +  uv_start_page--;
> >> +
> >> +  rotate_pages(page_addr_list, uv_start_page,
> >> +   rot_info->width_pages_uv,
> >> +   rot_info->height_pages_uv,
> >> +   st, sg);
> >> +  }
> >> +
> >>DRM_DEBUG_KMS(
> >> -"Created rotated page mapping for object size %zu 
> >> (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
> >> +"Created rotated page mapping for object size %zu 
> >> (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 
> >> 0)).\n",
> >>  obj->base.size, rot_info->pitch, rot_info->height,
> >>  rot_info->pixel_format, rot_info->width_pages,
> >> -rot_info->height_pages, size_pages);
> >> +rot_info->height_pages, size_pages + size_pages_uv,
> >> +size_pages);
> >>
> >>drm_free_large(page_addr_list);
> >>
> >> @@ -3321,10 +3345,11 @@ err_st_alloc:
> >>drm_free_large(page_addr_list);
> >>
> >>DRM_DEBUG_KMS(
> >> -"Failed to create rotated mapping for object size %zu! 
> >> (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
> >> +"Failed to create rotated mapping for object size %zu! 
> >> (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u 
> >> plane 0))\n",
> >>  obj->base.size, ret, rot_info->pitch, rot_info->height,
> >>  rot_info->pixel_format, rot_info->width_pages,
> >> -rot_info->height_pages, size_pages);
> >> +rot_info->height_pages, size_pages + size_pages_uv,
> >> +size_pages);
> >>return ERR_PTR(ret);
> >>   }
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
> >> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> >> index 82750073d5b3..197183d5c543 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> >> @@ -138,10 +138,13 @@ enum i915_ggtt_view_type {
> >>   struct intel_rotation_info {
> >>unsigned int height;
> >>unsigned int pitch;
> >> +  unsigned int uv_offset;
> >>   

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 10:56:31AM +0200, Patrik Jakobsson wrote:
> On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote:
> > > > On Wed, Sep 23, 2015 at 10:43:00AM +0200, Daniel Vetter wrote:
> > > > > On Mon, Sep 21, 2015 at 10:00:45AM +0200, Patrik Jakobsson wrote:
> > > > > > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > > > > > > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > > > > > > > We need to be able to control if DC6 is allowed or not. Much 
> > > > > > > > like
> > > > > > > > requesting power to a specific piece of the hardware we need to 
> > > > > > > > be able
> > > > > > > > to request that we don't enter DC6 during certain hw access.
> > > > > > > > 
> > > > > > > > To solve this without introducing too much infrastructure I'm 
> > > > > > > > hooking
> > > > > > > > into the power well / power domain framework. DC6 prevention is 
> > > > > > > > modeled
> > > > > > > > much like an enabled power well. Thus I'm using the terminology 
> > > > > > > > on/off
> > > > > > > > for DC states instead of enable/disable.
> > > > > > > > 
> > > > > > > > The problem that started this work is the need for DC6 to be 
> > > > > > > > disabled
> > > > > > > > when accessing DP_AUX_A during CRTC on/off. That is also fixed 
> > > > > > > > in this
> > > > > > > > patch.
> > > > > > > > 
> > > > > > > > This is posted as an RFC since DMC and DC state handling is 
> > > > > > > > being
> > > > > > > > reworked and will possibly affect the outcome of this patch. 
> > > > > > > > The patch
> > > > > > > > has known warnings.
> > > > > > > > 
> > > > > > > > Signed-off-by: Patrik Jakobsson 
> > > > > > > > 
> > > > > > > > ---
> > > > > > > >  drivers/gpu/drm/i915/intel_ddi.c|  9 +
> > > > > > > >  drivers/gpu/drm/i915/intel_drv.h|  2 +
> > > > > > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 69 
> > > > > > > > +
> > > > > > > >  3 files changed, 64 insertions(+), 16 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > > > > > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > index 4823184..c2c1ad2 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > @@ -2288,6 +2288,8 @@ static void intel_ddi_pre_enable(struct 
> > > > > > > > intel_encoder *intel_encoder)
> > > > > > > > if (type == INTEL_OUTPUT_DISPLAYPORT || type == 
> > > > > > > > INTEL_OUTPUT_EDP) {
> > > > > > > > struct intel_dp *intel_dp = 
> > > > > > > > enc_to_intel_dp(encoder);
> > > > > > > >  
> > > > > > > > +   intel_display_power_get(dev_priv, 
> > > > > > > > POWER_DOMAIN_AUX_A);
> > > > > > > > +
> > > > > > > 
> > > > > > > These I think shouldn't be necessary with my
> > > > > > > intel_display_port_aux_power_domain() stuff since 
> > > > > > > intel_dp_aux_ch() will
> > > > > > > itself grab the appropriate power domain.
> > > > > > > 
> > > > > > > That's of course assuming that AUX is the only reason why we need 
> > > > > > > to
> > > > > > > keep DC6 disabled here.
> > > > > > > 
> > > > > > 
> > > > > > The upside with having get/put around bigger aux transfers is that 
> > > > > > we don't get
> > > > > > tons of enable/disable lines in the log. My vote is that we keep 
> > > > > > this but also
> > > > > > have your fine-grained get/puts.
> > > > > 
> > > > > Imo the correct solution to avoid this is by adding a slight bit of
> > > > > hystersis to the power well code. Which means that yes, we reinvent
> > > > > another feature of the core power_domain code in our home-grown 
> > > > > solution -
> > > > > I hate it when my years old predictions come true ;-)
> > > > > 
> > > > > Sprinkling higher-level get/put calls all over the place is imo just
> > > > > leaking the abstraction, which isn't good.
> > > > > -Daniel
> > > > 
> > > > With Ville's patches the problem is not as bad as I first thought. We 
> > > > can add
> > > > hysteresis later if needed.
> > > > 
> > > > -Patrik
> > > 
> > > So I discovered that we cannot have DC5 and DC6 as seperate power wells 
> > > since
> > > they are mutually exclusive. As Ville pointed out we don't use DC5 for 
> > > anything
> > > so we could get away for now with just DC6 as a power well.
> > > 
> > > As I see it there are three ways to go about this:
> > > 
> > > A. Add AUX A to Power well 2.
> > > This would power up PW2 during DP Aux A even though we don't need it but 
> > > since
> > > we get the side effect of DC6 being disabled it should work.
> > > 
> > > B. Add DC6 off as a power well and remove DC5 off.
> > > Fairly straight forward but assumes we don't need DC5 control.
> > > 
> > > C. Add multi-state support for the DC power well.
> 

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

[Patrik Jakobsson]

On Fri, Sep 25, 2015 at 12:41:42PM +0300, Imre Deak wrote:
> On pe, 2015-09-25 at 10:56 +0200, Patrik Jakobsson wrote:
> > On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote:
> > > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote:
> > > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote:
> > > > > On Wed, Sep 23, 2015 at 10:43:00AM +0200, Daniel Vetter wrote:
> > > > > > On Mon, Sep 21, 2015 at 10:00:45AM +0200, Patrik Jakobsson wrote:
> > > > > > > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson 
> > > > > > > > wrote:
> > > > > > > > > We need to be able to control if DC6 is allowed or not. Much 
> > > > > > > > > like
> > > > > > > > > requesting power to a specific piece of the hardware we need 
> > > > > > > > > to be able
> > > > > > > > > to request that we don't enter DC6 during certain hw access.
> > > > > > > > > 
> > > > > > > > > To solve this without introducing too much infrastructure I'm 
> > > > > > > > > hooking
> > > > > > > > > into the power well / power domain framework. DC6 prevention 
> > > > > > > > > is modeled
> > > > > > > > > much like an enabled power well. Thus I'm using the 
> > > > > > > > > terminology on/off
> > > > > > > > > for DC states instead of enable/disable.
> > > > > > > > > 
> > > > > > > > > The problem that started this work is the need for DC6 to be 
> > > > > > > > > disabled
> > > > > > > > > when accessing DP_AUX_A during CRTC on/off. That is also 
> > > > > > > > > fixed in this
> > > > > > > > > patch.
> > > > > > > > > 
> > > > > > > > > This is posted as an RFC since DMC and DC state handling is 
> > > > > > > > > being
> > > > > > > > > reworked and will possibly affect the outcome of this patch. 
> > > > > > > > > The patch
> > > > > > > > > has known warnings.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Patrik Jakobsson 
> > > > > > > > > 
> > > > > > > > > ---
> > > > > > > > >  drivers/gpu/drm/i915/intel_ddi.c|  9 +
> > > > > > > > >  drivers/gpu/drm/i915/intel_drv.h|  2 +
> > > > > > > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 69 
> > > > > > > > > +
> > > > > > > > >  3 files changed, 64 insertions(+), 16 deletions(-)
> > > > > > > > > 
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > > > > > > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > > index 4823184..c2c1ad2 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > > @@ -2288,6 +2288,8 @@ static void intel_ddi_pre_enable(struct 
> > > > > > > > > intel_encoder *intel_encoder)
> > > > > > > > >   if (type == INTEL_OUTPUT_DISPLAYPORT || type == 
> > > > > > > > > INTEL_OUTPUT_EDP) {
> > > > > > > > >   struct intel_dp *intel_dp = 
> > > > > > > > > enc_to_intel_dp(encoder);
> > > > > > > > >  
> > > > > > > > > + intel_display_power_get(dev_priv, 
> > > > > > > > > POWER_DOMAIN_AUX_A);
> > > > > > > > > +
> > > > > > > > 
> > > > > > > > These I think shouldn't be necessary with my
> > > > > > > > intel_display_port_aux_power_domain() stuff since 
> > > > > > > > intel_dp_aux_ch() will
> > > > > > > > itself grab the appropriate power domain.
> > > > > > > > 
> > > > > > > > That's of course assuming that AUX is the only reason why we 
> > > > > > > > need to
> > > > > > > > keep DC6 disabled here.
> > > > > > > > 
> > > > > > > 
> > > > > > > The upside with having get/put around bigger aux transfers is 
> > > > > > > that we don't get
> > > > > > > tons of enable/disable lines in the log. My vote is that we keep 
> > > > > > > this but also
> > > > > > > have your fine-grained get/puts.
> > > > > > 
> > > > > > Imo the correct solution to avoid this is by adding a slight bit of
> > > > > > hystersis to the power well code. Which means that yes, we reinvent
> > > > > > another feature of the core power_domain code in our home-grown 
> > > > > > solution -
> > > > > > I hate it when my years old predictions come true ;-)
> > > > > > 
> > > > > > Sprinkling higher-level get/put calls all over the place is imo just
> > > > > > leaking the abstraction, which isn't good.
> > > > > > -Daniel
> > > > > 
> > > > > With Ville's patches the problem is not as bad as I first thought. We 
> > > > > can add
> > > > > hysteresis later if needed.
> > > > > 
> > > > > -Patrik
> > > > 
> > > > So I discovered that we cannot have DC5 and DC6 as seperate power wells 
> > > > since
> > > > they are mutually exclusive. As Ville pointed out we don't use DC5 for 
> > > > anything
> > > > so we could get away for now with just DC6 as a power well.
> > > > 
> > > > As I see it there are three ways to go about this:
> > > > 
> > > > A. Add AUX A to Power well 2.
> > > > This would power up PW2 during DP Aux A even though we don't need it 
> > > > but since

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 09:34:13PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
> > Dropping it as it is for pre-production stepping.
> > 
> > Signed-off-by: Arun Siluvery 
> > ---
> >  drivers/gpu/drm/i915/intel_lrc.c|  5 ++---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
> >  2 files changed, 13 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 256167b..e3baffd 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs 
> > *ring,
> > struct drm_device *dev = ring->dev;
> > uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
> >  
> > -   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> > -   if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> > -   (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> > +   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > +   if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
> > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> > wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> > wa_ctx_emit(batch, index,
> 
> Looks like we have some duplicated defines and whatnot. See
> WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
> Maybe you can figure out why we have the same stuff in two places?

Oh and there's also 
WaDisablePixelMaskBasedCammingInRcpbe
which we seem to be missing...

> 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 963b3ca..d5fdbc8 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct 
> > intel_engine_cs *ring)
> >   GEN9_DG_MIRROR_FIX_ENABLE);
> > }
> >  
> > -   if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> > -   (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
> > -   /* 
> > WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> > -   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > - GEN9_RHWO_OPTIMIZATION_DISABLE);
> > -   /*
> > -* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
> > set
> > -* but we do that in per ctx batchbuffer as there is an issue
> > -* with this register not getting restored on ctx restore
> > -*/
> > -   }
> > -
> > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
> > IS_BROXTON(dev)) {
> > /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
> > @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct 
> > intel_engine_cs *ring)
> > GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> > }
> >  
> > +   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > +   if (INTEL_REVID(dev) < BXT_REVID_B0) {
> > +   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > + GEN9_RHWO_OPTIMIZATION_DISABLE);
> > +   /*
> > +* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
> > set
> > +* but we do that in per ctx batchbuffer as there is an issue
> > +* with this register not getting restored on ctx restore
> > +*/
> > +   }
> > +
> 
> 
> > return 0;
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> ___
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Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Arun Siluvery]

On 25/09/2015 19:34, Ville Syrjälä wrote:

On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:

Dropping it as it is for pre-production stepping.

Signed-off-by: Arun Siluvery 
---
  drivers/gpu/drm/i915/intel_lrc.c|  5 ++---
  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
  2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 256167b..e3baffd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs 
*ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

-   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-   if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
-   (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
+   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+   if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,


Looks like we have some duplicated defines and whatnot. See
WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
Maybe you can figure out why we have the same stuff in two places?
Yes I noticed that and I was not completely sure about 
WaDisableMaskBasedCammingInRCC. I will check again and update accordingly.


regards
Arun




diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 963b3ca..d5fdbc8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*ring)
  GEN9_DG_MIRROR_FIX_ENABLE);
}

-   if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
-   (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
-   /* 
WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
- GEN9_RHWO_OPTIMIZATION_DISABLE);
-   /*
-* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
set
-* but we do that in per ctx batchbuffer as there is an issue
-* with this register not getting restored on ctx restore
-*/
-   }
-
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
IS_BROXTON(dev)) {
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
@@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*ring)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}

+   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+   if (INTEL_REVID(dev) < BXT_REVID_B0) {
+   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+ GEN9_RHWO_OPTIMIZATION_DISABLE);
+   /*
+* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
set
+* but we do that in per ctx batchbuffer as there is an issue
+* with this register not getting restored on ctx restore
+*/
+   }
+




return 0;
  }

--
1.9.1

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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Add GuC css header parser

[Yu Dai]

On 09/25/2015 07:45 AM, Jani Nikula wrote:

On Thu, 24 Sep 2015, Yu Dai  wrote:
> On 09/24/2015 12:04 PM, Dave Gordon wrote:
>> On 24/09/15 19:34, Yu Dai wrote:
>> >
>> >
>> > On 09/24/2015 07:23 AM, Dave Gordon wrote:
>> >> On 22/09/15 21:48, yu@intel.com wrote:
>> >> > From: Alex Dai 
>> >> >
>> >> > By using information from GuC css header, we can eliminate some
>> >> > hard code w.r.t size of some components of firmware.
>> >> >
>> >> > v2: Add indent into DOC to make fixed-width format rather than
>> >> > change the tmpl.
>> >> >
>> >> > v1: 1) guc_css_header is defined as __packed now
>> >> >  2) Add and correct GuC related topics in kernel/Doc
>> >> >
>> >> > Signed-off-by: Alex Dai 
>> >> > ---
>> >> >   Documentation/DocBook/drm.tmpl  |   9 ++-
>> >> >   drivers/gpu/drm/i915/intel_guc.h|   2 +-
>> >> >   drivers/gpu/drm/i915/intel_guc_fwif.h   |  36 +++
>> >> >   drivers/gpu/drm/i915/intel_guc_loader.c | 107
>> >> ++--
>> >> >   4 files changed, 117 insertions(+), 37 deletions(-)
>> >> >
>> >> > diff --git a/Documentation/DocBook/drm.tmpl
>> >> b/Documentation/DocBook/drm.tmpl
>> >> > index 66bc646..116332f 100644
>> >> > --- a/Documentation/DocBook/drm.tmpl
>> >> > +++ b/Documentation/DocBook/drm.tmpl
>> >> > @@ -4155,14 +4155,19 @@ int num_ioctls;
>> >> > GuC-based Command Submission
>> >> > 
../linux-image-4.3.0-rc2-dsg-11022-g9765caf-dsg-intel-nightly_4.3.0-rc2-dsg-11022-g9765caf-dsg-intel-nightly-7_amd64.deb
>> >> >   GuC
>> >> > -!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader
>> >> > +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC
>> >> >   !Idrivers/gpu/drm/i915/intel_guc_loader.c
>> >> > 
>> >> > 
>> >> >   GuC Client
>> >> > -!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command
>> >> submissison
>> >> > +!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC Client
>> >> >   !Idrivers/gpu/drm/i915/i915_guc_submission.c
>> >> > 
>> >> > +  
>> >> > +GuC Firmware Layout
>> >> > +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC Firmware Layout
>> >> > +!Idrivers/gpu/drm/i915/intel_guc_loader.c
>> >> > +  
>> >> >   
>> >> >
>> >> >   
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc.h
>> >> b/drivers/gpu/drm/i915/intel_guc.h
>> >> > index 4ec2d27..e1389fc 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc.h
>> >> > +++ b/drivers/gpu/drm/i915/intel_guc.h
>> >> > @@ -71,6 +71,7 @@ struct intel_guc_fw {
>> >> >   struct drm_i915_gem_object *guc_fw_obj;
>> >> >   enum intel_guc_fw_statusguc_fw_fetch_status;
>> >> >   enum intel_guc_fw_statusguc_fw_load_status;
>> >> > +struct guc_css_headerguc_fw_header;
>> >> >
>> >> >   uint16_tguc_fw_major_wanted;
>> >> >   uint16_tguc_fw_minor_wanted;
>> >> > @@ -80,7 +81,6 @@ struct intel_guc_fw {
>> >> >
>> >> >   struct intel_guc {
>> >> >   struct intel_guc_fw guc_fw;
>> >> > -
>> >> >   uint32_t log_flags;
>> >> >   struct drm_i915_gem_object *log_obj;
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > index e1f47ba..006dc0d 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> >> > @@ -122,6 +122,42 @@
>> >> >
>> >> >   #define GUC_CTL_MAX_DWORDS(GUC_CTL_RSRVD + 1)
>> >> >
>> >> > +struct guc_css_header {
>> >> > +uint32_t module_type;
>> >> > +uint32_t header_len; /* header length plus size of all other
>> >> keys */
>> >> > +uint32_t header_version;
>> >> > +uint32_t module_id;
>> >> > +uint32_t module_vendor;
>> >> > +union {
>> >> > +struct {
>> >> > +uint8_t day;
>> >> > +uint8_t month;
>> >> > +uint16_t year;
>> >> > +};
>> >> > +uint32_t date;
>> >> > +};
>> >> > +uint32_t size; /* uCode size plus header_len */
>> >> > +uint32_t key_size;
>> >> > +uint32_t modulus_size;
>> >> > +uint32_t exponent_size;
>> >> > +union {
>> >> > +struct {
>> >> > +uint8_t hour;
>> >> > +uint8_t min;
>> >> > +uint16_t sec;
>> >> > +};
>> >> > +uint32_t time;
>> >> > +};
>> >> > +
>> >> > +char username[8];
>> >> > +char buildnumber[12];
>> >> > +uint32_t device_id;
>> >> > +uint32_t guc_sw_version;
>> >> > +uint32_t prod_preprod_fw;
>> >> > +uint32_t reserved[12];
>> >> > +uint32_t header_info;
>> >> > +} __packed;
>> >> > +
>> >> >   struct guc_doorbell_info {
>> >> >   u32 db_status;
>> >> >   u32 cookie;
>> >> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> > index 40241f3..a6703b4 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> >> > +++ 

Re: [Intel-gfx] [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote:
> Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no 
> name
> as they are part of same register. This will save an entry in WA array.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ad16ef4..963b3ca 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs 
> *ring)
>   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> - /* Syncing dependencies between camera and graphics:skl,bxt */
> - WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> + /* WA: Syncing dependencies between camera and graphics:skl,bxt */
> + /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> + tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
> + if (IS_SKYLAKE(dev) ||
> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> + tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
> + }
> + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);

I really dislike these platform+stepping checks in the shared codepath.
If there's any difference between the platforms, IMO the w/a should go into
the per-platform function.

>  
>   if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
>   INTEL_REVID(dev) == SKL_REVID_B0)) ||
> @@ -967,13 +972,6 @@ static int gen9_init_workarounds(struct intel_engine_cs 
> *ring)
>   tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
>   WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>  
> - /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> - if (IS_SKYLAKE(dev) ||
> - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> - WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -   GEN8_SAMPLER_POWER_BYPASS_DIS);
> - }
> -
>   /* WaDisableSTUnitPowerOptimization:skl,bxt */
>   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:42PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery 

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index be39f7ad..a6ee0d3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -77,12 +77,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  
>   if (INTEL_REVID(dev) <= SKL_REVID_B0) {
>   /*
> -  * WaDisableSDEUnitClockGating:skl
>* WaSetGAPSunitClckGateDisable:skl
>*/
>   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
> -GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);

Reviewed-by: Ville Syrjälä 

Not that BXT has the same with another name
WaSetSDEunitClckGatingDisable. We seem to have the "wrong" name in the
code for BXT. Also it could apparently use an A0 check.

>  
>   /* WaDisableVFUnitClockGating:skl */
>   I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:44PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping, also removed
> bit definition in i915_reg.h as it is not used anywhere else.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 -
>  drivers/gpu/drm/i915/intel_pm.c | 6 --
>  2 files changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ef3d71f..b510fdc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6688,7 +6688,6 @@ enum skl_disp_power_wells {
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE  (1 << 7)
>  
>  #define GEN6_UCGCTL2 0x9404
> -# define GEN6_VFUNIT_CLOCK_GATE_DISABLE  (1 << 31)

Again, I would keep the define.

>  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
>  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
>  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 65c60bc..88acb3e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -75,12 +75,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  
>   gen9_init_clock_gating(dev);
>  
> - if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> - /* WaDisableVFUnitClockGating:skl */
> - I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> -GEN6_VFUNIT_CLOCK_GATE_DISABLE);
> - }
> -

Reviewed-by: Ville Syrjälä 

>   if (INTEL_REVID(dev) <= SKL_REVID_D0) {
>   /* WaDisableHDCInvalidation:skl */
>   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> -- 
> 1.9.1
> 
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[Intel-gfx] [PATCH] drm/i915/guc: Add host2guc notification for suspend and resume

[yu . dai]

From: Alex Dai 

Add host2guc interfaces to nofigy GuC power state changes when
enter or resume from power saving state.

v2: Add GuC suspend/resume to runtime suspend/resume too

v1: Change to a more flexible way when fill host to GuC scratch
data in order to remove hard coding.

Signed-off-by: Alex Dai 
---
 drivers/gpu/drm/i915/i915_drv.c|  5 +++
 drivers/gpu/drm/i915/i915_gem.c|  2 ++
 drivers/gpu/drm/i915/i915_guc_submission.c | 50 ++
 drivers/gpu/drm/i915/intel_guc.h   |  2 ++
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  8 +
 drivers/gpu/drm/i915/intel_guc_loader.c|  4 ++-
 6 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6d7a69..842eb13 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -737,6 +737,8 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
 
+   intel_guc_resume(dev);
+
intel_modeset_init_hw(dev);
 
spin_lock_irq(_priv->irq_lock);
@@ -1476,6 +1478,7 @@ static int intel_runtime_suspend(struct device *device)
i915_gem_release_all_mmaps(dev_priv);
mutex_unlock(>struct_mutex);
 
+   intel_guc_suspend(dev);
intel_suspend_gt_powersave(dev);
intel_runtime_pm_disable_interrupts(dev_priv);
 
@@ -1535,6 +1538,8 @@ static int intel_runtime_resume(struct device *device)
intel_opregion_notify_adapter(dev, PCI_D0);
dev_priv->pm.suspended = false;
 
+   intel_guc_resume(dev);
+
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf5ef7a..679ed55 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4460,6 +4460,8 @@ i915_gem_suspend(struct drm_device *dev)
i915_gem_stop_ringbuffers(dev);
mutex_unlock(>struct_mutex);
 
+   intel_guc_suspend(dev);
+
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->mm.retire_work);
flush_delayed_work(_priv->mm.idle_work);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 792d0b9..38b6ef4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -914,3 +914,53 @@ void i915_guc_submission_fini(struct drm_device *dev)
gem_release_guc_obj(guc->ctx_pool_obj);
guc->ctx_pool_obj = NULL;
 }
+
+/**
+ * intel_guc_suspend() - notify GuC entering suspend state
+ * @dev:   drm device
+ */
+int intel_guc_suspend(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_guc *guc = _priv->guc;
+   struct intel_context *ctx;
+   u32 data[3];
+
+   if (!i915.enable_guc_submission)
+   return 0;
+
+   ctx = dev_priv->ring[RCS].default_context;
+
+   data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
+   /* any value greater than GUC_POWER_D0 */
+   data[1] = GUC_POWER_D1;
+   /* first page is shared data with GuC */
+   data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
+
+   return host2guc_action(guc, data, ARRAY_SIZE(data));
+}
+
+
+/**
+ * intel_guc_resume() - notify GuC resuming from suspend state
+ * @dev:   drm device
+ */
+int intel_guc_resume(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_guc *guc = _priv->guc;
+   struct intel_context *ctx;
+   u32 data[3];
+
+   if (!i915.enable_guc_submission)
+   return 0;
+
+   ctx = dev_priv->ring[RCS].default_context;
+
+   data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
+   data[1] = GUC_POWER_D0;
+   /* first page is shared data with GuC */
+   data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
+
+   return host2guc_action(guc, data, ARRAY_SIZE(data));
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 55c9bf8..39cf460 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -116,6 +116,8 @@ extern void intel_guc_ucode_init(struct drm_device *dev);
 extern int intel_guc_ucode_load(struct drm_device *dev);
 extern void intel_guc_ucode_fini(struct drm_device *dev);
 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern int intel_guc_suspend(struct drm_device *dev);
+extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index cd94075..4029478 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -290,12 +290,20 @@ 

[Intel-gfx] [PATCH] drm/i915/guc: Media domain bit needed when notify GuC rc6 state

[yu . dai]

From: Alex Dai 

GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.

v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating

v1: Add parameters definition to avoid magic value

Signed-off-by: Alex Dai 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 13 +++--
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  3 +++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 38b6ef4..036b42b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -155,12 +155,21 @@ static int host2guc_sample_forcewake(struct intel_guc 
*guc,
 struct i915_guc_client *client)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   struct drm_device *dev = dev_priv->dev;
u32 data[2];
 
data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
-   data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
+   /* WaRsDisableCoarsePowerGating:skl,bxt */
+   if (!intel_enable_rc6(dev_priv->dev) ||
+   (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+   (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) ||
+   (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+   data[1] = 0;
+   else
+   /* bit 0 and 1 are for Render and Media domain separately */
+   data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 
-   return host2guc_action(guc, data, 2);
+   return host2guc_action(guc, data, ARRAY_SIZE(data));
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 4029478..04ca777 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -296,6 +296,9 @@ struct guc_context_desc {
 #define GUC_POWER_D2   3
 #define GUC_POWER_D3   4
 
+#define GUC_FORCEWAKE_RENDER   (1 << 0)
+#define GUC_FORCEWAKE_MEDIA(1 << 1)
+
 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
 enum host2guc_action {
HOST2GUC_ACTION_DEFAULT = 0x0,
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/guc: Fix a bug in GuC status check

[yu . dai]

From: Alex Dai 

Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
status is a reliable readiness flag only when resuming from RC6.
This fix a racing issue that allocation of doorbell fails whilst
GuC init is not finished.

v2: Split the status check into two parts for better reading and
understanding the code.

Signed-off-by: Alex Dai 
---
 drivers/gpu/drm/i915/i915_guc_reg.h |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 11 +--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 9d79a6b..b355661 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -37,6 +37,7 @@
 #define   GS_UKERNEL_READY   (0xF0 << GS_UKERNEL_SHIFT)
 #define   GS_MIA_SHIFT 16
 #define   GS_MIA_MASK(0x07 << GS_MIA_SHIFT)
+#define   GS_MIA_CORE_STATE  (1 << GS_MIA_SHIFT)
 
 #define SOFT_SCRATCH(n)(0xc180 + ((n) * 4))
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index e0601cc..98d3ce7 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -209,9 +209,16 @@ static inline bool guc_ucode_response(struct 
drm_i915_private *dev_priv,
  u32 *status)
 {
u32 val = I915_READ(GUC_STATUS);
+   u32 uk_val = val & GS_UKERNEL_MASK;
*status = val;
-   return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
-   (val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
+
+   /* If resuming from RC6, look for LAPIC_DONE */
+   if (val & GS_MIA_CORE_STATE)
+   if (uk_val == GS_UKERNEL_LAPIC_DONE)
+   return true;
+
+   /* Otherwise just check whether the uKernel is READY */
+   return uk_val == GS_UKERNEL_READY;
 }
 
 /*
-- 
1.9.1

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[Intel-gfx] [PATCH v2 02/10] drm/i915/gen8: Move INSTPM WA to common function

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 10f9ea0..4f3942f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -802,6 +802,10 @@ static int wa_add(struct drm_i915_private *dev_priv,
 
 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 {
+   struct drm_device *dev = ring->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
return 0;
 }
@@ -816,8 +820,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:bdw */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
@@ -887,8 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery 

Series lgtm, so
Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++--
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1e60aa0..35afe73 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
> *ring)
>* invalidation occurs during a PSD flush.
>*/
>   /* WaForceEnableNonCoherent:bdw,chv */
> + /* WaHdcDisableFetchWhenMasked:bdw,chv */
>   WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +   HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> HDC_FORCE_NON_COHERENT);
>  
>   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> @@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   WA_SET_BIT_MASKED(HDC_CHICKEN0,
> /* WaForceContextSaveRestoreNonCoherent:bdw */
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> -   /* WaHdcDisableFetchWhenMasked:bdw */
> -   HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>  
> @@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
> *ring)
>   /* WaDisableThreadStallDopClockGating:chv */
>   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>  
> - /* WaHdcDisableFetchWhenMasked:chv */
> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
> -   HDC_DONOT_FETCH_MEM_WHEN_MASKED);
> -
>   /* Improve HiZ throughput on CHV. */
>   WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>  
> -- 
> 1.9.1

-- 
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Re: [Intel-gfx] [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:39PM +0100, Arun Siluvery wrote:
> The implementation for this WA is same as 
> WaSetHdcUnitClockGatingDisableInUcgctl6.
> Both of them are for BXT:A0 except that 
> WaSetHdcUnitClockGatingDisableInUcgctl6
> is applicable only when either SS0 or SS2 is active but if we apply the 
> former WA
> then the latter one also gets applied irrespective of which SS is enabled.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 ++-
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 093a5e4..c73d37d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device 
> *dev)
>   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
> - /*
> -  * FIXME:
> -  * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> + /* WaSetHDCunitClckGatingDisable:bxt */
> + /* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
> + /* The implementation is same for both of these WA except that
> +  * WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when
> +  * either SS0 or SS2 is active but if we apply the first one then the
> +  * second one also gets applied irrespective of which SS is enabled.
>*/
> - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> + if (INTEL_REVID(dev) == BXT_REVID_A0) {
> + I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
> +   
> GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
> + }

Again BSpec seems confused. It says this applies to BXT from A0, and SKL
from C0. The register description only says to do it for 3x6 BXT, and
w/a db says both workarounds are for BXT until A0. Quite a nice mess.

>  
>   if (INTEL_REVID(dev) == BXT_REVID_A0) {
>   /*
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote:
> Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
> an entry in WA array.
> 
> Signed-off-by: Arun Siluvery 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 6671800..ad16ef4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs 
> *ring)
>   }
>  
>   /* Wa4x4STCOptimizationDisable:skl,bxt */
> - WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> -
>   /* WaDisablePartialResolveInVc:skl,bxt */
> - WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> + WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
> +  GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
>   /* WaCcsTlbPrefetchDisable:skl,bxt */
>   WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:35PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdff606..6671800 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1026,10 +1026,13 @@ static int skl_tune_iz_hashing(struct intel_engine_cs 
> *ring)
>  
>  static int skl_init_workarounds(struct intel_engine_cs *ring)
>  {
> + int ret;
>   struct drm_device *dev = ring->dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>  
> - gen9_init_workarounds(ring);
> + ret = gen9_init_workarounds(ring);
> + if (ret)
> + return ret;
>  
>   /* WaDisablePowerCompilerClockGating:skl */
>   if (INTEL_REVID(dev) == SKL_REVID_B0)
> @@ -1066,10 +1069,13 @@ static int skl_init_workarounds(struct 
> intel_engine_cs *ring)
>  
>  static int bxt_init_workarounds(struct intel_engine_cs *ring)
>  {
> + int ret;
>   struct drm_device *dev = ring->dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>  
> - gen9_init_workarounds(ring);
> + ret = gen9_init_workarounds(ring);
> + if (ret)
> + return ret;
>  
>   /* WaDisableThreadStallDopClockGating:bxt */
>   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Detect virtual south bridge

[Jesse Barnes]

On 09/25/2015 08:31 AM, Jesse Barnes wrote:
> On 09/24/2015 08:41 PM, Tian, Kevin wrote:
>>> From: Jesse Barnes [mailto:jbar...@virtuousgeek.org]
>>> Sent: Friday, September 25, 2015 12:41 AM
>>>
>>> On 08/28/2015 05:10 AM, robert.beck...@intel.com wrote:
 From: Robert Beckett 

 Virtualized systems often use a virtual P2X4 south bridge.
 Detect this in intel_detect_pch and make a best guess as to which PCH
 we should be using.

 This was seen on vmware esxi hypervisor. When passing the graphics device
 through to a guest, it can not pass through the PCH. Instead it simulates
 a P2X4 southbridge.

 Signed-off-by: Robert Beckett 
 ---
  drivers/gpu/drm/i915/i915_drv.c |   30
>>> ++
  drivers/gpu/drm/i915/i915_drv.h |1 +
  2 files changed, 31 insertions(+)

 diff --git a/drivers/gpu/drm/i915/i915_drv.c 
 b/drivers/gpu/drm/i915/i915_drv.c
 index ce3bd0c..8e158b3 100644
 --- a/drivers/gpu/drm/i915/i915_drv.c
 +++ b/drivers/gpu/drm/i915/i915_drv.c
 @@ -443,6 +443,34 @@ static const struct pci_device_id pciidlist[] = { 
 /* aka
>>> */

  MODULE_DEVICE_TABLE(pci, pciidlist);

 +static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 +{
 +  enum intel_pch ret = PCH_NOP;
 +
 +  /*
 +   * In a virtualized passthrough environment we can be in a
 +   * setup where the ISA bridge is not able to be passed through.
 +   * In this case, a south bridge can be emulated and we have to
 +   * make an educated guess as to which PCH is really there.
 +   */
 +
 +  if (IS_GEN5(dev)) {
 +  ret = PCH_IBX;
 +  DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 +  } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 +  ret = PCH_CPT;
 +  DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 +  } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 +  ret = PCH_LPT;
 +  DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 +  } else if (IS_SKYLAKE(dev)) {
 +  ret = PCH_SPT;
 +  DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 +  }
 +
 +  return ret;
 +}
 +
  void intel_detect_pch(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = dev->dev_private;
 @@ -503,6 +531,8 @@ void intel_detect_pch(struct drm_device *dev)
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev));
 +  } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {
 +  dev_priv->pch_type = intel_virt_detect_pch(dev);
} else
continue;

 diff --git a/drivers/gpu/drm/i915/i915_drv.h 
 b/drivers/gpu/drm/i915/i915_drv.h
 index 8c93845..6eb0230 100644
 --- a/drivers/gpu/drm/i915/i915_drv.h
 +++ b/drivers/gpu/drm/i915/i915_drv.h
 @@ -2584,6 +2584,7 @@ struct drm_i915_cmd_table {
  #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE   0x9c00
  #define INTEL_PCH_SPT_DEVICE_ID_TYPE  0xA100
  #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE   0x9D00
 +#define INTEL_PCH_P2X_DEVICE_ID_TYPE  0x7100

  #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
  #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)

>>>
>>> Assuming Kevin is ok with this:
>>> Reviewed-by: Jesse Barnes 
>>
>> Yes, I'm OK with this change. Just one comment. Does it make
>> sense to always have the guess as the fallback, instead of only
>> for P2X? If native side is OK with this, it will remove the need 
>> to add more IDs for different hypervisors in the future...
> 
> Yeah, at this point I don't think we have mix & match cases to worry
> about, so we could guess based on the GPU type across the board.

On second thought, let's get this version merged first, then play with
assuming a bridge type in a later patch, in case that breaks something.

Jesse

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[Intel-gfx] [PATCH i-g-t] tests/pm_rc6_residency: Measure the sleep duration

[ville . syrjala]

From: Ville Syrjälä 

The code is confused about the units of CODE_TIME. The comment
says 50 microsseconds, but the actual code makes it 50
milliseconds. Avoid the whole mess by measuring the sleep
duration ourselves. Since the time measurement is taken around
the whole operation it obviously includes a bit of extra, but
at least it's much less than the fixed 50 ms.

For instance on one VLV board I now get something like this:
- Residency in rc6 or deeper state: 3002 ms (ratio to expected duration: 0.98)
+ Residency in rc6 or deeper state: 3001 ms (sleep duration 3003 ms) (ratio to 
expected duration: 1.00)
so the reported ratio is now much closer to reality.

Signed-off-by: Ville Syrjälä 
---
 tests/Makefile.am|  1 +
 tests/pm_rc6_residency.c | 35 +--
 2 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/tests/Makefile.am b/tests/Makefile.am
index 5aa480b..c4f1f01 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -85,6 +85,7 @@ gem_userptr_blits_LDADD = $(LDADD) -lpthread
 
 gem_wait_LDADD = $(LDADD) -lrt
 kms_flip_LDADD = $(LDADD) -lrt -lpthread
+pm_rc6_residency_LDADD = $(LDADD) -lrt
 
 prime_nv_test_CFLAGS = $(AM_CFLAGS) $(DRM_NOUVEAU_CFLAGS)
 prime_nv_test_LDADD = $(LDADD) $(DRM_NOUVEAU_LIBS)
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index a1e281c..2772969 100644
--- a/tests/pm_rc6_residency.c
+++ b/tests/pm_rc6_residency.c
@@ -32,10 +32,10 @@
 #include 
 #include 
 #include 
+#include 
 
 
-#define SLEEP_DURATION 3000 // in milliseconds
-#define CODE_TIME 50 // in microseconfs
+#define SLEEP_DURATION 3 /* in seconds */
 
 #define RC6_ENABLED1
 #define RC6P_ENABLED   2
@@ -46,6 +46,7 @@ struct residencies {
int media_rc6;
int rc6p;
int rc6pp;
+   int duration;
 };
 
 static unsigned int readit(const char *path)
@@ -96,14 +97,15 @@ static int read_rc6_residency(const char 
*name_of_rc6_residency)
 }
 
 static void residency_accuracy(unsigned int diff,
+  unsigned int duration,
   const char *name_of_rc6_residency)
 {
double ratio;
 
-   ratio = (double)diff / (SLEEP_DURATION + CODE_TIME);
+   ratio = (double)diff / duration;
 
-   igt_info("Residency in %s or deeper state: %u ms (ratio to expected 
duration: %.02f)\n",
-name_of_rc6_residency, diff, ratio);
+   igt_info("Residency in %s or deeper state: %u ms (sleep duration %u ms) 
(ratio to expected duration: %.02f)\n",
+name_of_rc6_residency, diff, duration, ratio);
igt_assert_f(ratio > 0.9 && ratio <= 1,
 "Sysfs RC6 residency counter is inaccurate.\n");
 }
@@ -125,12 +127,22 @@ static void read_residencies(int devid, unsigned int 
rc6_mask,
res->rc6pp = read_rc6_residency("rc6pp");
 }
 
+static unsigned long gettime_ms(void)
+{
+   struct timespec ts;
+
+   clock_gettime(CLOCK_MONOTONIC, );
+
+   return ts.tv_sec * 1000 + ts.tv_nsec / 100;
+}
+
 static void measure_residencies(int devid, unsigned int rc6_mask,
struct residencies *res)
 {
struct residencies start = { };
struct residencies end = { };
int retry;
+   unsigned long t;
 
if (!rc6_mask)
return;
@@ -147,9 +159,11 @@ static void measure_residencies(int devid, unsigned int 
rc6_mask,
 * different platforms and so fixing it up would be non-trivial.
 */
for (retry = 0; retry < 2; retry++) {
+   t = gettime_ms();
read_residencies(devid, rc6_mask, );
-   sleep(SLEEP_DURATION / 1000);
+   sleep(SLEEP_DURATION);
read_residencies(devid, rc6_mask, );
+   t = gettime_ms() - t;
 
if (end.rc6 >= start.rc6 && end.media_rc6 >= start.media_rc6 &&
end.rc6p >= start.rc6p && end.rc6pp >= start.rc6pp)
@@ -161,6 +175,7 @@ static void measure_residencies(int devid, unsigned int 
rc6_mask,
res->rc6p = end.rc6p - start.rc6p;
res->rc6pp = end.rc6pp - start.rc6pp;
res->media_rc6 = end.media_rc6 - start.media_rc6;
+   res->duration = t;
 
/*
 * For the purposes of this test case we want a given residency value
@@ -196,22 +211,22 @@ igt_main
igt_subtest("rc6-accuracy") {
igt_skip_on(!(rc6_mask & RC6_ENABLED));
 
-   residency_accuracy(res.rc6, "rc6");
+   residency_accuracy(res.rc6, res.duration, "rc6");
}
igt_subtest("media-rc6-accuracy") {
igt_skip_on(!((rc6_mask & RC6_ENABLED) &&
  (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid;
 
-   residency_accuracy(res.media_rc6, "media_rc6");
+   residency_accuracy(res.media_rc6, res.duration, "media_rc6");
}

Re: [Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ab5ac5e..093a5e4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>   /* WaDisableKillLogic:bxt,skl */
>   I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  ECOCHK_DIS_TLB);
> +
> + /* WaOCLCoherentLineFlush:skl,bxt */
> + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> + GEN8_LQSC_FLUSH_COHERENT_LINES));

According to Bspec + w/a db this should be done for BDW too (actually
BSpec shows it for BDW only?). If that's the case, then we should be
able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
someone goes and adds the DC flush to the normal post batch flush.

>  }
>  
>  static void skl_init_clock_gating(struct drm_device *dev)
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:41PM +0100, Arun Siluvery wrote:
> It is also applicable for B0.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9151a2b..be39f7ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>   gen9_init_clock_gating(dev);
>  
>   /* WaDisableSDEUnitClockGating:bxt */
> - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> + if (INTEL_REVID(dev) >= BXT_REVID_A0) {

I don't see a point in such a check. We don't have anything older than A
stepping anyway, so this will always be true.

Also BSpec says it's FROM_A0, w/a database says UNTIL_A0. Would be nice
to know which is correct...

> + I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
> +   GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
> + }
>  
>   /* WaSetHDCunitClckGatingDisable:bxt */
>   /* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
> -- 
> 1.9.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

[Michel Thierry]

On 9/25/2015 4:44 PM, Mika Kuoppala wrote:

Michel Thierry  writes:

-   ring->next_context_status_buffer = 0;
+
+   /*
+* Instead of resetting the Context Status Buffer (CSB) read pointer to
+* zero, we need to read the write pointer from hardware and use its
+* value because "this register is power context save restored".
+* Effectively, these states have been observed:
+*
+*  | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
+* BDW  | CSB regs not reset   | CSB regs reset   |
+* CHT  | CSB regs not reset   | CSB regs not reset   |
+*/
+   next_context_status_buffer_hw = I915_READ(RING_CONTEXT_STATUS_PTR(ring)) 
& 0x07;
+
+   /*
+* When the CSB registers are reset (also after power-up / gpu reset),
+* CSB write pointer is set to all 1's, which is not valid, use 0 in
+* this special case.
+*/
+   if (next_context_status_buffer_hw == 0x7)
+   next_context_status_buffer_hw = 0;



If hardware has been reset and we have b111 here, I assume
the first write will be at index zero.

If we look at the interrupt code there is while (read_pointer <
write_pointer). Initializing next status buffer to zero
would mean that you miss the first write to csb[0].

If b111 is found, I think the correct value is 5.


Correct, it needs to be set to 5. Luckily, csb[0] would always be 
Idle-to-Active, which we ignore.




-Mika




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Re: [Intel-gfx] [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:40PM +0100, Arun Siluvery wrote:
> Updated WA with the name.
> 
> Signed-off-by: Arun Siluvery 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++--
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c73d37d..9151a2b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -136,13 +136,10 @@ static void bxt_init_clock_gating(struct drm_device 
> *dev)
> 
> GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
>   }
>  
> - if (INTEL_REVID(dev) == BXT_REVID_A0) {
> - /*
> -  * Hardware specification requires this bit to be
> -  * set to 1 for A0
> -  */
> + /* WaStoreMultiplePTEenable:bxt */
> + /* This is a requirement according to Hardware specification */
> + if (INTEL_REVID(dev) == BXT_REVID_A0)
>   I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> - }
>  
>   /* WaSetClckGatingDisableMedia:bxt */
>   if (INTEL_REVID(dev) == BXT_REVID_A0) {
> -- 
> 1.9.1
> 
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[Intel-gfx] [PATCH v2 06/10] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++---
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0b545cf..a42dff9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -814,6 +814,16 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
+   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
+* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
+*  polygons in the same 8x4 pixel/sample area to be processed without
+*  stalling waiting for the earlier ones to write to Hierarchical Z
+*  buffer."
+*
+* This optimization is off by default for BDW and CHV; turn it on.
+*/
+   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+
return 0;
 }
 
@@ -848,16 +858,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
-   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
-* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
-*  polygons in the same 8x4 pixel/sample area to be processed without
-*  stalling waiting for the earlier ones to write to Hierarchical Z
-*  buffer."
-*
-* This optimization is off by default for Broadwell; turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
/* Wa4x4STCOptimizationDisable:bdw */
WA_SET_BIT_MASKED(CACHE_MODE_1,
  GEN8_4x4_STC_OPTIMIZATION_DISABLE);
@@ -900,11 +900,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
  HDC_FORCE_NON_COHERENT |
  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
-   /* According to the CACHE_MODE_0 default value documentation, some
-* CHV platforms disable this optimization by default.  Turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
/* Wa4x4STCOptimizationDisable:chv */
WA_SET_BIT_MASKED(CACHE_MODE_1,
  GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-- 
1.9.1

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[Intel-gfx] [PATCH v2 08/10] drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++--
 1 file changed, 12 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1b12584..97f9cec 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -827,6 +827,18 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
/* Wa4x4STCOptimizationDisable:bdw,chv */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+   /*
+* BSpec recommends 8x4 when MSAA is used,
+* however in practice 16x4 seems fastest.
+*
+* Note that PS/WM thread counts depend on the WIZ hashing
+* disable bit, which we don't touch here, but it's good
+* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+*/
+   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+   GEN6_WIZ_HASHING_MASK,
+   GEN6_WIZ_HASHING_16x4);
+
return 0;
 }
 
@@ -861,18 +873,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
-   /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
-   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
-   GEN6_WIZ_HASHING_MASK,
-   GEN6_WIZ_HASHING_16x4);
-
return 0;
 }
 
@@ -902,18 +902,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-   /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
-   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
-   GEN6_WIZ_HASHING_MASK,
-   GEN6_WIZ_HASHING_16x4);
-
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH v2 01/10] drm/i915/gen8: Add gen8_init_workarounds for common WA

[Arun Siluvery]

WA in this function should be ordered based on register address.
The following order is suggested (Ville),

instpm
mi_mode
row chicken
half slice chicken
common slice chicken
hdc chicken
cache_mode_0
cache_mode_1
gt_mode

Cc: Ville Syrjälä 
Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16a4ead..10f9ea0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -800,11 +800,22 @@ static int wa_add(struct drm_i915_private *dev_priv,
 
 #define WA_WRITE(addr, val) WA_REG(addr, 0x, val)
 
+static int gen8_init_workarounds(struct intel_engine_cs *ring)
+{
+
+   return 0;
+}
+
 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
+   ret = gen8_init_workarounds(ring);
+   if (ret)
+   return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
/* WaDisableAsyncFlipPerfMode:bdw */
@@ -868,9 +879,14 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
 
 static int chv_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
+   ret = gen8_init_workarounds(ring);
+   if (ret)
+   return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
/* WaDisableAsyncFlipPerfMode:chv */
-- 
1.9.1

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[Intel-gfx] [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d8fa9d1..0b545cf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -827,9 +827,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
-
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  DOP_CLOCK_GATING_DISABLE);
-- 
1.9.1

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[Intel-gfx] [PATCH v2 00/10] Gen8 WA cleanup patches

[Arun Siluvery]

Add gen8_init_workarounds() and initialize common WA in this func.

v2: drop pre-production WA and order them based on register as below (Ville).
instpm
mi_mode
row chicken
half slice chicken
common slice chicken
hdc chicken
cache_mode_0
cache_mode_1
gt_mode

Only the WA in gen8_init_workarounds() are reordered.

v1: http://lists.freedesktop.org/archives/intel-gfx/2015-September/076681.html

Arun Siluvery (10):
  drm/i915/gen8: Add gen8_init_workarounds for common WA
  drm/i915/gen8: Move INSTPM WA to common function
  drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn
  drm/i915/gen8: Move WaDisablePartialInstShootdown to common init fn
  drm/i915/bdw: Remove WaDisableThreadStallDopClockGating
  drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common
init fn
  drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn
  drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn
  drm/i915/gen8: Move WaForceEnableNonCoherent to common init fn
  drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

 drivers/gpu/drm/i915/intel_ringbuffer.c | 98 +
 1 file changed, 38 insertions(+), 60 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1e60aa0..35afe73 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
 * invalidation occurs during a PSD flush.
 */
/* WaForceEnableNonCoherent:bdw,chv */
+   /* WaHdcDisableFetchWhenMasked:bdw,chv */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_DONOT_FETCH_MEM_WHEN_MASKED |
  HDC_FORCE_NON_COHERENT);
 
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
@@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
WA_SET_BIT_MASKED(HDC_CHICKEN0,
  /* WaForceContextSaveRestoreNonCoherent:bdw */
  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
- /* WaHdcDisableFetchWhenMasked:bdw */
- HDC_DONOT_FETCH_MEM_WHEN_MASKED |
  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
@@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 
-   /* WaHdcDisableFetchWhenMasked:chv */
-   WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_DONOT_FETCH_MEM_WHEN_MASKED);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-- 
1.9.1

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[Intel-gfx] [PATCH v2 04/10] drm/i915/gen8: Move WaDisablePartialInstShootdown to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3bc14fa..d8fa9d1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -810,6 +810,10 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
/* WaDisableAsyncFlipPerfMode:bdw,chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
+   /* WaDisablePartialInstShootdown:bdw,chv */
+   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+
return 0;
 }
 
@@ -823,11 +827,8 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
+   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
@@ -889,11 +890,8 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
+   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 
/* Use Force Non-Coherent whenever executing a 3D context. This is a
 * workaround for a possible hang in the unlikely event a TLB
-- 
1.9.1

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[Intel-gfx] [PATCH v2 03/10] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4f3942f..3bc14fa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -807,6 +807,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
 
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
+   /* WaDisableAsyncFlipPerfMode:bdw,chv */
+   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
return 0;
 }
 
@@ -820,9 +823,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisableAsyncFlipPerfMode:bdw */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -889,9 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisableAsyncFlipPerfMode:chv */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-- 
1.9.1

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[Intel-gfx] [PATCH v2 07/10] drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a42dff9..1b12584 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -824,6 +824,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
 */
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 
+   /* Wa4x4STCOptimizationDisable:bdw,chv */
+   WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
return 0;
 }
 
@@ -858,10 +861,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
-   /* Wa4x4STCOptimizationDisable:bdw */
-   WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/*
 * BSpec recommends 8x4 when MSAA is used,
 * however in practice 16x4 seems fastest.
@@ -900,10 +899,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
  HDC_FORCE_NON_COHERENT |
  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
-   /* Wa4x4STCOptimizationDisable:chv */
-   WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-- 
1.9.1

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[Intel-gfx] [PATCH v2 09/10] drm/i915/gen8: Move WaForceEnableNonCoherent to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 97f9cec..1e60aa0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -814,6 +814,14 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
+   /* Use Force Non-Coherent whenever executing a 3D context. This is a
+* workaround for for a possible hang in the unlikely event a TLB
+* invalidation occurs during a PSD flush.
+*/
+   /* WaForceEnableNonCoherent:bdw,chv */
+   WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT);
+
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 *  polygons in the same 8x4 pixel/sample area to be processed without
@@ -859,13 +867,7 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
-   /* Use Force Non-Coherent whenever executing a 3D context. This is a
-* workaround for for a possible hang in the unlikely event a TLB
-* invalidation occurs during a PSD flush.
-*/
WA_SET_BIT_MASKED(HDC_CHICKEN0,
- /* WaForceEnableNonCoherent:bdw */
- HDC_FORCE_NON_COHERENT |
  /* WaForceContextSaveRestoreNonCoherent:bdw */
  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
  /* WaHdcDisableFetchWhenMasked:bdw */
@@ -889,14 +891,8 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 
-   /* Use Force Non-Coherent whenever executing a 3D context. This is a
-* workaround for a possible hang in the unlikely event a TLB
-* invalidation occurs during a PSD flush.
-*/
-   /* WaForceEnableNonCoherent:chv */
/* WaHdcDisableFetchWhenMasked:chv */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_NON_COHERENT |
  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
/* Improve HiZ throughput on CHV. */
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:43PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping, also removed
> bit definition in i915_reg as it is not used anywhere else.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 -
>  drivers/gpu/drm/i915/intel_pm.c | 6 --
>  2 files changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 085ffa2..ef3d71f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6705,7 +6705,6 @@ enum skl_disp_power_wells {
>  #define GEN6_RSTCTL  0x9420
>  
>  #define GEN8_UCGCTL6 0x9430
> -#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE   (1<<24)
>  #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE(1<<14)
>  #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)

I would keep the bit define.

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a6ee0d3..65c60bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -76,12 +76,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
>   gen9_init_clock_gating(dev);
>  
>   if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> - /*
> -  * WaSetGAPSunitClckGateDisable:skl
> -  */
> - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
> -

Reviewed-by: Ville Syrjälä 

But again BSpec is confused. It says BXT until B0 would also need this,
whereas w/a db doesn't have it fot BXT.

>   /* WaDisableVFUnitClockGating:skl */
>   I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
>  GEN6_VFUNIT_CLOCK_GATE_DISABLE);
> -- 
> 1.9.1
> 
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-- 
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Re: [Intel-gfx] [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:46PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d5fdbc8..2a33b9d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1019,11 +1019,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
> *ring)
>   if (ret)
>   return ret;
>  
> - /* WaDisablePowerCompilerClockGating:skl */
> - if (INTEL_REVID(dev) == SKL_REVID_B0)
> - WA_SET_BIT_MASKED(HIZ_CHICKEN,
> -   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
> -

Yes. However Bspec shows this to be valid for BXT until B0. The register
description OTOH says SKL:B only, as does the w/a database. I'm too lazy
to start hsd trawling now, so maybe you can figure out what's going on there?

>   if (INTEL_REVID(dev) <= SKL_REVID_D0) {
>   /*
>*Use Force Non-Coherent whenever executing a 3D context. This
> -- 
> 1.9.1
> 
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-- 
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Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
> Dropping it as it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_lrc.c|  5 ++---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
>  2 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 256167b..e3baffd 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs 
> *ring,
>   struct drm_device *dev = ring->dev;
>   uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>  
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> - (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
>   wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>   wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
>   wa_ctx_emit(batch, index,

Looks like we have some duplicated defines and whatnot. See
WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
Maybe you can figure out why we have the same stuff in two places?

> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 963b3ca..d5fdbc8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs 
> *ring)
> GEN9_DG_MIRROR_FIX_ENABLE);
>   }
>  
> - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
> - /* 
> WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> -   GEN9_RHWO_OPTIMIZATION_DISABLE);
> - /*
> -  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
> set
> -  * but we do that in per ctx batchbuffer as there is an issue
> -  * with this register not getting restored on ctx restore
> -  */
> - }
> -
>   if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
>   IS_BROXTON(dev)) {
>   /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
> @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs 
> *ring)
>   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>   }
>  
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (INTEL_REVID(dev) < BXT_REVID_B0) {
> + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> +   GEN9_RHWO_OPTIMIZATION_DISABLE);
> + /*
> +  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
> set
> +  * but we do that in per ctx batchbuffer as there is an issue
> +  * with this register not getting restored on ctx restore
> +  */
> + }
> +


>   return 0;
>  }
>  
> -- 
> 1.9.1
> 
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-- 
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[Intel-gfx] [PATCH] drm/i915/guc: Add GuC css header parser

[yu . dai]

From: Alex Dai 

The size / offset information of all firmware ingredients are
now caculated from header. Driver will validate the header and
rsa key size. If any component is out of boundary, driver will
reject the loading too.

v3: 1) Move DOC to intel_guc_fwif.h right before css_header
definition. Add more comments.
2) Change 'size' to 'len' or 'length' to avoid confusion.
3) Add UOS_RSA_SCRATCH_MAX_COUNT according to BSpec. And
driver validate size of RSA key now.
4) Add fw component size/offset info to intel_guc_fw.

v2: Add indent into DOC to make fixed-width format rather than
change the tmpl.

v1: 1) guc_css_header is defined as __packed now
2) Add and correct GuC related topics in kernel/Doc

Signed-off-by: Alex Dai 
---
 Documentation/DocBook/drm.tmpl  |   9 ++-
 drivers/gpu/drm/i915/i915_debugfs.c |  10 ++-
 drivers/gpu/drm/i915/i915_guc_reg.h |   1 +
 drivers/gpu/drm/i915/intel_guc.h|  16 +++--
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  72 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 110 +++-
 6 files changed, 166 insertions(+), 52 deletions(-)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 66bc646..4d8dffb 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4155,14 +4155,19 @@ int num_ioctls;
   GuC-based Command Submission
   
 GuC
-!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader
+!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC
 !Idrivers/gpu/drm/i915/intel_guc_loader.c
   
   
 GuC Client
-!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submissison
+!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC Client
 !Idrivers/gpu/drm/i915/i915_guc_submission.c
   
+  
+GuC Firmware Layout
+!Pdrivers/gpu/drm/i915/intel_guc_fwif.h GuC Firmware Layout
+!Idrivers/gpu/drm/i915/intel_guc_fwif.h
+  
 
 
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..0753b2f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2386,9 +2386,15 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
seq_printf(m, "\tload: %s\n",
intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->ver_major_wanted, guc_fw->ver_minor_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->ver_major_found, guc_fw->ver_minor_found);
+   seq_printf(m, "\theader: offset is %d; size = %d\n",
+   guc_fw->header_offset, guc_fw->header_size);
+   seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+   guc_fw->ucode_offset, guc_fw->ucode_size);
+   seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+   guc_fw->rsa_offset, guc_fw->rsa_size);
 
tmp = I915_READ(GUC_STATUS);
 
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index b355661..578739d 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -42,6 +42,7 @@
 #define SOFT_SCRATCH(n)(0xc180 + ((n) * 4))
 
 #define UOS_RSA_SCRATCH_0  0xc200
+#define   UOS_RSA_SCRATCH_MAX_COUNT  64
 #define DMA_ADDR_0_LOW 0xc300
 #define DMA_ADDR_0_HIGH0xc304
 #define DMA_ADDR_1_LOW 0xc308
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4ec2d27..55c9bf8 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -72,15 +72,21 @@ struct intel_guc_fw {
enum intel_guc_fw_statusguc_fw_fetch_status;
enum intel_guc_fw_statusguc_fw_load_status;
 
-   uint16_tguc_fw_major_wanted;
-   uint16_tguc_fw_minor_wanted;
-   uint16_tguc_fw_major_found;
-   uint16_tguc_fw_minor_found;
+   uint32_t header_size;
+   uint32_t header_offset;
+   uint32_t rsa_size;
+   uint32_t rsa_offset;
+   uint32_t ucode_size;
+   uint32_t ucode_offset;
+
+   uint16_t ver_major_wanted;
+   uint16_t ver_minor_wanted;
+   uint16_t ver_major_found;
+   uint16_t ver_minor_found;
 };
 
 struct intel_guc {
struct intel_guc_fw guc_fw;
-
uint32_t log_flags;
struct drm_i915_gem_object *log_obj;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index e1f47ba..cd94075 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ 

Re: [Intel-gfx] [1/7] drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.

[Brian Norris]

On Thu, Aug 20, 2015 at 05:55:38PM -0700, Rodrigo Vivi wrote:
> This is wrong since my commit (89251b17). The intention of that
> commit was to remove this one here that is also wrong anyway,
> but it was forgotten.
> 
> Signed-off-by: Rodrigo Vivi 

Tested-by: Brian Norris 

(caveat below)

I was just debugging some PSR issues on Broadwell and ran across your
commit 89251b17. I was also left wondering:
(1) why the duplicate DPCD write to DP_PSR_EN_CFG and
(2) why the '& ~DP_PSR_MAIN_LINK_ACTIVE' mask

Anyway, I was going to send a similar patch soon :)

*** Testing caveat: ***

PSR is still broken on my Broadwell system as of commit 3301d4092106
("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic"). I've done a
partial revert of this commit (but made sure I avoid link standby, as
commit 89251b177b58 ("drm/i915: PSR: deprecate link_standby support for
core platforms.") rightly argues).

But I'll send a proper mail for this issue separately, rather than
carrying on about it here on an unrelated patch.

*** End caveat ***

Regards,
Brian

> ---
> drivers/gpu/drm/i915/intel_psr.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index a04b4dc..51f0514 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -170,9 +170,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  
>   aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>  
> - drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG,
> -DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
> -
>   /* Enable AUX frame sync at sink */
>   if (dev_priv->psr.aux_frame_sync)
>   drm_dp_dpcd_writeb(_dp->aux,
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Re: [Intel-gfx] [4/7] drm/i915: PSR: Mask LPSP hw tracking back again.

[Brian Norris]

On Thu, Aug 20, 2015 at 05:55:41PM -0700, Rodrigo Vivi wrote:
> At the beginning it was masked to allow PSR at all.
> Than it got removed later by my
> commit 09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.")
> in order to trying fixing one case reported at intel-gfx mailing list
> where we were missing screen updates when runtime_pm was enabled.
> 
> However I verified that other patch that makes flush to force
> invalidate also fixes this issue by itself.
> commit 169de1316c1e ("drm/i915: PSR: Flush means invalidate + flush")
> 
> Mainly now that we are relying more on frontbuffer tracking it is a
> good idea to mask this hw tracking again.
> 
> But besides all this above it is important to hightligh that with LPSP
> unmasked we started seeing some screen freezings as reported at fd.o.
> 
> This patch fixes the unrecoverable frozen screens reported:
> 
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91437
> 
> Cc: Ivan Mitev 
> Signed-off-by: Rodrigo Vivi 

FWIW:

Tested-by: Brian Norris 

After patching up another regression locally, I bisected down to commit
09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.") when
searching for why I could rarely get into PSR. I guess that's intended
behavior from the commit message?

WARNING: With this patch if snd_intel_hda driver is
running and not releasing power well properly PSR will
constant Exit and Performance Counter will be 0.

Anyway, I guess I'm saying I'm interested in whether there is a sane
path to getting PSR going again (without disabling sound!).

Regards,
Brian
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[Intel-gfx] [RFC PATCH] drm/i915: PSR regressions on Broadwell

[Brian Norris]

When using PSR, I see the screen freeze after only a few frames (sometimes a
split second; sometimes it seems like practically the first frame). Bisecting
led me to commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT
logic") in v4.2. This patch is the simplest fix that gets it working again for
me, but it's probably wrong.

Random thought: perhaps my panel's DPCD is programmed incorrectly?

Anyway, any tips on fixing this properly?

Seen on Chromebook Pixel 2.

Also required this patch to get PSR properly running on 4.3-rc2:

https://patchwork.freedesktop.org/patch/57698/

Signed-off-by: Brian Norris 
---
 drivers/gpu/drm/i915/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7e335a8546f6..4cd33b76b8a6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -261,7 +261,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
uint32_t val = 0x0;
const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-   if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
+   if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) &&
+   !IS_BROADWELL(dev)) {
/* It doesn't mean we shouldn't send TPS patters, so let's
   send the minimal TP1 possible and skip TP2. */
val |= EDP_PSR_TP1_TIME_100us;
-- 
2.6.0.rc2.230.g3dd15c0

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[Intel-gfx] [PATCH] drm/i915: On reset/suspend disable hpd pins & cancel pending delayed work

[Egbert Eich]

This makes sure no hpd interrupt or reenable worker fires when
resetting or suspending.
We already call intel_hpd_init() in most cases on resume and
after reset to undo this.

Signed-off-by: Egbert Eich 
---
 drivers/gpu/drm/i915/i915_drv.c  |  3 +++
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_display.c |  5 +++--
 drivers/gpu/drm/i915/intel_hotplug.c | 28 
 4 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e2bf9e2..cb8d75f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -620,6 +620,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
intel_dp_mst_suspend(dev);
 
+   intel_hpd_uninit(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_hpd_cancel_work(dev_priv);
 
@@ -1477,12 +1478,14 @@ static int intel_runtime_suspend(struct device *device)
mutex_unlock(>struct_mutex);
 
intel_suspend_gt_powersave(dev);
+   intel_hpd_uninit(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
 
ret = intel_suspend_complete(dev_priv);
if (ret) {
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_hpd_init(dev_priv);
 
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6b7576..3c06629 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2688,6 +2688,7 @@ void i915_firmware_load_error_print(const char *fw_path, 
int err);
 /* intel_hotplug.c */
 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 
long_mask);
 void intel_hpd_init(struct drm_i915_private *dev_priv);
+void intel_hpd_uninit(struct drm_i915_private *dev_priv);
 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fc00867..fadd4f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3207,16 +3207,17 @@ void intel_finish_reset(struct drm_device *dev)
 * The display has been reset as well,
 * so need a full re-initialization.
 */
+   intel_hpd_uninit(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_runtime_pm_enable_interrupts(dev_priv);
 
intel_modeset_init_hw(dev);
-
+#if 0
spin_lock_irq(_priv->irq_lock);
if (dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev);
spin_unlock_irq(_priv->irq_lock);
-
+#endif
intel_display_resume(dev);
 
intel_hpd_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
b/drivers/gpu/drm/i915/intel_hotplug.c
index b177857..4f2a179 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -484,6 +484,34 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
spin_unlock_irq(_priv->irq_lock);
 }
 
+/**
+ * intel_hpd_uninit - disable and deinitialize hpd support
+ * @dev_priv: i915 device instance
+ *
+ * This function disables any pending delayed work for HPD and
+ * disables all hpd pins. Calling this during suspend/reset
+ * avoids conflicts with the reenable worker of interrupt handler
+ * firing.
+ * At resume we call intel_hpd_init() to reenable things.
+ */
+void intel_hpd_uninit(struct drm_i915_private *dev_priv)
+{
+   struct drm_device *dev = dev_priv->dev;
+   int i;
+
+   cancel_delayed_work_sync(_priv->hotplug.reenable_work);
+
+   spin_lock_irq(_priv->irq_lock);
+
+   for_each_hpd_pin(i) {
+   dev_priv->hotplug.stats[i].state = HPD_DISABLED;
+   }
+   if (dev_priv->display.hpd_irq_setup)
+   dev_priv->display.hpd_irq_setup(dev);
+
+   spin_unlock_irq(_priv->irq_lock);
+}
+
 void intel_hpd_init_work(struct drm_i915_private *dev_priv)
 {
INIT_WORK(_priv->hotplug.hotplug_work, i915_hotplug_work_func);
-- 
1.8.4.5

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Re: [Intel-gfx] [PATCH 1/2] drm: Add a non-locking version of drm_kms_helper_poll_enable(), v2

[Egbert Eich]

Jani Nikula writes:
 > 
 > Shouldn't this be _unlocked?
 > 
 > I thought the convention was that functions that do not acquire locks
 > are called _unlocked (although they may require a lock to be held when
 > called). And you might have foo() that grabs locks around a call to
 > foo_unlocked().
 > 

Looking into this, functions that are to be called in a context where
the lock is already held should receive the suffix _locked while
those which do locking themselves and thus need to be called from
a context that doesn't hold this lock already receive the suffix 
_unlocked: the past tense refers to what has happened before.

Cheers,
Egbert.
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Re: [Intel-gfx] [PATCH v2] drm/i915: set proper N/CTS in modeset

[Jani Nikula]

On Fri, 25 Sep 2015, libin.y...@intel.com wrote:
> From: Libin Yang 
>
> When modeset occurs and the TMDS frequency is set to some
> speical values, the N/CTS need to be set manually if audio
> is playing.
>
> Signed-off-by: Libin Yang 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/intel_audio.c | 57 
> --
>  include/drm/i915_component.h   | 10 +++
>  2 files changed, 58 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index e3c32ce..642dfbd 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -128,6 +128,20 @@ static int audio_config_get_n(const struct 
> drm_display_mode *mode, int rate)
>   return 0;
>  }
>  
> +static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
> +{
> + int n_low, n_up;
> + uint32_t tmp = val;
> +
> + n_low = n & 0xfff;
> + n_up = (n >> 12) & 0xff;
> + tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
> + tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
> + (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
> + AUD_CONFIG_N_PROG_ENABLE);
> + return tmp;
> +}
> +
>  /* check whether N/CTS/M need be set manually */
>  static bool audio_rate_need_prog(struct intel_crtc *crtc,
>   struct drm_display_mode *mode)
> @@ -262,9 +276,14 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>   struct drm_i915_private *dev_priv = connector->dev->dev_private;
>   struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>   enum pipe pipe = intel_crtc->pipe;
> + struct i915_audio_component *acomp = dev_priv->audio_component;
>   const uint8_t *eld = connector->eld;
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(>base);
> + enum port port = intel_dig_port->port;
>   uint32_t tmp;
>   int len, i;
> + int n, rate;
>  
>   DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
> pipe_name(pipe), drm_eld_size(eld));
> @@ -302,12 +321,29 @@ static void hsw_audio_codec_enable(struct drm_connector 
> *connector,
>   /* Enable timestamps */
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
>   tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
> - tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
>   tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
>   if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
>   tmp |= AUD_CONFIG_N_VALUE_INDEX;
>   else
>   tmp |= audio_config_hdmi_pixel_clock(mode);
> +
> + tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> + if (audio_rate_need_prog(intel_crtc, mode)) {
> + if (!acomp)
> + rate = 0;
> + else if (port >= PORT_A && port <= PORT_E)
> + rate = acomp->aud_sample_rate[port];
> + else {
> + DRM_ERROR("invalid port: %d\n", port);
> + rate = 0;
> + }
> + n = audio_config_get_n(mode, rate);
> + if (n != 0)
> + tmp = audio_config_setup_n_reg(n, tmp);
> + else
> + DRM_DEBUG_KMS("no suitable N value is found\n");
> + }
> +
>   I915_WRITE(HSW_AUD_CFG(pipe), tmp);
>  
>   mutex_unlock(_priv->av_mutex);
> @@ -594,9 +630,10 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
>   struct intel_digital_port *intel_dig_port;
>   struct intel_crtc *crtc;
>   struct drm_display_mode *mode;
> + struct i915_audio_component *acomp = dev_priv->audio_component;
>   enum pipe pipe = -1;
>   u32 tmp;
> - int n_low, n_up, n;
> + int n;
>  
>   /* HSW, BDW SKL need this fix */
>   if (!IS_SKYLAKE(dev_priv) &&
> @@ -630,6 +667,9 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
> pipe_name(pipe), port_name(port));
>   mode = >config->base.adjusted_mode;
>  
> + /* port must be valid now, otherwise the pipe will be invalid */
> + acomp->aud_sample_rate[port] = rate;
> +
>   /* 2. check whether to set the N/CTS/M manually or not */
>   if (!audio_rate_need_prog(crtc, mode)) {
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
> @@ -649,15 +689,10 @@ static int i915_audio_component_sync_audio_rate(struct 
> device *dev,
>   mutex_unlock(_priv->av_mutex);
>   return 0;
>   }
> - n_low = n & 0xfff;
> - n_up = (n >> 12) & 0xff;
>  
> - /* 4. set the N/CTS/M */
> + /* 3. set the N/CTS/M */
>   tmp = I915_READ(HSW_AUD_CFG(pipe));
> - tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
> - tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
> - (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
> -   

[Intel-gfx] [PATCH v4] drm/i915/bdw: Check for slice, subslice and EU count for BDW

[Łukasz Daniluk]

Added checks for available slices, subslices and EUs for Broadwell. This
information is filled in intel_device_info and is available to user with
GET_PARAM.
Added checks for enabled slices, subslices and EU for Broadwell. This
information is based on available counts but takes power gated slices
into account. It can be read in debugfs.
Introduce new register defines that contain information on slices on
Broadwell.

v2:
- Introduce GT_SLICE_INFO register
- Change Broadwell sseu_device_status function to use GT_SLICE_INFO
  register instead of RPCS register
- Undo removal of dev_priv variables in Cherryview and Gen9
  sseu_device_satus functions

v3:
- Fix style issues

v4:
- Corrected comment
- Reverted reordering of defines

Cc: Jeff Mcgee 
Cc: Arun Siluvery 
Signed-off-by: Łukasz Daniluk 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 29 +-
 drivers/gpu/drm/i915/i915_dma.c | 78 +
 drivers/gpu/drm/i915/i915_reg.h | 18 +
 3 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 72ae347..d0f784d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5037,13 +5037,38 @@ static void gen9_sseu_device_status(struct drm_device 
*dev,
}
 }
 
+static void broadwell_sseu_device_status(struct drm_device *dev,
+struct sseu_dev_status *stat)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   int s;
+   u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
+
+   stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
+
+   if (stat->slice_total) {
+   stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
+   stat->subslice_total = stat->slice_total *
+  stat->subslice_per_slice;
+   stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
+   stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
+
+   /* subtract fused off EU(s) from enabled slice(s) */
+   for (s = 0; s < stat->slice_total; s++) {
+   u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
+
+   stat->eu_total -= hweight8(subslice_7eu);
+   }
+   }
+}
+
 static int i915_sseu_status(struct seq_file *m, void *unused)
 {
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct sseu_dev_status stat;
 
-   if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
+   if (INTEL_INFO(dev)->gen < 8)
return -ENODEV;
 
seq_puts(m, "SSEU Device Info\n");
@@ -5068,6 +5093,8 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
memset(, 0, sizeof(stat));
if (IS_CHERRYVIEW(dev)) {
cherryview_sseu_device_status(dev, );
+   } else if (IS_BROADWELL(dev)) {
+   broadwell_sseu_device_status(dev, );
} else if (INTEL_INFO(dev)->gen >= 9) {
gen9_sseu_device_status(dev, );
}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 066a0ef..72e2bbd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -713,6 +713,82 @@ static void gen9_sseu_info_init(struct drm_device *dev)
info->has_eu_pg = (info->eu_per_subslice > 2);
 }
 
+static void broadwell_sseu_info_init(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_device_info *info;
+   const int s_max = 3, ss_max = 3, eu_max = 8;
+   int s, ss;
+   u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+
+   fuse2 = I915_READ(GEN8_FUSE2);
+   s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+   ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
+
+   eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
+   eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
+   ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
+(32 - GEN8_EU_DIS0_S1_SHIFT));
+   eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
+   ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
+(32 - GEN8_EU_DIS1_S2_SHIFT));
+
+
+   info = (struct intel_device_info *)_priv->info;
+   info->slice_total = hweight32(s_enable);
+
+   /*
+* The subslice disable field is global, i.e. it applies
+* to each of the enabled slices.
+*/
+   info->subslice_per_slice = ss_max - hweight32(ss_disable);
+   info->subslice_total = info->slice_total * info->subslice_per_slice;
+

Re: [Intel-gfx] [PATCH 1/2] drm: Add a non-locking version of drm_kms_helper_poll_enable(), v2

[Jani Nikula]

On Fri, 25 Sep 2015, Egbert Eich  wrote:
> Jani Nikula writes:
>  > 
>  > Shouldn't this be _unlocked?
>  > 
>  > I thought the convention was that functions that do not acquire locks
>  > are called _unlocked (although they may require a lock to be held when
>  > called). And you might have foo() that grabs locks around a call to
>  > foo_unlocked().
>  > 
>
> Looking into this, functions that are to be called in a context where
> the lock is already held should receive the suffix _locked while
> those which do locking themselves and thus need to be called from
> a context that doesn't hold this lock already receive the suffix 
> _unlocked: the past tense refers to what has happened before.

I'm afraid existing conventions trump what makes sense.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: set proper N/CTS in modeset

[Takashi Iwai]

On Fri, 25 Sep 2015 10:01:48 +0200,
Jani Nikula wrote:
> 
> On Fri, 25 Sep 2015, libin.y...@intel.com wrote:
> > From: Libin Yang 
> >
> > When modeset occurs and the TMDS frequency is set to some
> > speical values, the N/CTS need to be set manually if audio
> > is playing.
> >
> > Signed-off-by: Libin Yang 
> 
> Reviewed-by: Jani Nikula 

Now all 4 patches are applied to topic/drm-sync-audio-rate.
  git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git 
topic/drm-sync-audio-rate

It was merged back to sound for-next branch, too.

Feel free to merge this branch into drm tree.


thanks,

Takashi

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_audio.c | 57 
> > --
> >  include/drm/i915_component.h   | 10 +++
> >  2 files changed, 58 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index e3c32ce..642dfbd 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -128,6 +128,20 @@ static int audio_config_get_n(const struct 
> > drm_display_mode *mode, int rate)
> > return 0;
> >  }
> >  
> > +static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
> > +{
> > +   int n_low, n_up;
> > +   uint32_t tmp = val;
> > +
> > +   n_low = n & 0xfff;
> > +   n_up = (n >> 12) & 0xff;
> > +   tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
> > +   tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
> > +   (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
> > +   AUD_CONFIG_N_PROG_ENABLE);
> > +   return tmp;
> > +}
> > +
> >  /* check whether N/CTS/M need be set manually */
> >  static bool audio_rate_need_prog(struct intel_crtc *crtc,
> > struct drm_display_mode *mode)
> > @@ -262,9 +276,14 @@ static void hsw_audio_codec_enable(struct 
> > drm_connector *connector,
> > struct drm_i915_private *dev_priv = connector->dev->dev_private;
> > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> > enum pipe pipe = intel_crtc->pipe;
> > +   struct i915_audio_component *acomp = dev_priv->audio_component;
> > const uint8_t *eld = connector->eld;
> > +   struct intel_digital_port *intel_dig_port =
> > +   enc_to_dig_port(>base);
> > +   enum port port = intel_dig_port->port;
> > uint32_t tmp;
> > int len, i;
> > +   int n, rate;
> >  
> > DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
> >   pipe_name(pipe), drm_eld_size(eld));
> > @@ -302,12 +321,29 @@ static void hsw_audio_codec_enable(struct 
> > drm_connector *connector,
> > /* Enable timestamps */
> > tmp = I915_READ(HSW_AUD_CFG(pipe));
> > tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
> > -   tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> > tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
> > if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
> > tmp |= AUD_CONFIG_N_VALUE_INDEX;
> > else
> > tmp |= audio_config_hdmi_pixel_clock(mode);
> > +
> > +   tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> > +   if (audio_rate_need_prog(intel_crtc, mode)) {
> > +   if (!acomp)
> > +   rate = 0;
> > +   else if (port >= PORT_A && port <= PORT_E)
> > +   rate = acomp->aud_sample_rate[port];
> > +   else {
> > +   DRM_ERROR("invalid port: %d\n", port);
> > +   rate = 0;
> > +   }
> > +   n = audio_config_get_n(mode, rate);
> > +   if (n != 0)
> > +   tmp = audio_config_setup_n_reg(n, tmp);
> > +   else
> > +   DRM_DEBUG_KMS("no suitable N value is found\n");
> > +   }
> > +
> > I915_WRITE(HSW_AUD_CFG(pipe), tmp);
> >  
> > mutex_unlock(_priv->av_mutex);
> > @@ -594,9 +630,10 @@ static int i915_audio_component_sync_audio_rate(struct 
> > device *dev,
> > struct intel_digital_port *intel_dig_port;
> > struct intel_crtc *crtc;
> > struct drm_display_mode *mode;
> > +   struct i915_audio_component *acomp = dev_priv->audio_component;
> > enum pipe pipe = -1;
> > u32 tmp;
> > -   int n_low, n_up, n;
> > +   int n;
> >  
> > /* HSW, BDW SKL need this fix */
> > if (!IS_SKYLAKE(dev_priv) &&
> > @@ -630,6 +667,9 @@ static int i915_audio_component_sync_audio_rate(struct 
> > device *dev,
> >   pipe_name(pipe), port_name(port));
> > mode = >config->base.adjusted_mode;
> >  
> > +   /* port must be valid now, otherwise the pipe will be invalid */
> > +   acomp->aud_sample_rate[port] = rate;
> > +
> > /* 2. check whether to set the N/CTS/M manually or not */
> > if (!audio_rate_need_prog(crtc, mode)) {
> > tmp = I915_READ(HSW_AUD_CFG(pipe));
> > @@ -649,15 +689,10 @@ static int 
> > i915_audio_component_sync_audio_rate(struct device *dev,
> > 

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

[Patrik Jakobsson]

On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote:
> > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Sep 23, 2015 at 10:43:00AM +0200, Daniel Vetter wrote:
> > > > On Mon, Sep 21, 2015 at 10:00:45AM +0200, Patrik Jakobsson wrote:
> > > > > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > > > > > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > > > > > > We need to be able to control if DC6 is allowed or not. Much like
> > > > > > > requesting power to a specific piece of the hardware we need to 
> > > > > > > be able
> > > > > > > to request that we don't enter DC6 during certain hw access.
> > > > > > > 
> > > > > > > To solve this without introducing too much infrastructure I'm 
> > > > > > > hooking
> > > > > > > into the power well / power domain framework. DC6 prevention is 
> > > > > > > modeled
> > > > > > > much like an enabled power well. Thus I'm using the terminology 
> > > > > > > on/off
> > > > > > > for DC states instead of enable/disable.
> > > > > > > 
> > > > > > > The problem that started this work is the need for DC6 to be 
> > > > > > > disabled
> > > > > > > when accessing DP_AUX_A during CRTC on/off. That is also fixed in 
> > > > > > > this
> > > > > > > patch.
> > > > > > > 
> > > > > > > This is posted as an RFC since DMC and DC state handling is being
> > > > > > > reworked and will possibly affect the outcome of this patch. The 
> > > > > > > patch
> > > > > > > has known warnings.
> > > > > > > 
> > > > > > > Signed-off-by: Patrik Jakobsson 
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/i915/intel_ddi.c|  9 +
> > > > > > >  drivers/gpu/drm/i915/intel_drv.h|  2 +
> > > > > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 69 
> > > > > > > +
> > > > > > >  3 files changed, 64 insertions(+), 16 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > > > > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > index 4823184..c2c1ad2 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > @@ -2288,6 +2288,8 @@ static void intel_ddi_pre_enable(struct 
> > > > > > > intel_encoder *intel_encoder)
> > > > > > >   if (type == INTEL_OUTPUT_DISPLAYPORT || type == 
> > > > > > > INTEL_OUTPUT_EDP) {
> > > > > > >   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > > > > >  
> > > > > > > + intel_display_power_get(dev_priv, POWER_DOMAIN_AUX_A);
> > > > > > > +
> > > > > > 
> > > > > > These I think shouldn't be necessary with my
> > > > > > intel_display_port_aux_power_domain() stuff since intel_dp_aux_ch() 
> > > > > > will
> > > > > > itself grab the appropriate power domain.
> > > > > > 
> > > > > > That's of course assuming that AUX is the only reason why we need to
> > > > > > keep DC6 disabled here.
> > > > > > 
> > > > > 
> > > > > The upside with having get/put around bigger aux transfers is that we 
> > > > > don't get
> > > > > tons of enable/disable lines in the log. My vote is that we keep this 
> > > > > but also
> > > > > have your fine-grained get/puts.
> > > > 
> > > > Imo the correct solution to avoid this is by adding a slight bit of
> > > > hystersis to the power well code. Which means that yes, we reinvent
> > > > another feature of the core power_domain code in our home-grown 
> > > > solution -
> > > > I hate it when my years old predictions come true ;-)
> > > > 
> > > > Sprinkling higher-level get/put calls all over the place is imo just
> > > > leaking the abstraction, which isn't good.
> > > > -Daniel
> > > 
> > > With Ville's patches the problem is not as bad as I first thought. We can 
> > > add
> > > hysteresis later if needed.
> > > 
> > > -Patrik
> > 
> > So I discovered that we cannot have DC5 and DC6 as seperate power wells 
> > since
> > they are mutually exclusive. As Ville pointed out we don't use DC5 for 
> > anything
> > so we could get away for now with just DC6 as a power well.
> > 
> > As I see it there are three ways to go about this:
> > 
> > A. Add AUX A to Power well 2.
> > This would power up PW2 during DP Aux A even though we don't need it but 
> > since
> > we get the side effect of DC6 being disabled it should work.
> > 
> > B. Add DC6 off as a power well and remove DC5 off.
> > Fairly straight forward but assumes we don't need DC5 control.
> > 
> > C. Add multi-state support for the DC power well.
> > Would be the nice way but perhaps a bit overkill. Good thing about this 
> > would be
> > that we can incorporate DC9 control for BXT and unify more of the DC code.
> > 
> > So A, B or C?
> 
> After some spitballing with Imre we came up with the following power well 
> layout,
> which I think matches the documented seuqences in the spec the best:
> 
> display well:
> domains: 

[Intel-gfx] [PULL] topic/drm-misc

[Daniel Vetter]

Hi Dave,

Another attempt at drm-misc for 4.4 ...
- better atomic helpers for runtime pm drivers
- atomic fbdev
- dp aux i2c STATUS_UPDATE handling (for short i2c replies from the sink)
- bunch of constify patches
- inital kerneldoc for vga switcheroo
- some vblank code cleanups from Ville and Thierry
- various polish all over

Cheers, Daniel


The following changes since commit 1f93e4a96c9109378204c147b3eec0d0e8100fde:

  Linux 4.3-rc2 (2015-09-20 14:32:34 -0700)

are available in the git repository at:

  git://anongit.freedesktop.org/drm-intel tags/topic/drm-misc-2015-09-25

for you to fetch changes up to cf6483050e9bf13979415d9fd388554d8c8f3477:

  drm/irq: Add drm_crtc_vblank_count_and_time() (2015-09-24 20:27:17 +0200)


Bob Paauwe (1):
  dtrm/edid: Allow comma separated edid binaries. (v3)

Daniel Vetter (9):
  drm/atomic-helper: properly annotate functions in kerneldoc
  drm/fb-helper: Use -errno return in restore_mode_unlocked
  drm: Make drm_fb_unregister/remove accept NULL fb
  drm/fb-helper: Add module option to disable fbdev emulation
  drm/atomic: refuse changing CRTC for planes directly
  drm/atomic-helper: Add option to update planes only on active crtc
  drm/atomic-helper: Pimp docs with recommendations for rpm drivers
  drm: Nuke drm_framebuffer->helper_private
  Merge tag 'v4.3-rc2' into topic/drm-misc

Danilo Cesar Lemes de Paula (1):
  drm/doc: Fixing xml documentation warning

David Herrmann (2):
  drm: simplify drm_sysfs_destroy() via IS_ERR_OR_NULL()
  drm: move drm_class into drm_sysfs.c

Geliang Tang (2):
  drm: fix kernel-doc warnings in drm_crtc.h
  drm: drm_atomic_crtc_get_property should be static

Gustavo Padovan (1):
  drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers

Laurent Pinchart (1):
  drm/atomic-helper: Don't skip plane disabling on active CRTC

Lukas Wunner (4):
  vga_switcheroo: Document _ALL_ the things!
  drm: Spell vga_switcheroo consistently
  vga_switcheroo: Sort headers alphabetically
  vga_switcheroo: Set active attribute to false for audio clients

Maarten Lankhorst (5):
  drm/atomic: Make sure lock is held in trylock contexts.
  drm/atomic: Make prepare_fb/cleanup_fb only take state, v3.
  drm/core: Do not call drm_framebuffer_remove internally during teardown.
  drm/core: Preserve the framebuffer after removing it.
  drm/core: Preserve the fb id on close.

Matt Roper (1):
  drm/fbdev: Update legacy plane->fb refcounting for atomic restore

Michel Thierry (1):
  drm/mm: Do DRM_MM_CREATE_TOP adj_start calculation after color_adjust

Rob Clark (5):
  drm: cleanup modesetting ioctls, one param per line
  drm/fb-helper: add headerdoc for drm_fb_helper
  drm/fb-helper: atomic restore_fbdev_mode()..
  drm/fb-helper: atomic pan_display()..
  drm/i915: enable atomic fb-helper

Thierry Reding (4):
  drm/atomic-helper: Implement drm_atomic_helper_duplicate_state()
  drm/gma500: Remove DP_LINK_STATUS_SIZE redefinition
  drm/irq: Rename drm_crtc -> crtc
  drm/irq: Add drm_crtc_vblank_count_and_time()

Ville Syrjälä (21):
  drm: Constify generic_edid_names[]
  drm: Constify TV mode names
  drm/i2c/ch7006: Constify ch7006_tv_norms[] and ch7006_modes[]
  drm/dp: s/I2C_STATUS/I2C_WRITE_STATUS_UPDATE/
  drm/i915: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE
  drm/radeon: Handle DP_AUX_I2C_WRITE_STATUS_UPDATE
  drm/tegra: Handle I2C_WRITE_STATUS_UPDATE for address only writes
  drm/dp: Use I2C_WRITE_STATUS_UPDATE to drain partial I2C_WRITE requests
  drm: Make some modes const when iterating through them
  drm: Remove the 'mode' argument from drm_select_eld()
  drm: Make drm_av_sync_delay() 'mode' argument const
  drm: s/int crtc/unsigned int pipe/ straggles
  drm: Move timestamping constants into drm_vblank_crtc
  drm: Stop using linedur_ns and pixeldur_ns for vblank timestamps
  drm: Kill pixeldur_ns
  drm/i915: Fix vblank count variable types
  drm: Pass flags to drm_update_vblank_count()
  drm: Limit the number of .get_vblank_counter() retries
  drm: Clean up drm_calc_vbltimestamp_from_scanoutpos() vbl_status
  drm: store_vblank() is never called with NULL timestamp
  drm: Use vblank timestamps to guesstimate how many vblanks were missed

 Documentation/DocBook/drm.tmpl  |   2 +-
 Documentation/kernel-parameters.txt |  15 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  11 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h|   3 +-
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |   4 +-
 drivers/gpu/drm/drm_atomic.c|  28 +-
 drivers/gpu/drm/drm_atomic_helper.c | 316 --
 drivers/gpu/drm/drm_crtc.c  |  34 

Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

[R, Durgadoss]

Hi Daniel,

Thanks for having a look at it..

>-Original Message-
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
>Sent: Wednesday, September 23, 2015 3:14 PM
>To: R, Durgadoss
>Cc: Jani Nikula; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT
>
>On Wed, Sep 16, 2015 at 10:57:45AM +, R, Durgadoss wrote:
>> Hi Jani,
>>
>> >-Original Message-
>> >From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>> >Sent: Wednesday, September 16, 2015 3:18 PM
>> >To: R, Durgadoss; intel-gfx@lists.freedesktop.org
>> >Cc: R, Durgadoss
>> >Subject: Re: [RFC DP-typeC 0/2] Support USB typeC based DP on BXT
>> >
>> >On Tue, 15 Sep 2015, Durgadoss R  wrote:
>> >> This is an RFC series to start the review/discussion on approach
>> >> to support USB type C based DP panel.
>> >>
>> >> To support USB type C alternate DP mode, the display driver needs to
>> >> know the number of lanes required by the DP panel as well as number
>> >> of lanes that can be supported by the type-C cable. Sometimes, the
>> >> type-C cable may limit the bandwidth even if Panel can support
>> >> more lanes.
>> >>
>> >> The goal is to find out the number of lanes which can be supported
>> >> using a particular cable so that we can cap 'max_available_lanes'
>> >> to that number during modeset.
>> >>
>> >> These two patches are based on 4.2-rc2 and tested only on
>> >> a BXT A1 platform for now.
>> >>
>> >> Brief summary of the approach taken:
>> >> ---
>> >> 1.As soon as DP-hotplug is detected, driver starts link training
>> >>   with highest number of lanes/bandwidth possible. If it fails,
>> >>   driver retries link training with lane/2 for same bandwidth.
>> >>   We continue this procedure until we find a working configuration
>> >>   of lane/bandwidth values. This 'number of lanes' is then
>> >>   set as the 'max_available_lanes', so that the following
>> >>   intel_dp_compute_config() during modeset picks it up as
>> >>   max_lane_count (instead of 4 always, from DPCD).
>> >
>> >Would all of this work automatically if our link training sequence
>> >followed the DP spec to the letter wrt degrading the link on failures?
>>
>> That is one part of it.
>>
>> Our intention is also to filter out the modes that cannot be set
>> with 'max_available_lanes' through connector->mode_valid
>> callback, which uses these variables. Otherwise, we risk failing
>> a modeset that uses higher resolutions than possible.
>>
>> Sorry, I should have also added this as part of the commit message.
>
>One approach to implement DP link training to the spec is that if things
>fail we enable the pipe anyway (since anything else would seriously
>surprise userspace, especially for async modesets, and lead to hangs in
>userspace if vblank interrupts don't happen). And then we generate a
>hotplug event to inform userspace that something change with the monitor
>configuration, to give userspace a chance to look at the filtered mode
>list and select a new config it likes.
>
>That approach would fit rather well into the overall framework of how
>detection/mode-config changes are done currently by keeping all the policy
>for selecting the precise mode config in userspace. Downside is that for
>usb type-C it would cause flicker since if we only have 2 lanes we'll
>always first try the high-res mode and fail. So I think in the end we need

Yes, agreed.

>both approaches. Wrt the rfc it would be great if we can make it at least
>somewhat platform-agnostic - anything on big core since hsw+ supports

By platform-agnostic,

do you mean to try and implement _upfront_link_train() 
for few more platforms since HSW+ to see how we can re-use common code
if any ?

If it is something else, please elaborate a bit more..

>enabling the DP port without enabling a pipe (because dp mst needs that),
>so could support your approach here too.

We have this kind of implementation tested in CHV and BXT.
Can I consider at least the BXT part as a sample for HSW+ platforms ?

Thanks,
Durga

>-Daniel
>--
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Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

[Daniel Vetter]

Another regression for Jairo to track.
-Daniel

On Thu, Sep 24, 2015 at 05:22:09PM -0400, Nick Bowler wrote:
> Hi,
> 
> Testing out 4.3-rc2, first thing I notice is that the VGA output is
> not working.  Specifically, the display is continuously powering on
> and off -- at no point is any image visible on the screen (I am expecting
> to see the console output).  The display connected to the HDMI output is
> working fine.
> 
> Linux 4.2 did not suffer from this problem.
> 
> In dmesg I see the following messages, which I do not see on a working
> kernel.  Full dmesg from 4.3-rc2 is attached (gzipped).
> 
>   [0.115339] [drm:drm_calc_timestamping_constants] *ERROR* crtc
> 21: Can't calculate constants, dotclock = 0!
>   [0.117582] [drm:intel_opregion_init] *ERROR* No ACPI video bus found
> 
> This is an older machine with Intel G45 graphics.
> 
> Unfortunately bisection is proving difficult, because the commits it
> wants me to test have a different problem: neither display comes up at
> all (both remain in standby).  Partial results follow.
> 
> Thanks,
>   Nick
> 
>   git bisect start 'drivers/gpu/drm/i915'
>   # bad: [1f93e4a96c9109378204c147b3eec0d0e8100fde] Linux 4.3-rc2
>   git bisect bad 1f93e4a96c9109378204c147b3eec0d0e8100fde
>   # good: [64291f7db5bd8150a74ad2036f1037e6a0428df2] Linux 4.2
>   git bisect good 64291f7db5bd8150a74ad2036f1037e6a0428df2
>   # skip: [a7a6c498927ea42c9a3b26e0caa5c854a980d58c] drm/i915:
> POSTING_READ() in intel_set_memory_cxsr()
>   git bisect skip a7a6c498927ea42c9a3b26e0caa5c854a980d58c
>   # skip: [031b698a77a70a6c394568034437b5486a44e868] drm/i915:
> Unconditionally do fb tracking invalidate in set_domain
>   git bisect skip 031b698a77a70a6c394568034437b5486a44e868
>   # skip: [adeca76d8e2b34b5c739a36f4191aed63080da40] drm/i915:
> Simplify i915_gem_execbuffer_retire_commands() parameters
>   git bisect skip adeca76d8e2b34b5c739a36f4191aed63080da40
>   # good: [369712e89404089fa559235bb1ee8fc40d976e6b] drm/i915: reduce
> duplicate conditions in i9xx_hpd_irq_handler
>   git bisect good 369712e89404089fa559235bb1ee8fc40d976e6b
>   # skip: [6eb1a6817246f1a67de4d6959a84d09efead5329] drm/i915: Read wm
> values from hardware at init on CHV
>   git bisect skip 6eb1a6817246f1a67de4d6959a84d09efead5329
>   # bad: [d14e7b6d1d8747826cb900db852351c550e00fdd] drm/i915: Check DP
> link status on long hpd too
>   git bisect bad d14e7b6d1d8747826cb900db852351c550e00fdd
>   # skip: [fe36f55d4d4447679923fc74564786ae423ca4bd] drm/i915/gtt:
> Cleanup page directory encoding
>   git bisect skip fe36f55d4d4447679923fc74564786ae423ca4bd


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Re: [Intel-gfx] [PATCH v2 04/43] drm/i915: Parametrize fence registers

[Jani Nikula]

On Mon, 21 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
>
> v2: Hide the 945 vs. rest of gen2/3 difference in the macro
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_gem_fence.c | 41 
> +++
>  drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++---
>  drivers/gpu/drm/i915/i915_reg.h   | 18 ++-
>  3 files changed, 39 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
> b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 6077dff..1cbfd5b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, 
> int reg,
>struct drm_i915_gem_object *obj)
>  {
>   struct drm_i915_private *dev_priv = dev->dev_private;
> - int fence_reg;
> + int fence_reg_lo, fence_reg_hi;
>   int fence_pitch_shift;
>  
>   if (INTEL_INFO(dev)->gen >= 6) {
> - fence_reg = FENCE_REG_SANDYBRIDGE_0;
> - fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
> + fence_reg_lo = FENCE_REG_GEN6_LO(reg);
> + fence_reg_hi = FENCE_REG_GEN6_HI(reg);
> + fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>   } else {
> - fence_reg = FENCE_REG_965_0;
> + fence_reg_lo = FENCE_REG_965_LO(reg);
> + fence_reg_hi = FENCE_REG_965_HI(reg);
>   fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
>   }
>  
> - fence_reg += reg * 8;
> -
>   /* To w/a incoherency with non-atomic 64-bit register updates,
>* we split the 64-bit update into two 32-bit writes. In order
>* for a partial fence not to be evaluated between writes, we
> @@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, 
> int reg,
>* For extra levels of paranoia, we make sure each step lands
>* before applying the next step.
>*/
> - I915_WRITE(fence_reg, 0);
> - POSTING_READ(fence_reg);
> + I915_WRITE(fence_reg_lo, 0);
> + POSTING_READ(fence_reg_lo);
>  
>   if (obj) {
>   u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device 
> *dev, int reg,
>   val |= 1 << I965_FENCE_TILING_Y_SHIFT;
>   val |= I965_FENCE_REG_VALID;
>  
> - I915_WRITE(fence_reg + 4, val >> 32);
> - POSTING_READ(fence_reg + 4);
> + I915_WRITE(fence_reg_hi, val >> 32);
> + POSTING_READ(fence_reg_hi);
>  
> - I915_WRITE(fence_reg + 0, val);
> - POSTING_READ(fence_reg);
> + I915_WRITE(fence_reg_lo, val);
> + POSTING_READ(fence_reg_lo);
>   } else {
> - I915_WRITE(fence_reg + 4, 0);
> - POSTING_READ(fence_reg + 4);
> + I915_WRITE(fence_reg_hi, 0);
> + POSTING_READ(fence_reg_hi);
>   }
>  }
>  
> @@ -149,13 +149,8 @@ static void i915_write_fence_reg(struct drm_device *dev, 
> int reg,
>   } else
>   val = 0;
>  
> - if (reg < 8)
> - reg = FENCE_REG_830_0 + reg * 4;
> - else
> - reg = FENCE_REG_945_8 + (reg - 8) * 4;
> -
> - I915_WRITE(reg, val);
> - POSTING_READ(reg);
> + I915_WRITE(FENCE_REG(reg), val);
> + POSTING_READ(FENCE_REG(reg));
>  }
>  
>  static void i830_write_fence_reg(struct drm_device *dev, int reg,
> @@ -186,8 +181,8 @@ static void i830_write_fence_reg(struct drm_device *dev, 
> int reg,
>   } else
>   val = 0;
>  
> - I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
> - POSTING_READ(FENCE_REG_830_0 + reg * 4);
> + I915_WRITE(FENCE_REG(reg), val);
> + POSTING_READ(FENCE_REG(reg));
>  }
>  
>  inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3379f9c..3b574c2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -786,20 +786,15 @@ static void i915_gem_record_fences(struct drm_device 
> *dev,
>   int i;
>  
>   if (IS_GEN3(dev) || IS_GEN2(dev)) {
> - for (i = 0; i < 8; i++)
> - error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> - for (i = 0; i < 8; i++)
> - error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> -   (i * 4));
> - } else if (IS_GEN5(dev) || IS_GEN4(dev))
> - for (i = 0; i < 16; i++)
> - error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> -   (i * 8));
> - 

Re: [Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

[Daniel Vetter]

On Fri, Sep 25, 2015 at 02:16:07PM +0300, Jani Nikula wrote:
> On Fri, 25 Sep 2015, Geliang Tang  wrote:
> > Leak a task reference in i915_ppgtt_info(), add put_task_struct()
> > to fix it.
> 
> Introduced by
> 
> commit 1c60fef535d143860d5bf6593e24ab6417f5227c
> Author: Ben Widawsky 
> Date:   Fri Dec 6 14:11:30 2013 -0800
> 
> drm/i915: Dump all ppgtt

Queued for -next, thanks for the patch.
-Daniel

> 
> 
> >
> > Signed-off-by: Geliang Tang 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5615d3d..8797717 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2288,9 +2288,13 @@ static int i915_ppgtt_info(struct seq_file *m, void 
> > *data)
> >  
> > list_for_each_entry_reverse(file, >filelist, lhead) {
> > struct drm_i915_file_private *file_priv = file->driver_priv;
> > +   struct task_struct *task;
> >  
> > -   seq_printf(m, "\nproc: %s\n",
> > -  get_pid_task(file->pid, PIDTYPE_PID)->comm);
> > +   task = get_pid_task(file->pid, PIDTYPE_PID);
> > +   if (!task)
> > +   return -ESRCH;
> > +   seq_printf(m, "\nproc: %s\n", task->comm);
> > +   put_task_struct(task);
> > idr_for_each(_priv->context_idr, per_file_ctx,
> >  (void *)(unsigned long)m);
> > }
> > -- 
> > 1.9.1
> >
> >
> 
> -- 
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Re: [Intel-gfx] [PATCH] drm/i915: On reset/suspend disable hpd pins & cancel pending delayed work

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 08:09:57AM +0200, Egbert Eich wrote:
> This makes sure no hpd interrupt or reenable worker fires when
> resetting or suspending.
> We already call intel_hpd_init() in most cases on resume and
> after reset to undo this.
> 
> Signed-off-by: Egbert Eich 
> ---
>  drivers/gpu/drm/i915/i915_drv.c  |  3 +++
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_display.c |  5 +++--
>  drivers/gpu/drm/i915/intel_hotplug.c | 28 
>  4 files changed, 35 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e2bf9e2..cb8d75f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -620,6 +620,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>  
>   intel_dp_mst_suspend(dev);
>  
> + intel_hpd_uninit(dev_priv);
>   intel_runtime_pm_disable_interrupts(dev_priv);
>   intel_hpd_cancel_work(dev_priv);
>  
> @@ -1477,12 +1478,14 @@ static int intel_runtime_suspend(struct device 
> *device)
>   mutex_unlock(>struct_mutex);
>  
>   intel_suspend_gt_powersave(dev);
> + intel_hpd_uninit(dev_priv);
>   intel_runtime_pm_disable_interrupts(dev_priv);
>  
>   ret = intel_suspend_complete(dev_priv);
>   if (ret) {
>   DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
>   intel_runtime_pm_enable_interrupts(dev_priv);
> + intel_hpd_init(dev_priv);
>  
>   return ret;
>   }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a6b7576..3c06629 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2688,6 +2688,7 @@ void i915_firmware_load_error_print(const char 
> *fw_path, int err);
>  /* intel_hotplug.c */
>  void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 
> long_mask);
>  void intel_hpd_init(struct drm_i915_private *dev_priv);
> +void intel_hpd_uninit(struct drm_i915_private *dev_priv);
>  void intel_hpd_init_work(struct drm_i915_private *dev_priv);
>  void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
>  bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index fc00867..fadd4f2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3207,16 +3207,17 @@ void intel_finish_reset(struct drm_device *dev)
>* The display has been reset as well,
>* so need a full re-initialization.
>*/
> + intel_hpd_uninit(dev_priv);
>   intel_runtime_pm_disable_interrupts(dev_priv);
>   intel_runtime_pm_enable_interrupts(dev_priv);
>  
>   intel_modeset_init_hw(dev);
> -
> +#if 0
>   spin_lock_irq(_priv->irq_lock);
>   if (dev_priv->display.hpd_irq_setup)
>   dev_priv->display.hpd_irq_setup(dev);
>   spin_unlock_irq(_priv->irq_lock);
> -
> +#endif

This pattern or hdp_irq_setup()+intel_hpd_init() has been cargo culted
all over the place. Can you just kill off the hpd_irq_setup() stuff from
everywhere where it's not needed?

>   intel_display_resume(dev);
>  
>   intel_hpd_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
> b/drivers/gpu/drm/i915/intel_hotplug.c
> index b177857..4f2a179 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -484,6 +484,34 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
>   spin_unlock_irq(_priv->irq_lock);
>  }
>  
> +/**
> + * intel_hpd_uninit - disable and deinitialize hpd support
> + * @dev_priv: i915 device instance
> + *
> + * This function disables any pending delayed work for HPD and
> + * disables all hpd pins. Calling this during suspend/reset
> + * avoids conflicts with the reenable worker of interrupt handler
> + * firing.
> + * At resume we call intel_hpd_init() to reenable things.
> + */
> +void intel_hpd_uninit(struct drm_i915_private *dev_priv)
> +{
> + struct drm_device *dev = dev_priv->dev;
> + int i;
> +
> + cancel_delayed_work_sync(_priv->hotplug.reenable_work);

What if another hpd happens here?

Oh and we already have the intel_hpd_cancel_work() function. Sounds like
we need to rethink how that works rather than rolling another function
to do the same thing.

There's also the matter of VLV/CHV where hpd init gets called from the
display power well enable hook. I was thinking that could race with this
stuff, but since this is only called from the suspend I suppose we
shouldn't be re-enabling the display power well at that time.

> +
> + spin_lock_irq(_priv->irq_lock);
> +
> + for_each_hpd_pin(i) {
> + dev_priv->hotplug.stats[i].state = HPD_DISABLED;
> + }
> + if (dev_priv->display.hpd_irq_setup)
> + dev_priv->display.hpd_irq_setup(dev);
> +
> 

Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

[Jani Nikula]

On Wed, 23 Sep 2015, Rodrigo Vivi  wrote:
> In case something goes wrong with power well initialization we were calling
> intel_prepare_ddi during boot while encoder list isnt't initilized.

Broken record, is this a regression, what is the regressing commit, or
if this was always broken, which commit introduced the broken feature?

BR,
Jani.


>
> [9.618747] i915 :00:02.0: Invalid ROM contents
> [9.631446] [drm] failed to find VBIOS tables
> [9.720036] BUG: unable to handle kernel NULL pointer dereference at 
> 
> 0058
> [9.721986] IP: [] ddi_get_encoder_port+0x82/0x190 [i915]
> [9.723736] PGD 0
> [9.724286] Oops:  [#1] PREEMPT SMP
> [9.725386] Modules linked in: intel_powerclamp snd_hda_intel(+) coretemp 
> crc
> 32c_intel snd_hda_codec snd_hda_core serio_raw snd_pcm snd_timer i915(+) 
> parport
> _pc parport pinctrl_sunrisepoint pinctrl_intel nfsd nfs_acl
> [9.730635] CPU: 0 PID: 497 Comm: systemd-udevd Not tainted 
> 4.3.0-rc2-eywa-10
> 967-g72de2cfd-dirty #2
> [9.732785] Hardware name: Intel Corporation Cannonlake Client 
> platform/Skyla
> ke DT DDR4 RVP8, BIOS CNLSE2R1.R00.X021.B00.1508040310 08/04/2015
> [9.735785] task: 88008a704700 ti: 88016a1ac000 task.ti: 
> 88016a1a
> c000
> [9.737584] RIP: 0010:[]  [] 
> ddi_get_enco
> der_port+0x82/0x190 [i915]
> [9.739934] RSP: :88016a1af710  EFLAGS: 00010296
> [9.741184] RAX: 004e RBX: 88008a9edc98 RCX: 
> 0001
> [9.742934] RDX: 004e RSI: 81fc1e82 RDI: 
> 
> [9.744634] RBP: 88016a1af730 R08:  R09: 
> 0578
> [9.746333] R10: 1065 R11: 0578 R12: 
> fff8
> [9.748033] R13: 88016a1af7a8 R14: 88016a1af794 R15: 
> 
> [9.749733] FS:  7eff2e1e07c0() GS:88016fc0() 
> knlGS:0
> 000
> [9.751683] CS:  0010 DS:  ES:  CR0: 80050033
> [9.753083] CR2: 0058 CR3: 00016922b000 CR4: 
> 003406f0
> [9.754782] Stack:
> [9.755332]  88008a9edc98 88008a9ed800 a01d07b0 
> fffb9
> 09e
> [9.757232]  88016a1af7d8 a0154ea7 0246 
> 88016a370
> 080
> [9.759182]  88016a370080 88008a9ed800 0246 
> 88008a9ed
> c98
> [9.761132] Call Trace:
> [9.761782]  [] intel_prepare_ddi+0x67/0x860 [i915]
> [9.763332]  [] ? _raw_spin_unlock_irqrestore+0x26/0x40
> [9.765031]  [] ? gen9_read32+0x141/0x360 [i915]
> [9.766531]  [] skl_set_power_well+0x431/0xa80 [i915]
> [9.768181]  [] skl_power_well_enable+0x13/0x20 [i915]
> [9.769781]  [] intel_power_well_enable+0x28/0x50 [i915]
> [9.771481]  [] intel_display_power_get+0x92/0xc0 [i915]
> [9.773180]  [] intel_display_set_init_power+0x3b/0x40 
> [i91
> 5]
> [9.774980]  [] intel_power_domains_init_hw+0x120/0x520 
> [i9
> 15]
> [9.776780]  [] i915_driver_load+0xb21/0xf40 [i915]
>
> So let's protect this case.
>
> My first attempt was to remove the intel_prepare_ddi, but Daniel had pointed 
> out
> this is really needed to restore those registers values. And Imre pointed out
> that this case was without the flag protection and this was actually where 
> things
> were going bad. So I've just checked and this indeed solves my issue.
>
> Cc: Imre Deak 
> Cc: Daniel Vetter 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 85c35fd..d194492 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -246,7 +246,8 @@ static void skl_power_well_post_enable(struct 
> drm_i915_private *dev_priv,
>   }
>  
>   if (power_well->data == SKL_DISP_PW_1) {
> - intel_prepare_ddi(dev);
> + if (!dev_priv->power_domains.initializing)
> + intel_prepare_ddi(dev);
>   gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
>   }
>  }
> -- 
> 2.4.3
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 3/7] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4f3942f..3bc14fa 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -807,6 +807,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
 
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
+   /* WaDisableAsyncFlipPerfMode:bdw,chv */
+   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
return 0;
 }
 
@@ -820,9 +823,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisableAsyncFlipPerfMode:bdw */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -889,9 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisableAsyncFlipPerfMode:chv */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-- 
1.9.1

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[Intel-gfx] [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA to common init fn

[Arun Siluvery]

Move WaDisablePartialInstShootdown and WaDisableThreadStallDopClockGating

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a06788a..5d15e31 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -807,6 +807,12 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
 
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
+   /* WaDisablePartialInstShootdown:bdw,chv */
+   /* WaDisableThreadStallDopClockGating:chv, bdw (pre-production) */
+   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+ STALL_DOP_GATING_DISABLE);
+
/* WaDisableAsyncFlipPerfMode:bdw,chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
@@ -826,12 +832,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisablePartialInstShootdown:bdw */
-   /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
-
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  DOP_CLOCK_GATING_DISABLE);
@@ -888,12 +888,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisablePartialInstShootdown:chv */
-   /* WaDisableThreadStallDopClockGating:chv */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
- STALL_DOP_GATING_DISABLE);
-
/* Use Force Non-Coherent whenever executing a 3D context. This is a
 * workaround for a possible hang in the unlikely event a TLB
 * invalidation occurs during a PSD flush.
-- 
1.9.1

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[Intel-gfx] [PATCH 4/7] drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3bc14fa..a06788a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -810,6 +810,9 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
/* WaDisableAsyncFlipPerfMode:bdw,chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
+   /* Wa4x4STCOptimizationDisable:bdw,chv */
+   WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
return 0;
 }
 
@@ -860,10 +863,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
 */
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 
-   /* Wa4x4STCOptimizationDisable:bdw */
-   WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/*
 * BSpec recommends 8x4 when MSAA is used,
 * however in practice 16x4 seems fastest.
@@ -910,10 +909,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
 */
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 
-   /* Wa4x4STCOptimizationDisable:chv */
-   WA_SET_BIT_MASKED(CACHE_MODE_1,
- GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 2/7] drm/i915/gen8: Move INSTPM WA to common function

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 10f9ea0..4f3942f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -802,6 +802,10 @@ static int wa_add(struct drm_i915_private *dev_priv,
 
 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 {
+   struct drm_device *dev = ring->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
return 0;
 }
@@ -816,8 +820,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:bdw */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
@@ -887,8 +889,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
/* WaDisableAsyncFlipPerfMode:chv */
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

[Arun Siluvery]

Changes that add new WA, merge WA that are applied for the same register,
update stepping checks and remove pre-production ones .

Arun Siluvery (12):
  drm/i915/gen9: Handle error returned by gen9_init_workarounds
  drm/i915/gen9: Add WaOCLCoherentLineFlush
  drm/i915/gen9: Merge two WA as they part of same register
  drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA
  drm/i915/bxt: update WaSetHDCunitClckGatingDisable
  drm/i915/bxt: Add WaStoreMultiplePTEenable name
  drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating
  drm/i915/skl: Remove WaDisableSDEUnitClockGating
  drm/i915/skl: Remove WaSetGAPSunitClckGateDisable
  drm/i915/skl: Remove WaDisableVFUnitClockGating
  drm/i915/skl: Remove
WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
  drm/i915:skl: Remove WaDisablePowerCompilerClockGating

 drivers/gpu/drm/i915/i915_reg.h |  2 --
 drivers/gpu/drm/i915/intel_lrc.c|  5 ++-
 drivers/gpu/drm/i915/intel_pm.c | 48 --
 drivers/gpu/drm/i915/intel_ringbuffer.c | 61 -
 4 files changed, 52 insertions(+), 64 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ab5ac5e..093a5e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
/* WaDisableKillLogic:bxt,skl */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
   ECOCHK_DIS_TLB);
+
+   /* WaOCLCoherentLineFlush:skl,bxt */
+   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+   GEN8_LQSC_FLUSH_COHERENT_LINES));
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
-- 
1.9.1

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[Intel-gfx] [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

[Arun Siluvery]

Dropping it because it is for pre-production stepping, also removed
bit definition in i915_reg as it is not used anywhere else.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 -
 drivers/gpu/drm/i915/intel_pm.c | 6 --
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 085ffa2..ef3d71f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6705,7 +6705,6 @@ enum skl_disp_power_wells {
 #define GEN6_RSTCTL0x9420
 
 #define GEN8_UCGCTL6   0x9430
-#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE  (1<<14)
 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6ee0d3..65c60bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -76,12 +76,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
gen9_init_clock_gating(dev);
 
if (INTEL_REVID(dev) <= SKL_REVID_B0) {
-   /*
-* WaSetGAPSunitClckGateDisable:skl
-*/
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
-
/* WaDisableVFUnitClockGating:skl */
I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
-- 
1.9.1

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[Intel-gfx] [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

[Arun Siluvery]

The implementation for this WA is same as 
WaSetHdcUnitClockGatingDisableInUcgctl6.
Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6
is applicable only when either SS0 or SS2 is active but if we apply the former 
WA
then the latter one also gets applied irrespective of which SS is enabled.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_pm.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 093a5e4..c73d37d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
-   /*
-* FIXME:
-* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
+   /* WaSetHDCunitClckGatingDisable:bxt */
+   /* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
+   /* The implementation is same for both of these WA except that
+* WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when
+* either SS0 or SS2 is active but if we apply the first one then the
+* second one also gets applied irrespective of which SS is enabled.
 */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+   if (INTEL_REVID(dev) == BXT_REVID_A0) {
+   I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+ 
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
+   }
 
if (INTEL_REVID(dev) == BXT_REVID_A0) {
/*
-- 
1.9.1

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[Intel-gfx] [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdff606..6671800 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1026,10 +1026,13 @@ static int skl_tune_iz_hashing(struct intel_engine_cs 
*ring)
 
 static int skl_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   gen9_init_workarounds(ring);
+   ret = gen9_init_workarounds(ring);
+   if (ret)
+   return ret;
 
/* WaDisablePowerCompilerClockGating:skl */
if (INTEL_REVID(dev) == SKL_REVID_B0)
@@ -1066,10 +1069,13 @@ static int skl_init_workarounds(struct intel_engine_cs 
*ring)
 
 static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   gen9_init_workarounds(ring);
+   ret = gen9_init_workarounds(ring);
+   if (ret)
+   return ret;
 
/* WaDisableThreadStallDopClockGating:bxt */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-- 
1.9.1

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[Intel-gfx] [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Arun Siluvery]

Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name
as they are part of same register. This will save an entry in WA array.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ad16ef4..963b3ca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-   /* Syncing dependencies between camera and graphics:skl,bxt */
-   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
- GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
+   /* WA: Syncing dependencies between camera and graphics:skl,bxt */
+   /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
+   tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
+   if (IS_SKYLAKE(dev) ||
+   (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
+   tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
+   }
+   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);
 
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
INTEL_REVID(dev) == SKL_REVID_B0)) ||
@@ -967,13 +972,6 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*ring)
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
-   /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
-   if (IS_SKYLAKE(dev) ||
-   (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
-   WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
- GEN8_SAMPLER_POWER_BYPASS_DIS);
-   }
-
/* WaDisableSTUnitPowerOptimization:skl,bxt */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d5fdbc8..2a33b9d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1019,11 +1019,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
*ring)
if (ret)
return ret;
 
-   /* WaDisablePowerCompilerClockGating:skl */
-   if (INTEL_REVID(dev) == SKL_REVID_B0)
-   WA_SET_BIT_MASKED(HIZ_CHICKEN,
- BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
-
if (INTEL_REVID(dev) <= SKL_REVID_D0) {
/*
 *Use Force Non-Coherent whenever executing a 3D context. This
-- 
1.9.1

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[Intel-gfx] [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping, also removed
bit definition in i915_reg.h as it is not used anywhere else.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 -
 drivers/gpu/drm/i915/intel_pm.c | 6 --
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef3d71f..b510fdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6688,7 +6688,6 @@ enum skl_disp_power_wells {
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE(1 << 7)
 
 #define GEN6_UCGCTL2   0x9404
-# define GEN6_VFUNIT_CLOCK_GATE_DISABLE(1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE   (1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE   (1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE   (1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 65c60bc..88acb3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -75,12 +75,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
gen9_init_clock_gating(dev);
 
-   if (INTEL_REVID(dev) <= SKL_REVID_B0) {
-   /* WaDisableVFUnitClockGating:skl */
-   I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
-  GEN6_VFUNIT_CLOCK_GATE_DISABLE);
-   }
-
if (INTEL_REVID(dev) <= SKL_REVID_D0) {
/* WaDisableHDCInvalidation:skl */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-- 
1.9.1

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[Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Arun Siluvery]

Dropping it as it is for pre-production stepping.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_lrc.c|  5 ++---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 256167b..e3baffd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs 
*ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-   if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
-   (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
+   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+   if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 963b3ca..d5fdbc8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*ring)
  GEN9_DG_MIRROR_FIX_ENABLE);
}
 
-   if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
-   (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
-   /* 
WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
- GEN9_RHWO_OPTIMIZATION_DISABLE);
-   /*
-* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
set
-* but we do that in per ctx batchbuffer as there is an issue
-* with this register not getting restored on ctx restore
-*/
-   }
-
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
IS_BROXTON(dev)) {
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
@@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*ring)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
 
+   /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+   if (INTEL_REVID(dev) < BXT_REVID_B0) {
+   WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+ GEN9_RHWO_OPTIMIZATION_DISABLE);
+   /*
+* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
set
+* but we do that in per ctx batchbuffer as there is an issue
+* with this register not getting restored on ctx restore
+*/
+   }
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Arun Siluvery]

It is also applicable for B0.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_pm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9151a2b..be39f7ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
gen9_init_clock_gating(dev);
 
/* WaDisableSDEUnitClockGating:bxt */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+   if (INTEL_REVID(dev) >= BXT_REVID_A0) {
+   I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+ GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
+   }
 
/* WaSetHDCunitClckGatingDisable:bxt */
/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
-- 
1.9.1

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[Intel-gfx] [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index be39f7ad..a6ee0d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -77,12 +77,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
if (INTEL_REVID(dev) <= SKL_REVID_B0) {
/*
-* WaDisableSDEUnitClockGating:skl
 * WaSetGAPSunitClckGateDisable:skl
 */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+  GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
 
/* WaDisableVFUnitClockGating:skl */
I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
-- 
1.9.1

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[Intel-gfx] [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

[Arun Siluvery]

Updated WA with the name.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_pm.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c73d37d..9151a2b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -136,13 +136,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
  
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
}
 
-   if (INTEL_REVID(dev) == BXT_REVID_A0) {
-   /*
-* Hardware specification requires this bit to be
-* set to 1 for A0
-*/
+   /* WaStoreMultiplePTEenable:bxt */
+   /* This is a requirement according to Hardware specification */
+   if (INTEL_REVID(dev) == BXT_REVID_A0)
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
-   }
 
/* WaSetClckGatingDisableMedia:bxt */
if (INTEL_REVID(dev) == BXT_REVID_A0) {
-- 
1.9.1

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[Intel-gfx] [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

[Arun Siluvery]

Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
an entry in WA array.

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6671800..ad16ef4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*ring)
}
 
/* Wa4x4STCOptimizationDisable:skl,bxt */
-   WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
/* WaDisablePartialResolveInVc:skl,bxt */
-   WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+   WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
+GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
/* WaCcsTlbPrefetchDisable:skl,bxt */
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
-- 
1.9.1

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[Intel-gfx] [PATCH v2 4/7] drm/i915: Always use crtc_ timings when dealing with adjustead_mode

[ville . syrjala]

From: Ville Syrjälä 

The adjustead_mode crtc_ timings are what we will program into the hardware,
so it's those timings we should be looking practically everywhere.

The normal and crtc_ timings should differ only when stere doubling is
used. In that case the normal timings are the orignal non-doubled
timigns, and crtc_ timings are the doubled timings used by the hardware.

The only case where we continue to look at the normal timings is when we
pass the adjusted_mode to drm_match_{cea,hdmi}_mode() to find the VIC.
drm_edid keeps the modes aronund in the non-double form only, so it
needs the non-double timings to match against.

Done with sed
's/adjusted_mode->\([vhVH]\)/adjusted_mode->crtc_\1/g'
's/adjusted_mode->clock/adjusted_mode->crtc_clock/g'
with a manual s/VDisplay/vdisplay/ within the comment in intel_dvo.c

v2: Update due to intel_dsi.c changes

Reviewed-by: Mika Kahola 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/dvo_ivch.c  |  8 ++---
 drivers/gpu/drm/i915/intel_audio.c   |  4 +--
 drivers/gpu/drm/i915/intel_display.c |  4 +--
 drivers/gpu/drm/i915/intel_dp_mst.c  |  2 +-
 drivers/gpu/drm/i915/intel_dsi.c | 30 +--
 drivers/gpu/drm/i915/intel_dvo.c |  8 ++---
 drivers/gpu/drm/i915/intel_panel.c   | 58 ++--
 drivers/gpu/drm/i915/intel_sdvo.c|  4 +--
 8 files changed, 59 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index 732ce87..e082f75 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -414,16 +414,16 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
VR40_HORIZONTAL_INTERP_ENABLE);
 
-   if (mode->hdisplay != adjusted_mode->hdisplay ||
-   mode->vdisplay != adjusted_mode->vdisplay) {
+   if (mode->hdisplay != adjusted_mode->crtc_hdisplay ||
+   mode->vdisplay != adjusted_mode->crtc_vdisplay) {
uint16_t x_ratio, y_ratio;
 
vr01 |= VR01_PANEL_FIT_ENABLE;
vr40 |= VR40_CLOCK_GATING_ENABLE;
x_ratio = (((mode->hdisplay - 1) << 16) /
-  (adjusted_mode->hdisplay - 1)) >> 2;
+  (adjusted_mode->crtc_hdisplay - 1)) >> 2;
y_ratio = (((mode->vdisplay - 1) << 16) /
-  (adjusted_mode->vdisplay - 1)) >> 2;
+  (adjusted_mode->crtc_vdisplay - 1)) >> 2;
ivch_write(dvo, VR42, x_ratio);
ivch_write(dvo, VR41, y_ratio);
} else {
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 779f90c..e4c30e8 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -74,13 +74,13 @@ static u32 audio_config_hdmi_pixel_clock(const struct 
drm_display_mode *adjusted
int i;
 
for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
-   if (adjusted_mode->clock == hdmi_audio_clock[i].clock)
+   if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
break;
}
 
if (i == ARRAY_SIZE(hdmi_audio_clock)) {
DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, 
falling back to defaults\n",
- adjusted_mode->clock);
+ adjusted_mode->crtc_clock);
i = 1;
}
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f8605b9..91f88e9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4400,7 +4400,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id, DRM_ROTATE_0,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->hdisplay, adjusted_mode->vdisplay);
+   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
 }
 
 /**
@@ -6587,7 +6587,7 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 */
if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
-   adjusted_mode->hsync_start == adjusted_mode->hdisplay)
+   adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
return -EINVAL;
 
if (HAS_IPS(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index ff8ba55..cccf014 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -78,7 +78,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder 
*encoder,

[Intel-gfx] [PATCH v2 7/7] drm/i915: Add HDMI aspect ratio property for SDVO

[ville . syrjala]

From: Ville Syrjälä 

Handle the HDMI aspect ratio property the same way in the SDVO code
as we handle it in the HDMI code.

v2: Remove stray whitespace change

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c  |  9 -
 drivers/gpu/drm/i915/intel_modes.c |  9 +
 drivers/gpu/drm/i915/intel_sdvo.c  | 28 
 4 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c98ed81..ed66a4f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1300,6 +1300,7 @@ int intel_connector_update_modes(struct drm_connector 
*connector,
 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 void intel_attach_force_audio_property(struct drm_connector *connector);
 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+void intel_attach_aspect_ratio_property(struct drm_connector *connector);
 
 
 /* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index af231ed..3c5f2c9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2004,15 +2004,6 @@ static const struct drm_encoder_funcs 
intel_hdmi_enc_funcs = {
 };
 
 static void
-intel_attach_aspect_ratio_property(struct drm_connector *connector)
-{
-   if (!drm_mode_create_aspect_ratio_property(connector->dev))
-   drm_object_attach_property(>base,
-   connector->dev->mode_config.aspect_ratio_property,
-   DRM_MODE_PICTURE_ASPECT_NONE);
-}
-
-static void
 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector 
*connector)
 {
intel_attach_force_audio_property(connector);
diff --git a/drivers/gpu/drm/i915/intel_modes.c 
b/drivers/gpu/drm/i915/intel_modes.c
index 0e860f3..38a4c8c 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,12 @@ intel_attach_broadcast_rgb_property(struct drm_connector 
*connector)
 
drm_object_attach_property(>base, prop, 0);
 }
+
+void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+   if (!drm_mode_create_aspect_ratio_property(connector->dev))
+   drm_object_attach_property(>base,
+   connector->dev->mode_config.aspect_ratio_property,
+   DRM_MODE_PICTURE_ASPECT_NONE);
+}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index 857b1bd..c42b636 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -107,6 +107,11 @@ struct intel_sdvo {
bool color_range_auto;
 
/**
+* HDMI user specified aspect ratio
+*/
+   enum hdmi_picture_aspect aspect_ratio;
+
+   /**
 * This is set if we're going to treat the device as TV-out.
 *
 * While we have these nice friendly flags for output types that ought
@@ -1181,6 +1186,10 @@ static bool intel_sdvo_compute_config(struct 
intel_encoder *encoder,
if (intel_sdvo->is_tv)
i9xx_adjust_sdvo_tv_clock(pipe_config);
 
+   /* Set user selected PAR to incoming mode's member */
+   if (intel_sdvo->is_hdmi)
+   adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio;
+
return true;
 }
 
@@ -2043,6 +2052,23 @@ intel_sdvo_set_property(struct drm_connector *connector,
goto done;
}
 
+   if (property == connector->dev->mode_config.aspect_ratio_property) {
+   switch (val) {
+   case DRM_MODE_PICTURE_ASPECT_NONE:
+   intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+   break;
+   case DRM_MODE_PICTURE_ASPECT_4_3:
+   intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
+   break;
+   case DRM_MODE_PICTURE_ASPECT_16_9:
+   intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
+   break;
+   default:
+   return -EINVAL;
+   }
+   goto done;
+   }
+
 #define CHECK_PROPERTY(name, NAME) \
if (intel_sdvo_connector->name == property) { \
if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
@@ -2382,6 +2408,8 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo 
*intel_sdvo,
intel_attach_broadcast_rgb_property(>base.base);
intel_sdvo->color_range_auto = true;
}
+   intel_attach_aspect_ratio_property(>base.base);
+   intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
 }
 
 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
-- 
2.4.6

[Intel-gfx] [PATCH 6/7] drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++--
 1 file changed, 12 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5d15e31..c681c66 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -819,6 +819,18 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
/* Wa4x4STCOptimizationDisable:bdw,chv */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+   /*
+* BSpec recommends 8x4 when MSAA is used,
+* however in practice 16x4 seems fastest.
+*
+* Note that PS/WM thread counts depend on the WIZ hashing
+* disable bit, which we don't touch here, but it's good
+* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+*/
+   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+   GEN6_WIZ_HASHING_MASK,
+   GEN6_WIZ_HASHING_16x4);
+
return 0;
 }
 
@@ -863,18 +875,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
 */
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 
-   /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
-   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
-   GEN6_WIZ_HASHING_MASK,
-   GEN6_WIZ_HASHING_16x4);
-
return 0;
 }
 
@@ -906,18 +906,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-   /*
-* BSpec recommends 8x4 when MSAA is used,
-* however in practice 16x4 seems fastest.
-*
-* Note that PS/WM thread counts depend on the WIZ hashing
-* disable bit, which we don't touch here, but it's good
-* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
-*/
-   WA_SET_FIELD_MASKED(GEN7_GT_MODE,
-   GEN6_WIZ_HASHING_MASK,
-   GEN6_WIZ_HASHING_16x4);
-
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 7/7] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++---
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c681c66..fdff606 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -819,6 +819,16 @@ static int gen8_init_workarounds(struct intel_engine_cs 
*ring)
/* Wa4x4STCOptimizationDisable:bdw,chv */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
+* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
+*  polygons in the same 8x4 pixel/sample area to be processed without
+*  stalling waiting for the earlier ones to write to Hierarchical Z
+*  buffer."
+*
+* This optimization is off by default for BDW and CHV; turn it on.
+*/
+   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+
/*
 * BSpec recommends 8x4 when MSAA is used,
 * however in practice 16x4 seems fastest.
@@ -865,16 +875,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
-   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
-* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
-*  polygons in the same 8x4 pixel/sample area to be processed without
-*  stalling waiting for the earlier ones to write to Hierarchical Z
-*  buffer."
-*
-* This optimization is off by default for Broadwell; turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
return 0;
 }
 
@@ -898,11 +898,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
*ring)
  HDC_FORCE_NON_COHERENT |
  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
-   /* According to the CACHE_MODE_0 default value documentation, some
-* CHV platforms disable this optimization by default.  Turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 1/7] drm/i915/gen8: Add gen8_init_workarounds for common WA

[Arun Siluvery]

Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16a4ead..10f9ea0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -800,11 +800,22 @@ static int wa_add(struct drm_i915_private *dev_priv,
 
 #define WA_WRITE(addr, val) WA_REG(addr, 0x, val)
 
+static int gen8_init_workarounds(struct intel_engine_cs *ring)
+{
+
+   return 0;
+}
+
 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
+   ret = gen8_init_workarounds(ring);
+   if (ret)
+   return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
/* WaDisableAsyncFlipPerfMode:bdw */
@@ -868,9 +879,14 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
 
 static int chv_init_workarounds(struct intel_engine_cs *ring)
 {
+   int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
+   ret = gen8_init_workarounds(ring);
+   if (ret)
+   return ret;
+
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
/* WaDisableAsyncFlipPerfMode:chv */
-- 
1.9.1

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[Intel-gfx] [PATCH v2 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

[ville . syrjala]

From: Ville Syrjälä 

Rename the function argument to 'adjusted_mode' whenever the function
only ever gets passed the adjusted_mode.

v2: Update due to intel_dsi.c changes

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_audio.c  | 17 +
 drivers/gpu/drm/i915/intel_dsi.c| 22 +++---
 drivers/gpu/drm/i915/intel_panel.c  | 36 ++--
 drivers/gpu/drm/i915/intel_sdvo.c   |  6 +++---
 drivers/gpu/drm/i915/intel_sprite.c |  8 +---
 6 files changed, 47 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b5d587..d1e800a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -646,7 +646,7 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct drm_crtc *crtc);
void (*audio_codec_enable)(struct drm_connector *connector,
   struct intel_encoder *encoder,
-  struct drm_display_mode *mode);
+  const struct drm_display_mode 
*adjusted_mode);
void (*audio_codec_disable)(struct intel_encoder *encoder);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index d9876c5..779f90c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -69,17 +69,18 @@ static const struct {
 };
 
 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
-static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
+static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode 
*adjusted_mode)
 {
int i;
 
for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
-   if (mode->clock == hdmi_audio_clock[i].clock)
+   if (adjusted_mode->clock == hdmi_audio_clock[i].clock)
break;
}
 
if (i == ARRAY_SIZE(hdmi_audio_clock)) {
-   DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, 
falling back to defaults\n", mode->clock);
+   DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, 
falling back to defaults\n",
+ adjusted_mode->clock);
i = 1;
}
 
@@ -138,7 +139,7 @@ static void g4x_audio_codec_disable(struct intel_encoder 
*encoder)
 
 static void g4x_audio_codec_enable(struct drm_connector *connector,
   struct intel_encoder *encoder,
-  struct drm_display_mode *mode)
+  const struct drm_display_mode *adjusted_mode)
 {
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
@@ -203,7 +204,7 @@ static void hsw_audio_codec_disable(struct intel_encoder 
*encoder)
 
 static void hsw_audio_codec_enable(struct drm_connector *connector,
   struct intel_encoder *encoder,
-  struct drm_display_mode *mode)
+  const struct drm_display_mode *adjusted_mode)
 {
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -251,7 +252,7 @@ static void hsw_audio_codec_enable(struct drm_connector 
*connector,
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
-   tmp |= audio_config_hdmi_pixel_clock(mode);
+   tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 }
 
@@ -304,7 +305,7 @@ static void ilk_audio_codec_disable(struct intel_encoder 
*encoder)
 
 static void ilk_audio_codec_enable(struct drm_connector *connector,
   struct intel_encoder *encoder,
-  struct drm_display_mode *mode)
+  const struct drm_display_mode *adjusted_mode)
 {
struct drm_i915_private *dev_priv = connector->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -381,7 +382,7 @@ static void ilk_audio_codec_enable(struct drm_connector 
*connector,
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
-   tmp |= audio_config_hdmi_pixel_clock(mode);
+   tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
I915_WRITE(aud_config, tmp);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 23b7fc5..b4d5213 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ 

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

[Imre Deak]

On pe, 2015-09-25 at 10:56 +0200, Patrik Jakobsson wrote:
> On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote:
> > > > On Wed, Sep 23, 2015 at 10:43:00AM +0200, Daniel Vetter wrote:
> > > > > On Mon, Sep 21, 2015 at 10:00:45AM +0200, Patrik Jakobsson wrote:
> > > > > > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > > > > > > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > > > > > > > We need to be able to control if DC6 is allowed or not. Much 
> > > > > > > > like
> > > > > > > > requesting power to a specific piece of the hardware we need to 
> > > > > > > > be able
> > > > > > > > to request that we don't enter DC6 during certain hw access.
> > > > > > > > 
> > > > > > > > To solve this without introducing too much infrastructure I'm 
> > > > > > > > hooking
> > > > > > > > into the power well / power domain framework. DC6 prevention is 
> > > > > > > > modeled
> > > > > > > > much like an enabled power well. Thus I'm using the terminology 
> > > > > > > > on/off
> > > > > > > > for DC states instead of enable/disable.
> > > > > > > > 
> > > > > > > > The problem that started this work is the need for DC6 to be 
> > > > > > > > disabled
> > > > > > > > when accessing DP_AUX_A during CRTC on/off. That is also fixed 
> > > > > > > > in this
> > > > > > > > patch.
> > > > > > > > 
> > > > > > > > This is posted as an RFC since DMC and DC state handling is 
> > > > > > > > being
> > > > > > > > reworked and will possibly affect the outcome of this patch. 
> > > > > > > > The patch
> > > > > > > > has known warnings.
> > > > > > > > 
> > > > > > > > Signed-off-by: Patrik Jakobsson 
> > > > > > > > 
> > > > > > > > ---
> > > > > > > >  drivers/gpu/drm/i915/intel_ddi.c|  9 +
> > > > > > > >  drivers/gpu/drm/i915/intel_drv.h|  2 +
> > > > > > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 69 
> > > > > > > > +
> > > > > > > >  3 files changed, 64 insertions(+), 16 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > > > > > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > index 4823184..c2c1ad2 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > > > > > @@ -2288,6 +2288,8 @@ static void intel_ddi_pre_enable(struct 
> > > > > > > > intel_encoder *intel_encoder)
> > > > > > > > if (type == INTEL_OUTPUT_DISPLAYPORT || type == 
> > > > > > > > INTEL_OUTPUT_EDP) {
> > > > > > > > struct intel_dp *intel_dp = 
> > > > > > > > enc_to_intel_dp(encoder);
> > > > > > > >  
> > > > > > > > +   intel_display_power_get(dev_priv, 
> > > > > > > > POWER_DOMAIN_AUX_A);
> > > > > > > > +
> > > > > > > 
> > > > > > > These I think shouldn't be necessary with my
> > > > > > > intel_display_port_aux_power_domain() stuff since 
> > > > > > > intel_dp_aux_ch() will
> > > > > > > itself grab the appropriate power domain.
> > > > > > > 
> > > > > > > That's of course assuming that AUX is the only reason why we need 
> > > > > > > to
> > > > > > > keep DC6 disabled here.
> > > > > > > 
> > > > > > 
> > > > > > The upside with having get/put around bigger aux transfers is that 
> > > > > > we don't get
> > > > > > tons of enable/disable lines in the log. My vote is that we keep 
> > > > > > this but also
> > > > > > have your fine-grained get/puts.
> > > > > 
> > > > > Imo the correct solution to avoid this is by adding a slight bit of
> > > > > hystersis to the power well code. Which means that yes, we reinvent
> > > > > another feature of the core power_domain code in our home-grown 
> > > > > solution -
> > > > > I hate it when my years old predictions come true ;-)
> > > > > 
> > > > > Sprinkling higher-level get/put calls all over the place is imo just
> > > > > leaking the abstraction, which isn't good.
> > > > > -Daniel
> > > > 
> > > > With Ville's patches the problem is not as bad as I first thought. We 
> > > > can add
> > > > hysteresis later if needed.
> > > > 
> > > > -Patrik
> > > 
> > > So I discovered that we cannot have DC5 and DC6 as seperate power wells 
> > > since
> > > they are mutually exclusive. As Ville pointed out we don't use DC5 for 
> > > anything
> > > so we could get away for now with just DC6 as a power well.
> > > 
> > > As I see it there are three ways to go about this:
> > > 
> > > A. Add AUX A to Power well 2.
> > > This would power up PW2 during DP Aux A even though we don't need it but 
> > > since
> > > we get the side effect of DC6 being disabled it should work.
> > > 
> > > B. Add DC6 off as a power well and remove DC5 off.
> > > Fairly straight forward but assumes we don't need DC5 control.
> > > 
> > > C. Add multi-state support for the DC power well.
> > > 

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

[Tvrtko Ursulin]

On 09/24/2015 05:35 PM, Ville Syrjälä wrote:

On Mon, Sep 21, 2015 at 10:45:34AM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Just adding the rotated UV plane at the end of the rotated Y plane.

v2: Rebase.

Signed-off-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_gem_gtt.c  | 37 ++--
  drivers/gpu/drm/i915/i915_gem_gtt.h  |  3 +++
  drivers/gpu/drm/i915/intel_display.c | 12 
  3 files changed, 46 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 59c934fb9230..2df9d16dcefd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3272,10 +3272,13 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
*ggtt_view,
  {
struct intel_rotation_info *rot_info = _view->rotation_info;
unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
+   unsigned int size_pages_uv;
struct sg_page_iter sg_iter;
unsigned long i;
dma_addr_t *page_addr_list;
struct sg_table *st;
+   unsigned int uv_start_page;
+   struct scatterlist *sg;
int ret = -ENOMEM;

/* Allocate a temporary list of source pages for random access. */
@@ -3284,12 +3287,18 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
*ggtt_view,
if (!page_addr_list)
return ERR_PTR(ret);

+   /* Account for UV plane with NV12. */
+   if (rot_info->pixel_format == DRM_FORMAT_NV12)
+   size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
+   else
+   size_pages_uv = 0;
+
/* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
goto err_st_alloc;

-   ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
+   ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
if (ret)
goto err_sg_alloc;

@@ -3301,15 +3310,30 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view 
*ggtt_view,
}

/* Rotate the pages. */
-   rotate_pages(page_addr_list, 0,
+   sg = rotate_pages(page_addr_list, 0,
 rot_info->width_pages, rot_info->height_pages,
 st, NULL);

+   /* Append the UV plane if NV12. */
+   if (rot_info->pixel_format == DRM_FORMAT_NV12) {
+   uv_start_page = size_pages;
+
+   /* Check for tile-row un-alignment. */
+   if (offset_in_page(rot_info->uv_offset))
+   uv_start_page--;
+
+   rotate_pages(page_addr_list, uv_start_page,
+rot_info->width_pages_uv,
+rot_info->height_pages_uv,
+st, sg);
+   }
+
DRM_DEBUG_KMS(
- "Created rotated page mapping for object size %zu (pitch=%u, 
height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
+ "Created rotated page mapping for object size %zu (pitch=%u, 
height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
  obj->base.size, rot_info->pitch, rot_info->height,
  rot_info->pixel_format, rot_info->width_pages,
- rot_info->height_pages, size_pages);
+ rot_info->height_pages, size_pages + size_pages_uv,
+ size_pages);

drm_free_large(page_addr_list);

@@ -3321,10 +3345,11 @@ err_st_alloc:
drm_free_large(page_addr_list);

DRM_DEBUG_KMS(
- "Failed to create rotated mapping for object size %zu! (%d) 
(pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
+ "Failed to create rotated mapping for object size %zu! (%d) 
(pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
  obj->base.size, ret, rot_info->pitch, rot_info->height,
  rot_info->pixel_format, rot_info->width_pages,
- rot_info->height_pages, size_pages);
+ rot_info->height_pages, size_pages + size_pages_uv,
+ size_pages);
return ERR_PTR(ret);
  }

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 82750073d5b3..197183d5c543 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -138,10 +138,13 @@ enum i915_ggtt_view_type {
  struct intel_rotation_info {
unsigned int height;
unsigned int pitch;
+   unsigned int uv_offset;
uint32_t pixel_format;
uint64_t fb_modifier;
unsigned int width_pages, height_pages;
uint64_t size;
+   unsigned int width_pages_uv, height_pages_uv;
+   uint64_t size_uv;
  };

  struct i915_ggtt_view {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 

[Intel-gfx] Link training error with 4.3.rc2+

[Arun Siluvery]

Hi,

With 4.3.rc2+ I am seeing below WARN followed by a link training error 
when the login screen comes up on ubuntu. Once I get the error log in 
console screen goes blank and stays that way. I am also not able to get 
to virtual terminal.


The panel connected is eDP.

[   67.279643] ACPI: Video Device [GFX0] (multi-head: yes  rom: no post: no)
[   67.279951] input: Video Bus as 
/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input9
[   67.280054] [drm] Initialized i915 1.6.0 20150911 for :00:02.0 on 
minor 0

[   67.327150] fbcon: inteldrmfb (fb0) is primary device
[   67.327285] [ cut here ]
[   67.327328] WARNING: CPU: 0 PID: 40 at 
drivers/gpu/drm/i915/intel_uncore.c:619 
hsw_unclaimed_reg_debug.isra.14+0x70/0x90 [i915]()

[   67.327329] Unclaimed register detected after writing to register 0x68970
[   67.327361] Modules linked in: asix usbnet mii i915(E) intel_rapl 
iosf_mbi x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel 
hid_generic kvm crct10dif_pclmul crc32_pclmul ghash_clmulni_intel 
aesni_intel aes_x86_64 lrw gf128mul glue_helper ablk_helper cryptd 
drm_kms_helper drm serio_raw i2c_algo_bit fb_sys_fops usbhid syscopyarea 
sysfillrect sysimgblt mei_me mei wmi i2c_hid hid soc_button_array 
winbond_cir rc_core 8250_fintek video acpi_pad mac_hid parport_pc ppdev 
lp parport autofs4 e1000e ahci sdhci_pci ptp libahci psmouse pps_core sdhci
[   67.327363] CPU: 0 PID: 40 Comm: kworker/u16:1 Tainted: GW E 
  4.3.0-rc2+ #3

[   67.327367] Workqueue: events_unbound async_run_entry_fn
[   67.327370]  c04c0fa0 88007546f750 8139bc1d 
88007546f798
[   67.327371]  88007546f788 81077d56 880079cc0078 
00068970
[   67.327372]  00068970 880079cc0078 880079cc0080 
88007546f7e8

[   67.327373] Call Trace:
[   67.327377]  [] dump_stack+0x44/0x57
[   67.327378]  [] warn_slowpath_common+0x86/0xc0
[   67.327380]  [] warn_slowpath_fmt+0x4c/0x50
[   67.327404]  [] 
hsw_unclaimed_reg_debug.isra.14+0x70/0x90 [i915]

[   67.327425]  [] gen9_write32+0x12d/0x310 [i915]
[   67.327456]  [] skl_detach_scaler.isra.12+0x74/0xb0 
[i915]

[   67.327484]  [] skl_detach_scalers+0x63/0x70 [i915]
[   67.327497]  [] intel_begin_crtc_commit+0xab/0x1f0 
[i915]
[   67.327502]  [] 
drm_atomic_helper_commit_planes_on_crtc+0x5b/0x230 [drm_kms_helper]

[   67.327519]  [] intel_atomic_commit+0x2a0/0x1ed0 [i915]
[   67.327521]  [] ? __ww_mutex_lock+0x5f/0x97
[   67.327546]  [] ? drm_atomic_check_only+0x158/0x580 
[drm]
[   67.327554]  [] ? 
drm_atomic_add_affected_connectors+0x27/0xf0 [drm]

[   67.327577]  [] drm_atomic_commit+0x37/0x60 [drm]
[   67.327580]  [] restore_fbdev_mode+0x27e/0x2c0 
[drm_kms_helper]
[   67.327583]  [] 
drm_fb_helper_restore_fbdev_mode_unlocked+0x33/0x80 [drm_kms_helper]
[   67.327586]  [] drm_fb_helper_set_par+0x2c/0x50 
[drm_kms_helper]

[   67.327604]  [] intel_fbdev_set_par+0x1a/0x60 [i915]
[   67.327605]  [] fbcon_init+0x4c6/0x550
[   67.327608]  [] visual_init+0xca/0x130
[   67.327609]  [] do_bind_con_driver+0x146/0x310
[   67.327611]  [] do_take_over_console+0x141/0x1b0
[   67.327611]  [] do_fbcon_takeover+0x57/0xb0
[   67.327612]  [] fbcon_event_notify+0x60b/0x750
[   67.327614]  [] notifier_call_chain+0x49/0x70
[   67.327615]  [] 
__blocking_notifier_call_chain+0x4d/0x70

[   67.327617]  [] blocking_notifier_call_chain+0x16/0x20
[   67.327618]  [] fb_notifier_call_chain+0x1b/0x20
[   67.327619]  [] register_framebuffer+0x1de/0x300
[   67.327622]  [] 
drm_fb_helper_initial_config+0x258/0x3c0 [drm_kms_helper]
[   67.327638]  [] 
intel_fbdev_initial_config+0x1b/0x20 [i915]

[   67.327639]  [] async_run_entry_fn+0x48/0x150
[   67.327640]  [] process_one_work+0x14e/0x3d0
[   67.327641]  [] worker_thread+0x11a/0x470
[   67.327642]  [] ? __schedule+0x358/0x920
[   67.327643]  [] ? rescuer_thread+0x310/0x310
[   67.327644]  [] kthread+0xc9/0xe0
[   67.327645]  [] ? kthread_park+0x60/0x60
[   67.327647]  [] ret_from_fork+0x3f/0x70
[   67.327648]  [] ? kthread_park+0x60/0x60
[   67.327648] ---[ end trace 710ab680f03a2d12 ]---
[   67.377298] Console: switching to colour frame buffer device 400x112
[   67.385538] i915 :00:02.0: fb0: inteldrmfb frame buffer device
[   67.541546] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[   67.667504] systemd-journald[270]: Received request to flush runtime 
journal from PID 1
[   67.795077] audit: type=1400 audit(1443155408.705:2): 
apparmor="STATUS" operation="profile_load" 
name="/usr/lib/lightdm/lightdm-guest-session" pid=440 comm="apparmor_parser"
[   67.795082] audit: type=1400 audit(1443155408.705:3): 
apparmor="STATUS" operation="profile_load" name="chromium" pid=440 
comm="apparmor_parser"
[   67.796436] audit: type=1400 audit(1443155408.709:4): 
apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=440 
comm="apparmor_parser"
[   67.796441] audit: type=1400 audit(1443155408.709:5): 
apparmor="STATUS" 

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add max DOT clock frequency to debugfs

[Mika Kahola]

On Thu, 2015-09-24 at 23:49 +0300, Ville Syrjälä wrote:
> On Thu, Sep 24, 2015 at 02:28:41PM +0300, Mika Kahola wrote:
> > Information on maximum supported pixel clock frequency to
> > i915_frequency_info.
> > 
> > Signed-off-by: Mika Kahola 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 6882455..b418d9b 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1311,6 +1311,7 @@ static int i915_frequency_info(struct seq_file *m, 
> > void *unused)
> >  
> > seq_printf(m, "Current CD clock freq: %dkHz\n", dev_priv->cdclk_freq);
> > seq_printf(m, "Max CD clock freq: %dkHz\n", dev_priv->max_cdclk_freq);
> > +   seq_printf(m, "Max pixel clock freq: %dkHz\n", 
> > dev_priv->max_dotclk_freq);
> 
> I would put a space between the number and units.
> 
> The rest of the stuff in there is about the gt stuff, so not sure if
> this is the best place for it. But if no one else objects, I won't either.
> 
> Could probably squash all three patches into just one, since they're all
> doing the same thing anyway.
> 
> With that these are:
> Reviewed-by: Ville Syrjälä 
> 
Thanks! These patches are leftovers from the CD clock and mode validity
patch series. I'll combine all these three patches to one patch.

-Mika-

> >  
> >  out:
> > intel_runtime_pm_put(dev_priv);
> > -- 
> > 1.9.1
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [Intel-gfx] [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI backlight support

[Shankar, Uma]

>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Thursday, September 24, 2015 10:29 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI
>backlight support
>
>On Wed, Sep 23, 2015 at 11:30:43PM +0530, Uma Shankar wrote:
>> DSI backlight support for bxt is added.
>>
>> TODO: There is no support for backlight control in drm panel
>>   framework. This will be added as part of VBT version patches
>>   fixing the backlight sequence.
>>
>> v2: Fixed Jani's review comments from previous patch. Added the
>> BXT DSI backlight code in this patch. Backlight setup and
>> enable/disable code for backlight is added in intel_dsi.c.
>>
>> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
>>
>> v4: Making backlight calls generic as per Jani's suggestion.
>>
>> Signed-off-by: Uma Shankar 
>> ---
>>  drivers/gpu/drm/i915/intel_dsi.c |   20 +++-
>>  1 file changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> b/drivers/gpu/drm/i915/intel_dsi.c
>> index 08bade2..3e7f796 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder
>*encoder)
>>  struct drm_device *dev = encoder->base.dev;
>>  struct drm_i915_private *dev_priv = dev->dev_private;
>>  struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>> +struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>>  enum port port;
>>
>>  DRM_DEBUG_KMS("\n");
>> @@ -458,6 +459,9 @@ static void intel_dsi_enable(struct intel_encoder
>> *encoder)
>>
>>  intel_dsi_port_enable(encoder);
>>  }
>> +
>> +msleep(intel_dsi->backlight_on_delay);
>> +intel_panel_enable_backlight(intel_connector);
>>  }
>>
>>  static void intel_dsi_pre_enable(struct intel_encoder *encoder) @@
>> -623,10 +627,14 @@ static void intel_dsi_post_disable(struct
>> intel_encoder *encoder)  {
>>  struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>>  struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>> +struct intel_connector *intel_connector =
>> +intel_dsi->attached_connector;
>>  u32 val;
>>
>>  DRM_DEBUG_KMS("\n");
>>
>> +intel_panel_disable_backlight(intel_connector);
>> +msleep(intel_dsi->backlight_off_delay);
>> +
>>  intel_dsi_disable(encoder);
>>
>>  intel_dsi_clear_device_ready(encoder);
>> @@ -1226,8 +1234,18 @@ void intel_dsi_init(struct drm_device *dev)
>>
>>  intel_panel_init(_connector->panel, fixed_mode, NULL);
>>
>> -return;
>> +/*
>> + * Pipe parameter is not used for BXT.
>> + * Passing INVALID_PIPE to adher to API requirement.
>> + */
>> +if (IS_BROXTON(dev))
>> +intel_panel_setup_backlight(connector, INVALID_PIPE);
>> +else
>> +intel_panel_setup_backlight(connector,
>> +intel_encoder->crtc_mask == (1 << PIPE_A) ?
>> +PIPE_A : PIPE_B);
>
>Is this aganst some ancient kernel version? We have backlight calls in the dsi
>code already.
>

This support is added recently with Shobhit's "backlight control using CRC PMIC
Based PWM driver" series.  This seems to be merged last week. We can drop this 
patch,
as it is already taken care in nightly branch. 

Regards,
Uma Shankar

>> +return;
>>  err:
>>  drm_encoder_cleanup(_encoder->base);
>>  kfree(intel_dsi);
>> --
>> 1.7.9.5
>>
>> ___
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel OTC
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Re: [Intel-gfx] [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA to common init fn

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:23:32PM +0100, Arun Siluvery wrote:
> Move WaDisablePartialInstShootdown and WaDisableThreadStallDopClockGating

NAK for WaDisableThreadStallDopClockGating, we don't want it on production BDW.
Should just kill it for BDW instead.

> 
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++
>  1 file changed, 6 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a06788a..5d15e31 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -807,6 +807,12 @@ static int gen8_init_workarounds(struct intel_engine_cs 
> *ring)
>  
>   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>  
> + /* WaDisablePartialInstShootdown:bdw,chv */
> + /* WaDisableThreadStallDopClockGating:chv, bdw (pre-production) */
> + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> +   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> +   STALL_DOP_GATING_DISABLE);
> +
>   /* WaDisableAsyncFlipPerfMode:bdw,chv */
>   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>  
> @@ -826,12 +832,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   if (ret)
>   return ret;
>  
> - /* WaDisablePartialInstShootdown:bdw */
> - /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> -   STALL_DOP_GATING_DISABLE);
> -
>   /* WaDisableDopClockGating:bdw */
>   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
> @@ -888,12 +888,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
> *ring)
>   if (ret)
>   return ret;
>  
> - /* WaDisablePartialInstShootdown:chv */
> - /* WaDisableThreadStallDopClockGating:chv */
> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> -   STALL_DOP_GATING_DISABLE);
> -
>   /* Use Force Non-Coherent whenever executing a 3D context. This is a
>* workaround for a possible hang in the unlikely event a TLB
>* invalidation occurs during a PSD flush.
> -- 
> 1.9.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH 7/7] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:23:34PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++---
>  1 file changed, 10 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c681c66..fdff606 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -819,6 +819,16 @@ static int gen8_init_workarounds(struct intel_engine_cs 
> *ring)
>   /* Wa4x4STCOptimizationDisable:bdw,chv */
>   WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
>  
> + /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> +  * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
> +  *  polygons in the same 8x4 pixel/sample area to be processed without
> +  *  stalling waiting for the earlier ones to write to Hierarchical Z
> +  *  buffer."
> +  *
> +  * This optimization is off by default for BDW and CHV; turn it on.
> +  */
> + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> +

Ok, so apart from the threadstall thing the rest looks reasonable.
One request though, can you put w/as into some decent order? I
suggest ordering based on the register, so eg.

instpm
mi_mode
row chicken
half slice chicken
common slice chicken
hdc chicken
cache_mode_0
cache_mode_1
gt_mode

I think that should match reasonably well what we have in most places.
Or you can come up with something better if you wish, as long as the
same/similar registers are grouped decently.

>   /*
>* BSpec recommends 8x4 when MSAA is used,
>* however in practice 16x4 seems fastest.
> @@ -865,16 +875,6 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
> /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>  
> - /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> -  * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
> -  *  polygons in the same 8x4 pixel/sample area to be processed without
> -  *  stalling waiting for the earlier ones to write to Hierarchical Z
> -  *  buffer."
> -  *
> -  * This optimization is off by default for Broadwell; turn it on.
> -  */
> - WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> -
>   return 0;
>  }
>  
> @@ -898,11 +898,6 @@ static int chv_init_workarounds(struct intel_engine_cs 
> *ring)
> HDC_FORCE_NON_COHERENT |
> HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>  
> - /* According to the CACHE_MODE_0 default value documentation, some
> -  * CHV platforms disable this optimization by default.  Turn it on.
> -  */
> - WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> -
>   /* Improve HiZ throughput on CHV. */
>   WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>  
> -- 
> 1.9.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Add GuC css header parser

[Jani Nikula]

On Wed, 16 Sep 2015, yu@intel.com wrote:
> From: Alex Dai 
>
> By using information from GuC css header, we can eliminate some
> hard code w.r.t size of some components of firmware.

There's a catch here. You can't trust any of the firmware blob
contents. None at all. It's all malicious user input as far as the
kernel is concerned, and we don't have the means to check the signature.

I like the use of the __packed struct here, and I like making this more
dynamic. But you have to check the bounds for everything you use from
the css header.

BR,
Jani.


>
> v2: Add indent into DOC to make fixed-width format rather than
> change the tmpl.
>
> v1: 1) guc_css_header is defined as __packed now
> 2) Add and correct GuC related topics in kernel/Doc
>
> Signed-off-by: Alex Dai 
> ---
>  Documentation/DocBook/drm.tmpl  |   9 ++-
>  drivers/gpu/drm/i915/intel_guc.h|   2 +-
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  36 +++
>  drivers/gpu/drm/i915/intel_guc_loader.c | 107 
> ++--
>  4 files changed, 117 insertions(+), 37 deletions(-)
>
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index 66bc646..116332f 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4155,14 +4155,19 @@ int num_ioctls;
>GuC-based Command Submission
>
>  GuC
> -!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader
> +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC
>  !Idrivers/gpu/drm/i915/intel_guc_loader.c
>
>
>  GuC Client
> -!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submissison
> +!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC Client
>  !Idrivers/gpu/drm/i915/i915_guc_submission.c
>
> +  
> +GuC Firmware Layout
> +!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC Firmware Layout
> +!Idrivers/gpu/drm/i915/intel_guc_loader.c
> +  
>  
>  
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc.h 
> b/drivers/gpu/drm/i915/intel_guc.h
> index 4ec2d27..e1389fc 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -71,6 +71,7 @@ struct intel_guc_fw {
>   struct drm_i915_gem_object *guc_fw_obj;
>   enum intel_guc_fw_statusguc_fw_fetch_status;
>   enum intel_guc_fw_statusguc_fw_load_status;
> + struct guc_css_header   guc_fw_header;
>  
>   uint16_tguc_fw_major_wanted;
>   uint16_tguc_fw_minor_wanted;
> @@ -80,7 +81,6 @@ struct intel_guc_fw {
>  
>  struct intel_guc {
>   struct intel_guc_fw guc_fw;
> -
>   uint32_t log_flags;
>   struct drm_i915_gem_object *log_obj;
>  
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index e1f47ba..006dc0d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -122,6 +122,42 @@
>  
>  #define GUC_CTL_MAX_DWORDS   (GUC_CTL_RSRVD + 1)
>  
> +struct guc_css_header {
> + uint32_t module_type;
> + uint32_t header_len; /* header length plus size of all other keys */
> + uint32_t header_version;
> + uint32_t module_id;
> + uint32_t module_vendor;
> + union {
> + struct {
> + uint8_t day;
> + uint8_t month;
> + uint16_t year;
> + };
> + uint32_t date;
> + };
> + uint32_t size; /* uCode size plus header_len */
> + uint32_t key_size;
> + uint32_t modulus_size;
> + uint32_t exponent_size;
> + union {
> + struct {
> + uint8_t hour;
> + uint8_t min;
> + uint16_t sec;
> + };
> + uint32_t time;
> + };
> +
> + char username[8];
> + char buildnumber[12];
> + uint32_t device_id;
> + uint32_t guc_sw_version;
> + uint32_t prod_preprod_fw;
> + uint32_t reserved[12];
> + uint32_t header_info;
> +} __packed;
> +
>  struct guc_doorbell_info {
>   u32 db_status;
>   u32 cookie;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 40241f3..a6703b4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -215,18 +215,29 @@ static inline bool guc_ucode_response(struct 
> drm_i915_private *dev_priv,
>   ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
>  }
>  
> -/*
> - * Transfer the firmware image to RAM for execution by the microcontroller.
> +/**
> + * DOC: GuC Firmware Layout
>   *
> - * GuC Firmware layout:
> - * +---+  
> - * |  CSS header   |  128B
> - * | contains major/minor version  |
> - * +---+  
> - * |