Re: [PEDA] What's wrong with my query language program
you need to you use the abs value of each coordinate Bevan Weiss wrote: - Original Message - From: Mr. Zhang Yangtian [EMAIL PROTECTED] To: Protel [EMAIL PROTECTED] Sent: Thursday, February 12, 2004 4:47 AM Subject: [PEDA] What's wrong with my query language program I had write one line of query language in ProtelDXP as the following: IsTrack and ((ABS(X1-X2)-ABS(Y1-Y2))=0) Its target is to find out all the tracks with their lean at 45-degree or 135-degree. After the execution of the program, some tracks are found while some tracks satisfied with the constrain are leaked. I guess that the reason is the precision of floating point number calculation. So I change it to the following format: IsTrack and ((ABS(X1-X2)-ABS(Y1-Y2)) between -1 and 1). But this time, strange things happen: the queried tracks are nearlly all the tracks with 0 degree, not 45-degree or 135-degree. Who can tell me why. Is it a bug of DXP? Thank you very much! Why are you using subtraction?? surely it then matters what the absolute lengths of the track are... Perhaps the following would work: IsTrack and ((ABS(Y2 - Y1) / ABS (X2 - X1)) = 1) (you could also use a trig function to make it more understandable ie if available use (ARCTAN((ABS(Y2-Y1) / ABS(X2-X1)) = 45), the use of the absolute values for both X and Y directions constrains the angle to the upper right quadrant, ie angles between 0 and 90degrees. Bevan -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [dxp] Controll Connection to Plane by Area
A virtual short on the back side of the pwb (this would require breaking up pwr and gnd nets) or, Define a split plane inclosing the pins you dont want connected which would be associated to a phony net JaMi Smith wrote: Is there a way to control the connection to Planes, or specifically forbid them, by defining a physical area on the Board? Is there any other method? I am thinking of a circumstance such as a BGA where I may have 1 or more connections which are control inputs to the BGA, and that as such they need to be tied either High (VCC) or Low (GND), but which I do not want to connect directly to the Plane in the middle of the Board, since I may want to cut them loose from that specific connection during testing or at some other time. Is there any other way to do this, short of routing the connection out to a jumper pattern outside of the BGA? Another common area where I might want to do this is with a component where I have to put the Decoupling Capacitor(s) on the back side of the board, and I do not want the specific via that goes thru the Board to the Power Pin to connect to the Plane in the middle of the Board (i.e.: I want to decouple the Pin and not the Plane.) JaMi -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Flex Circuits
Pioneer Circuit ( http:///www.pioneercircuits.com ) has never let me down. Their home page features the 30 some layer rigid flex I designed for the '97 mars pathfinder rover. John Hamid A. Wasti wrote: I am looking for a manufacturer that can do flex circuits, both prototype quantities and runs of a few hundred pieces. We have been extremely underwhelmed by the company we have been working with and would like to try someone new that comes with good recommendations. Any recommendations for a company here in the US that can manufacture flex circuits, that you have used and have been happy with, would be greatly appreciated. Regards, Hamid -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Importing Ansoft data to Protel 99SE
All, Ansoft Ensemble 5.1 is an RF design suite and analysis suite which produces output that looks like this; 1663 RectBlock 2 4 72.70169102 33.2705964 72.70169102 33.1098652 73.10885302 33.1098652 73.10885302 33.2705964 0 0 0 0 RectBlock 2 4 73.10885302 33.1301979 101.2425915 33.1301979 101.2425915 33.2705837 73.10885302 33.2705837 etc. Each block represents an RF element expressed as the 4 corner coordinates in mm. The engineer that I get this input from has an old ansoft to DXF converter which is no longer supported and the CAD tool I've been import the DXF into is destined for the scrap heap (Computervision CADDS4X). So my question is can I place this data (with a minimum of manipulation) directly into a ddb as shapefill blocks? I opened a new pwb and added one block, closed it and then edited the ddb in wordpad, but I couldn't locate my block. If someone can give me a keyword to search for, or other pointers I'd appreciate it. Thanks, John -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
Leo, Within your schematic on those components where you want additional control of the ground routing I place a net of GND_Uxx_1 where Uxx is the device and 1 is the pin number. This gives me unique single pin nets. On the pwb you can then route them as you wish and use the virtual short technique (as has been described here). Or as I typically do, I'll route them as I wish and then short them to ground manually which then gives me DRC errors which are easy to recognize as OK as is because on the way I've named the nets (i.e. it's OK to short GND_Uxx_1 to GND). I'll then delete those errors from the report (but that's just between you and me). John Leo Potjewijd wrote: Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
One place where you'd want every pin in a net is if you do a exhaustive connectivity check of your bare board before loading components. John JaMi Smith wrote: I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] wierd blacklist message
Have you insulted anyone today? Bagotronix Tech Support wrote: Did anyone else get the message below? It looks as if that message was sent by me, but it wasn't. Someone is spoofing something. I sent no such message. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, March 19, 2003 9:21 AM Subject: Re: [PEDA] Seperate Systems - was Roxio, Nero, Virii and crashes The message sender's address or IP address was found in one or more of the following Anti-Spam real time black lists. Crystal Groups Own BanList Please contact your system administrator or ISP for further information on how to be removed from these lists. If you feel this message is in error, please contact [EMAIL PROTECTED] If Hotmail blocks your email too, or you don't hear from someone withing 24-48 hours, call your contact at Crystal Group. You can find the phone number for Crystal Group at www.crystalpc.com. -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Polygon Filled Planes
Bob, There's no problem with having polygon fills overlapping. The sequence would be to establish the inner fill first and then the larger fill will flow around the first. As for editing, temporally move the larger fill off the pwb to edit the smaller fills. Be sure to not rebuild the larger fill (it'll disappear) or place it onto a place holder via which has the same net associated to it. I'm unsure what your error messages are about, but you might consider breaking up the large poly fill into smaller overlapping ones?? John Robert M. Wolfe wrote: Hello, I believe there was a thread on this subject which also had split neg. planes within its thread. I never really ended up with an answer. So dealing with polygons and not split planes, what is the proper way to handle plane within plane. I do remember something about not overlapping, but thought that the discussion was slpit planes??? My real question is if I have one or more smaller ploygon planes within a large plane that covers almost the whole board, do I need to delete the large plane first then edit the small planes vertices, then redraw the large polygon plane??? I am getting some errors on system level, if you try to touch the big plane to let it rebiuld it spits out an exception error, however if I do delete big plane first, then fix small planes, then redo big plane, all seems well. I do however created a mechanical layer outline of the planes so it is easy to reproduce the large plane. Weird thing about this though is that on a much slower machine there is no problem at all. Any help with proper procedure on many polygon planes will be appriciated. Thanks Bob Wolfe -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.6400 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Default Pointer
Mike, Most, if not all windows programs remember (in the system registry) the last directory used by that program. But you can set your My Documents folder to a specific location such as a mapped drive. Keep in mind that if working collaboratively that all windows programs do not create lock files (i.e. this is a poor mans PDM system). You could have a situation where two or more folks are overwriting each others work. Does anyone know how the design team feature (with it's members, permissions and sessions) works with a drive shared in this way? Or if the *.ldb file created when a design is opened would lock out all others? John [EMAIL PROTECTED] wrote: Great question for the open web, though it seems somewhat ambiguous to me. Try www.deja.com (now www.google.com) -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED]] Hi All, Does anyone out there know how I can set all my windows programs, Client 99 included to point to another drive by default. Would like to know how this is done both in Win 98 and XP. Thanks in advance John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.6400 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] question about layer synchronization between PCB and footprintlibrary
Anand, You should not need to define any layers in the footprint file. John Anand Kulkarni wrote: Hi everybody, I have struggled with this problem for sometime now; I hope you can help me. I defined a PCB in Protel with 6 layers. The layers were named : top,midlayer1,midlayer2,midlayer29,midlayer30,bottom by default. Now I also created a footprint for a xilinx FPGA part with 6 layers in it and named them the same as above. Now when I do an update of the PCB from the schematics only the layers top,midlayer1,midlayer2 and bottom are copied form the footprint to the PCB ; the layers midlayer29 and midlayer30 do not get copied ; I don't know what is happening ; I'd greatly appreciate any suggestions thanks and regards Anand Kulkarni Watch a championship game with Elway or McGwire. Enter Now at http://champions.lycos.com -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.6400 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Database maxed !
Have you emptied the trash bin? And as Brad mentioned it would be best to experiment on a copy. David VanHorn wrote: In an effort to fix this problem, I have deleted all but two of the mechanical layers, and I still have the error. I don't understand this. I've been regularly saving all, and the incremental amount I added since the last save all is microscopic compared to the reduction of file size by deleting all those mechanical layers. Any suggestions would be appreciated. I'm getting a bit nervous. In access, there's an option to compact and repair the database. That might help. It grows a fair bit on each manipulation. -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.6400 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Twisted-pair tracks
I also looked at this for long LVDS on printed flex cabling and the effect was marginal. This was not a full twist (utilizing vias) but rather superimposed snaking traces on a thin base material. Instead we opted for controlled impedance traces grouped to minimize cross talk or isolated with guard traces. The only place I've used this with appreciable benefit is in minimizing magnetic signatures in sensitive instruments, and there the primary benefit was to reduce the number of areas to calculate and sum. John Jon Elson wrote: Cam Andruik wrote: Has anyone ever tried to fake creating a twisted-pair on a PCB? I tried doing so on a recent board and our testing indicates that it did nothing. I think it is a waste of time to even attempt it but some people here think it is helpful. I did this on one board that had analog differential signals right next to 10 A, 80 V pulses with 40-100 nS Tr. It probably works, as there was no measurable crosstalk on the analog signals. I didn't however, make the board both ways and compare. I wouldn't even bother with two comparable low-level signals. Jon -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.6400 Cell: 818.653.7818 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB file translation
Lloyd, Router Solutions' CADCAM product claims to be able to do what you need. http://www.camcad.com/Features/supportedsys.html John [EMAIL PROTECTED] wrote: Hello all, I just received a pcb file from a subsiduary in Spain. They want us to manufacture the product for them. Only one little problem, their files are made with VISULA from ZUKEN-REDAC. Anyone know anything about this S/W and whether there is a possibility of translating it to Protel? Or the alternative is to have it converted directly into Unidoc, which we can't do either. Any thoughts? GE Energy Services __ Lloyd Good Development Digitization -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.6400 Cell: 818.653.7818 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mismatching gerber
Kiernan, You may have produced the components pads with a fill area rather then a pad definition. A fill area would be painted by available round apertures (gerber legacy) resulting in radii at the corners. A pad is defined in the gerber data as a particular shape and is flashed at it's origin. On the other hand you've say the pads are very tight, but don't say how tight. If your working with .005 square pad you may be seeing the bottom end of Protel resolution. Good luck, John [EMAIL PROTECTED] wrote: I've just managed to get a PCB created under Protel and I'm struggling to get the gerber output to match what's on the Protel screen. I've got several components (that I've created myself) which use very small rectangular pads and I've used these components at several angles all over the PCB. When I produce the gerber, all the corners of the pads are rounded off, though on the screen they are square. I've had to keep the pad sizes very tight and I don't want the resist etc to encroach under the pad. So my question is how can I get the corners to be square? I can't afford to increase the pad sizes to accomodate for the rounding. The PCB itself is a horribly dense radial PCB - probably not the best thing to start learning a package with, but this was part of the reason for moving to Protel in the first place. Any help would be much appreciated. Kiernan Fitzpatrick -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.6400 Cell: 818.653.7818 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Component partition
Tony, You could keep the schematic symbols separate and add alternate packages that would have convenient origins to allow correct placement to mimic a single package on the pwb. The schematic should make it clear that D1 is related to SW1. If the single package is used you can blank the diode reference designator. Problem? pick and place, BOM, extraneous lines on assembly drawing John Tony Karavidas wrote: Here's one to ponder: I have a schematic that uses an array of SPST switches and LEDs. On the PCB, I want to potentially keeps these as integrated parts, or possibly as separate LEDs and switches. How can I draw one schematic and still have the flexibility to use either physical configuration? If I keep the LED and switch arrays separate in the sch, then annotation will make two parts (D1 and SW1) for each switch with a built-in LED. If I make a special sch symbol that contains an LED and a switch, the schematic is ugly as hell, and THEN I can't use a separate switch and separate LED. What would you do??? Tony -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.4860 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Urgent help needed
All, Do you find these components (in the negative quadrant) in the gerber or pick and place outputs? jmc Ian Wilson wrote: At 10:09 AM 25/10/01 +1000, you wrote: Ian, it's actually pretty easy to loose parts. We recently have had a situation where a group of components have been unknowingly moved into the negative region of the database as part of a move selection process early in the placement stage. It turns out that the syncroniser matches the parts and the pins for the netstherefore no missing components.The netlist exists in the database but the physical ratsnest does not (I assume the physical ratsnest is only valid for the database extents). The DRC was 100% ok. It would appear that the DRC makes the assumption that if there is a valid net but no ratsnest then the net must be connected. (ie no broken net) (also no clearance errors either) I would be interested if anyone else has had this problem. We use SP6, W98 We only found it by noticing an associated text string on the left hand edge of the database area when zoomed right out. I too have seen the moving components (not for a long time though), for me at least, they have always existed in the netlist and the component report. I had not noticed what happens to the ratsnest when a component is off in ga-ga land but it still exists in the database, the netlist, the component report, the ASCII PCB version and even component browser. I have not checked if they exist in an exported spreadsheet. Thanks for the info on the ratsnets not showing for the gone-ape components (technical term), Ian Wilson -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.4860 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating Assembly Drawings
We use Computer Vision Cadds5, but that's not important. The time saver is that I only bring over (DXF) the component outline, drill and pwb outline information. That's plenty for the fab and assembly and if it's desired to have images of the layer artwork then I'll take pdfs off a gerber viewer and attach those to the pdf of the fab drawing. jmc Andy Lintz wrote: I use Autocad for assembly drawings, and I also was plagued by huge files and long redraw times until I learned a trick. Before exporting from Protel make a scratch copy of the board, and then perform global edits on Tracks, Text, Designators, and Arcs that change the line width to 0. This greatly reduces the file size and redraw time. You also may want to change the linewidth of all Multilayer holes to 0 width in Autocad to get them to look a bit better. Andy Lintz PP Systems Hi, I'm working to define our internal process to document boards for production. Specifically, I'm having a difficult time generating assembly drawings. After much discussion, we decided the best path is to use AutoCAD. It allows a great deal of flexibility to scale, rotate, and position the details for improving communication with the production staff. I use Gerber files converted to DXF via Camtastic. Here's the problem. AutoCAD is dirt slow when it comes to redrawing the screen. A simple two layer board takes seconds to redraw with only the silk-screen layer imported. The entire layout in Protel or Camtastic is very quick to redraw. It's killing the process. Questions: 1.) Is there any way to improve the redraw speed in AutoCAD short of moving from my P3, 600Mhz, 256M RAM to a faster computer? -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.4860 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [PROTEL EDA USERS]: Designator conventions?!
Here's a search result link from IEEE which has the full pdf versions (see items 40 and 41) If the link doesn't come across go to http://ieeexplore.ieee.org and search on reference designations I couldn't find the spec at ANSI's site either. Regards jmc http://ieeexplore.ieee.org/search97/s97is.vts?action=FilterSearchQueryZip=%28reference+designations%29Filter=adv%5Fsch%2EhtsResultTemplate=adv%5Fcrst%2EhtsCollection=jourCollection=confCollection=stdsCollection=pprintSortField=pyrSortOrder=descViewTemplate=lpdocview%2EhtsResultStart=31ResultCount=15 Andrew Lowy Sybrandy wrote: All, I just went to the ANSI site, and had no luck finding my way around. Does anyone have some quick advise on how to navigate through this site www.ansi.org to actually find the ANSI Y32.16-1975 standard? I typed Y32.16 on their search engine, and it came up with no result. Many Thanks, Andy -Original Message- From: TSListServer [mailto:[EMAIL PROTECTED]]On Behalf Of Abd ul-Rahman Lomax Sent: Tuesday, February 13, 2001 1:31 PM To: Multiple recipients of list proteledausers Subject: RE: [PROTEL EDA USERS]: Designator conventions?! At 12:24 PM 2/13/01 -0500, [EMAIL PROTECTED] wrote: Hi all, Even the term Designator conventions smacks of oxymoron. I am trying to create a company library database and SOP for design. I have many Engineers with various cultural backgrounds, some of which use some pretty weird ID's and symbols. Before I institute my 10 commandments, I would love to see some Designator conventions used by all of you. Please include as many as possible in your replies. The more ammunition the better. Note- I would prefer more North Amercian conventions as we are a N.A company. Thanks, ANSI Y32.16-1975. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 278-100 Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109 Tel: 818.354.5407 MailTo:[EMAIL PROTECTED] Fax: 818.393.4860 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
