Re: [time-nuts] DDS'ery narrow scoped.
On 21/06/11 12:48, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. Cheers, Magnus - this reply was only a month late... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) Luis Cupido. ct1dmk. p.s. No problem with the delay... ;-) On 7/21/2011 9:11 AM, Magnus Danielson wrote: On 21/06/11 12:48, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. Cheers, Magnus - this reply was only a month late... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Dear Luis, On 07/21/2011 05:30 PM, Luis Cupido wrote: Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) As I was tired I did not disclose enough details for implementation, but selected to be brief to bring in the approach to see if it was obvious or not. OK. A typical phase accumulator of n bits have N = 2^n possible states. Considering that fout = fclk * M/N where M is the normal phase-accumulator frequency control you can also realize that it takes N/gcd(M,N) state-changes to come back to the original state, so it can take a number of output cycles for all the beat frequencies to take integer cycles. If you instead want to select N freely you have to realize that while we every clock cycle perform P = P + M we assume that the operation is modulus N, so the actual formula is P = (P + M) mod N but since N was of the form 2^n it is trivial to truncate the bit of and just do N bit addition. So far I have only been very picky about details. If we now want to choose N freely to be N = 2^n we realize that we still needs to do the modulus calculation. Come to think of it, it always has two outcomes... P = P + M and P = P + M - N We can also know which to pick, since P cannot be larger than N and it cannot be below zero, so assuming we have a P already within those limits all it takes is a comparision of P if (P+M = N) P = P + M - N else P = P + M That is enough for simulation, but doesn't quite cut it for FPGA since you would get the propagation delay of both the comparision and the additions... on every cycle. We can improve on this by calculating two potential sums, and watch the carry from one of them to let a mux select between them. Also, the M-N difference is fairly static, so we pre-calculate it. precalc O = M - N cycle P1 = P + M C|P2 = P + O if (C == 0) P = P2 else P = P1 That should give you all the M/N relationships you would like to play with in a fairly sufficient FPGA structure. Much finer control over spurioses that way. Still fairly cheap in FPGA terms. I hope you have what you need to start fooling around. I could throw together some VHDL code for you if you really need it. With above re-definition of the problem the performance hit in fclk should not be as severe as the naive approach. Luis Cupido. ct1dmk. p.s. No problem with the delay... ;-) As it ended with you not saying you had a good solution, I thought it would be nice to send a message anyway. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. regards, Gerhard It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) On 7/21/2011 9:11 AM, Magnus Danielson wrote: You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Gerhard. This was an old thing I asked a month ago or so... Only the MSB of the accumulator is used to serve as reference to a pll. No sin or DAC involved ;-) Luis Cupido. ct1dmk On 7/21/2011 6:10 PM, dk...@arcor.de wrote: IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. regards, Gerhard It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) On 7/21/2011 9:11 AM, Magnus Danielson wrote: You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Your algorithm looks very much like the solution to the problem how to find divider values in a rf receiver having a very low IF and *not* full length divider chains for dividing all the needed reference frequencies. So how to find two values connected. Interesting. - Henry -- ehydra.dyndns.info Magnus Danielson schrieb: As I was tired I did not disclose enough details for implementation, but selected to be brief to bring in the approach to see if it was obvious or not. OK. A typical phase accumulator of n bits have N = 2^n possible states. ... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 07/21/2011 07:10 PM, dk...@arcor.de wrote: IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. True, this is an issue if you waveshape to sine/cosine or other suitable waveform. The scaling error is N/2^n so you would have to multiply by 2^n/N to get proper scale. A few shifted down adds to form a multiply approximation would help to reduce the phase-jump with associated spurious generation. However, in Luis application he only uses the MSB. The MSB would get a PWM factor skewed from 50%, in fact it becomes N/2^n. Again, PWM factor can be adjusted with the addition/multiplication trick mentioned above... if it is important for the application. Otherwise it is just wasted logic. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 07/21/2011 08:44 PM, Jim Lux wrote: On 7/21/11 8:30 AM, Luis Cupido wrote: Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) You can set up a sine table with any number of entries. Powers of two are popular, but, it could be anything.. Say you had multiple tables, one 20 long, one 21 long, one 22 long. You could use the 20 long one for generating 1/20th of a Hz, the 21 long one for generating 1/21th Hz, etc. That so obvious, we did not consider it a problem. The problem is when you need a large variation of N. Using a tuneable scaling to map into a suitable length (power of too) would be a better choice. Most FPGAs today have hardware multiplier blocks that can do the scaling needed, otherwise shift-add scaling (similar to CORDIC) would be a possibility as I mentioned in another post. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Thanks Jim, Joseph already pointed me to a pdf in a previous post. Now it is digestion time... should I say congestion !!! those MASH delta-sigmas are killing me... lc. ct1dmk. On 6/23/2011 4:30 AM, Jim Lux wrote: On 6/22/11 3:36 PM, Luis Cupido wrote: I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. if you email the author, often they will send you a pdf of the paper (or they'll have it on the web). The standard IEEE copyright assignment lets the author self publish on their own website or by sending reprints electronically. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
May Google be with you: A search on the title and an author yielded: http://petrified.ucsd.edu/~ispg-adm/pubs/mtt-s_2006.pdf From: Luis Cupido cup...@mail.ua.pt To: Discussion of precise time and frequency measurement time-nuts@febo.com Date: 06/22/2011 06:37 PM Subject:Re: [time-nuts] DDS'ery narrow scoped. Sent by:time-nuts-boun...@febo.com I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. inline: graycol.gifinline: ecblank.gif___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 6/22/11 3:36 PM, Luis Cupido wrote: I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. if you email the author, often they will send you a pdf of the paper (or they'll have it on the web). The standard IEEE copyright assignment lets the author self publish on their own website or by sending reprints electronically. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hello, El 21/06/2011 02:19, Luis Cupido escribió: Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) Best regards, Javier ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von Luis Cupido Gesendet: Dienstag, 21. Juni 2011 02:20 An: Discussion of precise time and frequency measurement Betreff: [time-nuts] DDS'ery narrow scoped. Folks, Many thanks to you all, for the info. This is indeed a great forum. My aplic. is a DDS signal that will serve as reference for a pll with a relatively narrow loop filter. As I said before. Most replies presume the analog world with DAC filters etc etc. But that I know ;-) I'm digging out the possibilities in the digital side not involving going back to analog and back to digital. this is how this started :-) Now that you all have been so kind in the great comments you gave, please let me just be very very very specific. Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) So I'm researching a way to have that digital output cleaner (spurs) without leaving the digital(FPGA) world sticking to the block diagram of one FPGA one digital output. Specially worried about close in spurs (the far away ones won't bother me much). That is really scenario I'm trying to picture if there is any hope to generate a cleaner digital output out of an FPGA (dds with whatever processing required to be done after and producing a square wave). Thanks for your patience. Luis Cupido. ct1dmk P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hi Ulrich, Loop bandwidth could be in the KHz region or even less. I could choose more or less freely from Hz to many KHz but there are obvious tradeoffs and it is hard to decide. The phase noise of the VCO when I go too narrow versus the ammount of spurs when I go too wide. Application is the first LO for an experiment in SDR radio at VHF-SHF region,(not HF). Luis Cupido. ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. On 6/21/2011 7:43 AM, Javier Herrero wrote: But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I've played with the core from altera for a while, but since I was only interested in 1 bit I'm now playing with my own code. Trivial variations on the plain old clocked accumulator architecture. lc On 6/21/2011 7:37 AM, Javier Herrero wrote: What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
That is maybe interesting to you: http://www.holmea.demon.co.uk/Projects.htm#Frac - Henry -- ehydra.dyndns.info Luis Cupido schrieb: P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
