from:"Jay"

Re: [RE-wrenches] Optics

2024-05-19 Thread Jay via RE-wrenches

I agree with you WilliamWhile there could be all sorts of valid reasons for the downtime. What’s not acceptable is the lack of communication and notification that it was going to happen or had happened.  If they do have new owners they are not starting well. JayOn May 18, 2024, at 9:42 PM, William Miller via RE-wrenches  wrote:Friends: I am sure you are all acutely aware, but this is not a trivial matter.  We depend on Optics for alerts and trouble shooting.  We rely on Optics for the history it records to analyze trends and evaluate production and consumption. I doubt the data lost will back-fill.  I sell Outback based in great part on the Optics interface.  For this system to be down for days at a time is not a good sign at all. I will be lighting up the phone lines on Monday to find out what happened and to emphasize this cannot become a pattern. William Miller Solar17395 Oak Road, Atascadero, CA 93422805-438-5600www.millersolar.comCA Lic. 773985  From: RE-wrenches [mailto:re-wrenches-boun...@lists.re-wrenches.org] On Behalf Of Lou Russo via RE-wrenchesSent: Saturday, May 18, 2024 11:50 AMTo: RE-wrenchesCc: Lou RussoSubject: Re: [RE-wrenches] Optics All my sites are currently down. Not related but I tried to call tech support yesterday during business hours and got message saying thank you for calling Outback Sales leave a message. I do hope they are just in transition but I got a bad feeling about this. I hope I am wrong. Has anyone heard for sure who bought them? I know they were bought from talking to tech support but that is all I know and the Internet has 0 info on a recent sale.  On Sat, May 18, 2024, 6:48 AM Dan Fink via RE-wrenches  wrote:Mine all went down yesterday at noon MDT. I wonder if this has to do with the sale of Outback?Dan FinkOwner, Buckville Energy Consulting LLCIREC Certified Instructor for PV and Small Wind InstallationNABCEP Certified PV System InspectorNABCEP PV Associatedanbo...@gmail.com970-672-4342   On Sat, May 18, 2024 at 10:17 AM William Miller via RE-wrenches  wrote:Friends: 100% of our Optics sites are down since 11 AM yesterday. Is it just us?William MillerMiller Solar.com805-438-5600www.millersolar.com ___List sponsored by Redwood AlliancePay optional member dues here: http://re-wrenches.orgList Address: RE-wrenches@lists.re-wrenches.orgChange listserver email address & settings:http://lists.re-wrenches.org/options.cgi/re-wrenches-re-wrenches.orgThere are two list archives for searching. When one doesn't work, try the other:https://www.mail-archive.com/re-wrenches@lists.re-wrenches.org/http://lists.re-wrenches.org/pipermail/re-wrenches-re-wrenches.orgList rules & etiquette:http://www.re-wrenches.org/etiquette.htmCheck out or update participant bios:http://www.members.re-wrenches.org
___List sponsored by Redwood AlliancePay optional member dues here: http://re-wrenches.orgList Address: RE-wrenches@lists.re-wrenches.orgChange listserver email address & settings:http://lists.re-wrenches.org/options.cgi/re-wrenches-re-wrenches.orgThere are two list archives for searching. When one doesn't work, try the other:https://www.mail-archive.com/re-wrenches@lists.re-wrenches.org/http://lists.re-wrenches.org/pipermail/re-wrenches-re-wrenches.orgList rules & etiquette:http://www.re-wrenches.org/etiquette.htmCheck out or update participant bios:http://www.members.re-wrenches.org___
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Re: [cayugabirds-l] Brant flyover?

2024-05-18 Thread Jay McGowan

Highly likely, many thousand were migrating up Cayuga Lake early this
morning, from Myers and Long Point.

And hopefully most everyone interested in rare birds has joined the NY
Discord server by now, but if not, I found a winter plumage PACIFIC LOON
off Long Point State Park this morning as well!

On Sat, May 18, 2024, 12:28 PM Peter Saracino 
wrote:

> This morning outside the Refuge Visitor Center Mark Miller and I
> witnessed  a huge flyover of waterfowl. At first we were perplexed. They
> were backlit but obviously waterfowl- MANY of them! But they seemed to big
> for ducks and too small for geese...and we heard no honking. Mark got a few
> shots with his camera and the bills were on the short side. Our best guess
> is brant...and, if correct, I've never seen so many of them!
>
> Pete Saracino/ NY State Master Naturalist Volunteer
>
>
> --
> *Cayugabirds-L List Info:*
> Welcome and Basics
> 
> Rules and Information
> 
> Subscribe, Configuration and Leave
> 
> *Archives:*
> The Mail Archive
> 
> Surfbirds 
> ABA 
> *Please submit your observations to eBird
> !*
> --
>

--

(copy & paste any URL below, then modify any text "_DOT_" to a period ".")

Cayugabirds-L List Info:
NortheastBirding_DOT_com/CayugabirdsWELCOME_DOT_htm
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ARCHIVES:
1) mail-archive_DOT_com/cayugabirds-l@cornell_DOT_edu/maillist_DOT_html
2) surfbirds_DOT_com/birdingmail/Group/Cayugabirds
3) aba_DOT_org/birding-news/

Please submit your observations to eBird:
ebird_DOT_org/content/ebird/

--

[webkit-changes] [WebKit/WebKit] fe3cc4: Cleaning tests expectation for stale tests

2024-05-17 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: fe3cc47711ad28abeaf3e2725fed8eb3383f7fbf
  
https://github.com/WebKit/WebKit/commit/fe3cc47711ad28abeaf3e2725fed8eb3383f7fbf
  Author: Jay Stfleur 
  Date:   2024-05-17 (Fri, 17 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk2/TestExpectations
M LayoutTests/platform/mac/TestExpectations

  Log Message:
  ---
  Cleaning tests expectation for stale tests
https://bugs.webkit.org/show_bug.cgi?id=274280
rdar://128227241

Unreviewed test gardening.

Editing test expectation.

* LayoutTests/platform/mac-wk2/TestExpectations:
* LayoutTests/platform/mac/TestExpectations:

Canonical link: https://commits.webkit.org/278936@main



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[webkit-changes] [WebKit/WebKit] ef07ff: Cleaning tests expectation for stale tests

2024-05-17 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: ef07ff576cff9ae93edd19d0f87d77fa336a
  
https://github.com/WebKit/WebKit/commit/ef07ff576cff9ae93edd19d0f87d77fa336a
  Author: Jay Stfleur 
  Date:   2024-05-17 (Fri, 17 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk1/TestExpectations

  Log Message:
  ---
  Cleaning tests expectation for stale tests
https://bugs.webkit.org/show_bug.cgi?id=274280
rdar://128227241

Unreviewed test gardening.

Re-adding test expectation to tests that are still failing/crashing.

* LayoutTests/platform/mac-wk1/TestExpectations:

Canonical link: https://commits.webkit.org/278925@main



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Re: [Histonet] Agarose embedded tissue arrays embedded in paraffin block

2024-05-17 Thread Jay Lundgren via Histonet

Where did the agarose come from?

On Fri, May 17, 2024 at 12:09 PM Otto, Christopher M via Histonet <
histonet@lists.utsouthwestern.edu> wrote:

>
>
> Hello everyone!
>
>  I'm having trouble sectioning tissue array blocks where the array is in
> agarose embedded into a paraffin block.  I've chilled the blocks and I'm
> sectioning on a rotary microtome, at 5 microns, with a high profile
> Accuedge blade. The paraffin surrounding the agarose sections normally, but
> the agarose portion of the block causes the blade to "skip" across it
> slightly and even chip out as if my blade isn't snug in the blade holder
> (it is).  If I do get a tiny portion of agarose on my section to float out
> on the waterbath it flies away (like adding ETOH to a waterbath with
> sections already on it.)   Everyone I have asked about this says the
> agarose should section normally with the paraffin like any other FFPE
> blocks. Any ideas on why this agarose is behaving this way for me?  Thank
> you in advance!
>
>
>
> ___
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[webkit-changes] [WebKit/WebKit] f606fe: Cleaning tests expectation for stale tests

2024-05-16 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: f606fe226b6f65e34820bdb8b17cc2fab81a14ec
  
https://github.com/WebKit/WebKit/commit/f606fe226b6f65e34820bdb8b17cc2fab81a14ec
  Author: Jay Stfleur 
  Date:   2024-05-16 (Thu, 16 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk1/TestExpectations

  Log Message:
  ---
  Cleaning tests expectation for stale tests
https://bugs.webkit.org/show_bug.cgi?id=274280
rdar://128227241

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk1/TestExpectations:

Canonical link: https://commits.webkit.org/278894@main



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Re: Q: is RFC3531 still applicable?

2024-05-15 Thread Jay Acuna

A /64 is not "enough" period.  Each IPv6 /64 should be thought of as
the same as an IPv4 /32.
The RFC is still relevant.  You are able to be allocated IPs
justifying 8-bits per customer
(/56) and customers should expect that /56 be the minimum delegated by
their providers.

The prefix delegation for IPv6 is based on number of separate /64
subnets they might have a reason
to use (which can be for many reasons including security and division
of traffic and use cases),

Not number of individual hosts they may have, since subnet divisions
more granular than
/64 are not possible.

On Wed, May 15, 2024 at 8:17 AM Mel Beckman  wrote:
> I never could understand the motivation behind RFC3531. Just assign /64s. A 
> single /64 subnet has 18,446,744,073,709,551,616  host addresses.  It is 
> enough. Period.
>  -mel
>
--
-J

[webkit-changes] [WebKit/WebKit] 1b89fe: imported/w3c/web-platform-tests/xhr/setrequesthead...

2024-05-15 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 1b89fed2685918bddf4100882852d46780bbe427
  
https://github.com/WebKit/WebKit/commit/1b89fed2685918bddf4100882852d46780bbe427
  Author: Jay Stfleur 
  Date:   2024-05-15 (Wed, 15 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk1/TestExpectations

  Log Message:
  ---
  imported/w3c/web-platform-tests/xhr/setrequestheader-case-insensitive.htm is 
a flaky failure
https://bugs.webkit.org/show_bug.cgi?id=271770
rdar://125494602

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk1/TestExpectations:

Canonical link: https://commits.webkit.org/278836@main



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Re: [Histonet] De-mummification procedure?

2024-05-15 Thread Jay Lundgren via Histonet

The Mummy's major weakness is fire, a common weakness among the undead.
Since mummies tend to be dry and coated with various oils and resins, the
revenant tends to burn very well.  Thus fire is the only way to destroy the
Mummy forever (aka de-mummification).

Sincerely,

Jay A. Lundgren, M.S., HTL (ASCP)

On Tue, May 14, 2024 at 4:21 PM Cheryl via Histonet <
histonet@lists.utsouthwestern.edu> wrote:

> Hi and help?  A tech on another forum is dealing with a catastrophe.
>
> Does anyone have the glycerin de-mummification procedure?  Haven’t used it
> in decades but with what those samples went through it may be their last
> chance as any sort of readable slides.
>
> TIA!!
>
> Cheryl
>
>
> Please excuse typos-sent from a phone.
>
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[webkit-changes] [WebKit/WebKit] e2c6bb: REGRESSION (278786@main): [ MacOS iOS ] 3X http/wp...

2024-05-15 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: e2c6bb58208739792d5f65f54e61147adf471f5c
  
https://github.com/WebKit/WebKit/commit/e2c6bb58208739792d5f65f54e61147adf471f5c
  Author: Jay Stfleur 
  Date:   2024-05-15 (Wed, 15 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  REGRESSION (278786@main): [ MacOS iOS ] 3X http/wpt/webauthn tests are 
consistent failures
https://bugs.webkit.org/show_bug.cgi?id=274219
rdar://128137880

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:
* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278820@main



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[Geoserver-users] Cloud Run instance of geoserver loses config settings

2024-05-15 Thread Jay Hill

I am using the Kartoza docker container in a Google Cloud Run instance. I
thought I had setup the jdbc-store and the jdbc-config correctly to use a
postgresql instance for storing settings but after a period of no use I log
back into the web admin ui and my workspace is gone and so is the store I
had added with all the layers. My first question is what is the best way to
be sure my geoserver is using the postgresql for storing settings? Next
question is when checking my logs each time the instance starts I see it
listing the databases correctly but then I see messages saying schemas
already exist so why isn't it reading them for config info?
Thanks

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Re: [RE-wrenches] Fortress Avalon

2024-05-15 Thread Jay via RE-wrenches

It’s an interesting design. I went to a seminar on it. Wiring the main power distribution center, is a bit tricky with how they designed or not wire room. Probably want to use cobra wire.  The battery voltage design is unusual in that more batteries increases the voltage, not bad just different. Web management looks good I presume you’re installing 5 of the 11kw units for 50kw or did you mean 50 kWh with 1 inverter?As to the high battery volts, I’m old enough to remember the push back against 48v. Or when GT solar was 48, and when SMA came out at 600v, it was way too high. Makes a lot of sense to go higher battery volts because with lithium it’s possible vs with lead it isn’t really. Hopefully there becomes a new common high voltage the OEM’s agree on.  New times. JayOn May 14, 2024, at 7:33 PM, Darryl Thayer via RE-wrenches  wrote:I am looking at going high voltage as opposed to 48 volts. This is my largest battery system, I have a large distance between battery and inverter, 40 feet, the cost of wire, 50 kW, at 50 volts is 1000 amps.  I am thinking this is too big for me.  On Tue, May 14, 2024, 7:29 PM Mac Lewis via RE-wrenches  wrote:Hello Wrenches,I am looking closely at offering the Fortress Avalon system.  I would like to hear from anyone that has installed, commissioned and seen them work in the field. Pros and cons, all of your thoughts are appreciated.Thanks!

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[clang] [flang] [libc] [libcxx] [llvm] [mlir] Fix typo "indicies" (PR #92232)

2024-05-15 Thread Jay Foad via cfe-commits


https://github.com/jayfoad closed 
https://github.com/llvm/llvm-project/pull/92232
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[clang] [flang] [libc] [libcxx] [llvm] [mlir] Fix typo "indicies" (PR #92232)

2024-05-15 Thread Jay Foad via cfe-commits


https://github.com/jayfoad created 
https://github.com/llvm/llvm-project/pull/92232

None

>From a02c63497b0d60f55e1846f5a050820082fb5c86 Mon Sep 17 00:00:00 2001
From: Jay Foad 
Date: Wed, 15 May 2024 10:04:57 +0100
Subject: [PATCH] Fix typo "indicies"

---
 clang/include/clang/AST/VTTBuilder.h  |  6 +-
 clang/lib/AST/VTTBuilder.cpp  |  2 +-
 clang/lib/CodeGen/CGVTT.cpp   | 17 ++---
 clang/lib/CodeGen/CGVTables.h |  6 +-
 .../command/commands/DexExpectStepOrder.py|  2 +-
 flang/docs/HighLevelFIR.md|  2 +-
 flang/test/Lower/HLFIR/forall.f90 |  2 +-
 libc/src/stdio/printf_core/parser.h   |  2 +-
 .../views/mdspan/CustomTestLayouts.h  |  2 +-
 llvm/docs/GlobalISel/GenericOpcode.rst|  4 +-
 llvm/include/llvm/Target/Target.td|  4 +-
 llvm/lib/Analysis/DependenceAnalysis.cpp  | 10 +--
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 12 ++--
 llvm/lib/Bitcode/Writer/ValueEnumerator.cpp   |  2 +-
 llvm/lib/Bitcode/Writer/ValueEnumerator.h |  2 +-
 .../LiveDebugValues/VarLocBasedImpl.cpp   |  2 +-
 llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp   |  2 +-
 llvm/lib/CodeGen/PrologEpilogInserter.cpp |  2 +-
 llvm/lib/Support/ELFAttributeParser.cpp   | 10 +--
 .../Target/AArch64/AArch64ISelLowering.cpp|  2 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp |  2 +-
 .../DirectX/DXILWriter/DXILBitcodeWriter.cpp  | 10 +--
 .../DXILWriter/DXILValueEnumerator.cpp|  2 +-
 .../DirectX/DXILWriter/DXILValueEnumerator.h  |  2 +-
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp   |  2 +-
 .../Transforms/InstCombine/InstCombinePHI.cpp |  4 +-
 .../Scalar/SeparateConstOffsetFromGEP.cpp |  2 +-
 .../Utils/SampleProfileInference.cpp  |  2 +-
 .../Transforms/Vectorize/SLPVectorizer.cpp| 64 +--
 llvm/test/CodeGen/X86/avx-vperm2x128.ll   |  2 +-
 .../test/DebugInfo/PDB/Inputs/every-type.yaml |  4 +-
 ...h-directive-personalityindex-diagnostics.s |  6 +-
 .../InstCombine/phi-extractvalue.ll   |  8 +--
 .../InstCombine/phi-of-insertvalues.ll|  6 +-
 .../VectorCombine/X86/scalarize-vector-gep.ll | 12 ++--
 .../Linalg/Transforms/Vectorization.cpp   |  6 +-
 36 files changed, 114 insertions(+), 113 deletions(-)

diff --git a/clang/include/clang/AST/VTTBuilder.h 
b/clang/include/clang/AST/VTTBuilder.h
index 4acbc1f9e96b2..3c19e61a8701c 100644
--- a/clang/include/clang/AST/VTTBuilder.h
+++ b/clang/include/clang/AST/VTTBuilder.h
@@ -92,7 +92,7 @@ class VTTBuilder {
   using AddressPointsMapTy = llvm::DenseMap;
 
   /// The sub-VTT indices for the bases of the most derived class.
-  llvm::DenseMap SubVTTIndicies;
+  llvm::DenseMap SubVTTIndices;
 
   /// The secondary virtual pointer indices of all subobjects of
   /// the most derived class.
@@ -148,8 +148,8 @@ class VTTBuilder {
   }
 
   /// Returns a reference to the sub-VTT indices.
-  const llvm::DenseMap () const {
-return SubVTTIndicies;
+  const llvm::DenseMap () const {
+return SubVTTIndices;
   }
 
   /// Returns a reference to the secondary virtual pointer indices.
diff --git a/clang/lib/AST/VTTBuilder.cpp b/clang/lib/AST/VTTBuilder.cpp
index d58e875177852..464a2014c430a 100644
--- a/clang/lib/AST/VTTBuilder.cpp
+++ b/clang/lib/AST/VTTBuilder.cpp
@@ -189,7 +189,7 @@ void VTTBuilder::LayoutVTT(BaseSubobject Base, bool 
BaseIsVirtual) {
 
   if (!IsPrimaryVTT) {
 // Remember the sub-VTT index.
-SubVTTIndicies[Base] = VTTComponents.size();
+SubVTTIndices[Base] = VTTComponents.size();
   }
 
   uint64_t VTableIndex = VTTVTables.size();
diff --git a/clang/lib/CodeGen/CGVTT.cpp b/clang/lib/CodeGen/CGVTT.cpp
index d2376b14dd582..4cebb750c89e8 100644
--- a/clang/lib/CodeGen/CGVTT.cpp
+++ b/clang/lib/CodeGen/CGVTT.cpp
@@ -138,23 +138,24 @@ uint64_t CodeGenVTables::getSubVTTIndex(const 
CXXRecordDecl *RD,
 BaseSubobject Base) {
   BaseSubobjectPairTy ClassSubobjectPair(RD, Base);
 
-  SubVTTIndiciesMapTy::iterator I = SubVTTIndicies.find(ClassSubobjectPair);
-  if (I != SubVTTIndicies.end())
+  SubVTTIndicesMapTy::iterator I = SubVTTIndices.find(ClassSubobjectPair);
+  if (I != SubVTTIndices.end())
 return I->second;
 
   VTTBuilder Builder(CGM.getContext(), RD, /*GenerateDefinition=*/false);
 
-  for (llvm::DenseMap::const_iterator I =
-   Builder.getSubVTTIndicies().begin(),
-   E = Builder.getSubVTTIndicies().end(); I != E; ++I) {
+  for (llvm::DenseMap::const_iterator
+   I = Builder.getSubVTTIndices().begin(),
+   E = Builder.getSubVTTIndices().end();
+   I != E; ++I) {
 // Insert all indices.
 BaseSubobjectPairTy ClassSubobjectPair(RD, I->first);
 
-SubVTTIndicies.insert(std::make_pair(ClassSubobjectPair, I->second));
+SubVTTIndices.insert(std::make_pair(ClassSubobjectPair, I->second));
   }
 
-  I = SubVTTIndicies.find(ClassSubobjectPair);
-  asser

[webkit-changes] [WebKit/WebKit] aed617: REGRESSION (278484@main): [ iOS ] editing/selectio...

2024-05-14 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: aed6175892fd3dcdbbac080b56b9dbd9733c8076
  
https://github.com/WebKit/WebKit/commit/aed6175892fd3dcdbbac080b56b9dbd9733c8076
  Author: Jay Stfleur 
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (278484@main): [ iOS ] 
editing/selection/ios/place-selection-in-overflow-area.html is a consistent 
timeout
https://bugs.webkit.org/show_bug.cgi?id=274180
rdar://128086114

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278777@main



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[webkit-changes] [WebKit/WebKit] dc3896: REGRESSION (276847@main): [ iOS Debug ] 3X fast/vi...

2024-05-14 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: dc38968fb27909092d42f1f69b070b9c042b7e30
  
https://github.com/WebKit/WebKit/commit/dc38968fb27909092d42f1f69b070b9c042b7e30
  Author: Jay Stfleur 
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (276847@main): [ iOS Debug ] 3X fast/viewport/ios/viewport-fit 
tests are consistent failures
https://bugs.webkit.org/show_bug.cgi?id=274175
rdar://128078422

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278773@main



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Re: Please forgive a blatant plug: I reviewed v10 for the Reg

2024-05-13 Thread Jay Patel


A Journey Into BSD and Standards: BSD and POSIX 
https://indico.bsdcan.org/event/1/contributions/26/

Yahoo Mail: Search, organise, conquer 
 
  On Fri, 10 May 2024 at 12:28 am, Liam Proven wrote:   On 
Thu, 2 May 2024 at 14:51, Hauke Fath (SPG)  wrote:
>
> And there's the rub, right there.
>
> You want to tell other people ("developers") what they should spend
> their time on. And if you were ten times right, it wouldn't work that way

Re: [Histonet] Inquiry on Tissue Softening for Microtomy

2024-05-12 Thread Jay Lundgren via Histonet

Pleasant is not a mission parameter.
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[cctalk] Re: ANSI-M (Mumps) and the VA

2024-05-12 Thread Jay Jaeger via cctalk

They can apply at epic systems in Verona, Wisconsin.  They are underlying 
infrastructure is based on mice and mumps.

Sent from my iPad

> On May 12, 2024, at 08:59, Bill Gunshannon via cctalk  
> wrote:
> 
> 
> With the VA dropping Vista what happens to that army of Mumps
> programmers they had?  Can't see much call for them in the IT
> world today.  Seems like a worse fate than COBOL Programmers.
> 
> bill

Re: [Histonet] Inquiry on Tissue Softening for Microtomy

2024-05-11 Thread Jay Lundgren via Histonet

I wouldn't say softening, I would say hydrating.  Ammonia water accelerates
hydration of FFPE blocks.  Nobody knows how it works, it's a mystery.  Or
at least I've never heard a scientific explanation.  Only pseudo-scientific
mumbo jumbo like "facilitates the removal of paraffin" which is false.  Go
soak a solid block of paraffin in pure NH4OH for 24 hours, it won't do
anything.

I was told as a student at AFIP, "It opens the pores of the tissue so water
can get in."  In other words, pseudo-scientific mumbo jumbo.

 It works though.  Somebody needs to get a $150,000,000 NIH grant and do a
research project on how ammonia water hydrates tissue.  I worked with some
lovely Hmong people in California that called it "crying water".

Using it can cause a big interpersonal problem with certain people in the
lab though.  Interestingly, hypersensitivity to smells is one of the
symptoms of autism.  Hypersensitivity to smells is also highly correlated
with bipolar disorder and heightened emotional reactivity.  Sooo...

Jay A. Lundgren, M.S., HTL (ASCP)

On Fri, May 10, 2024 at 11:14 PM John Kiernan via Histonet <
histonet@lists.utsouthwestern.edu> wrote:

>If you apply the ammonia to the cut surface of the paraffin block, I
> suspect that it softens the tissue in the same way as applying water: by
> entering interstices of the tissue that are not occupied by paraffin
> molecules.
>I never tried ammonia for this purpose but in the 1960s to early '70s I
> occasionally used a proprietary product called Mollifex, which I see is
> still sold. In 1972 or '73 an elderly technician told me that water was
> just as good, and I soon found out that he was right. Indeed, water had the
> advantage of working in 15-30 minutes rather than taking several hours.
> John Kiernan
> Emeritus, UWO, London, Canada
> https://publish.uwo.ca/~jkiernan/
> = = =
> 
> From: IGNACIO GONZÁLEZ MASSONI via Histonet <
> histonet@lists.utsouthwestern.edu>
> Sent: May 10, 2024 8:53 PM
> To: histonet@lists.utsouthwestern.edu 
> Subject: [Histonet] Inquiry on Tissue Softening for Microtomy
>
> Dear friends at Histonet,
>
> I hope this message finds you well. I am reaching out to seek your
> expertise on a matter that has piqued my interest in the field of histology.
>
> I am currently delving into the process of preparing FFPE (formalin-fixed,
> paraffin-embedded) tissues for microtomy. Specifically, I am curious about
> the role of ammonia in softening these tissues before sectioning. From my
> understanding, ammonia serves as an alkaline agent that helps neutralize
> formalin's effects and facilitates the removal of paraffin, thus aiding in
> the softening of the tissue.
>
> However, I would greatly appreciate if you could provide a more detailed
> explanation of the chemical interactions at play here. How exactly does
> ammonia interact with the tissue components to achieve the desired
> softening effect? Moreover, are there any best practices or safety
> precautions that one should be aware of when using ammonia in this context?
>
> Your insights on this topic would be invaluable to me and would greatly
> enhance my understanding of the intricacies involved in histological
> preparations.
>
> Thank you for your time and assistance.
>
> Warm regards from Santiago of Chile
>
> Ignacio, Medical Technologist
> ___
> Histonet mailing list
> Histonet@lists.utsouthwestern.edu
> http://lists.utsouthwestern.edu/mailman/listinfo/histonet
> ___
> Histonet mailing list
> Histonet@lists.utsouthwestern.edu
> http://lists.utsouthwestern.edu/mailman/listinfo/histonet
>
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[webkit-changes] [WebKit/WebKit] 7a2108: REGRESSION (274876@main): [ iOS Debug ] accessibil...

2024-05-10 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 7a210888c6c3af9fe64f74cb962bed519f8d7ae9
  
https://github.com/WebKit/WebKit/commit/7a210888c6c3af9fe64f74cb962bed519f8d7ae9
  Author: Jay Stfleur 
  Date:   2024-05-10 (Fri, 10 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (274876@main): [ iOS Debug ] 
accessibility/text-marker/text-marker-range-stale-node-crash.html is a 
consistent crash
https://bugs.webkit.org/show_bug.cgi?id=274020
rdar://127901543

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278633@main



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Re: NOAA Space Weather Prediction Center issued a Severe (G4) Geomagnetic Storm Watch

2024-05-10 Thread Jay R. Ashworth

How odd.

Both clocks are stratum 1?  Were the associated servers chiming off other 
servers
as well?

Cheers,
-- jra

- Original Message -
> From: "Mel Beckman" 
> To: "John Curran" , "NANOG" 
> Sent: Friday, May 10, 2024 4:29:13 PM
> Subject: Re: NOAA Space Weather Prediction Center issued a Severe (G4) 
> Geomagnetic Storm Watch

> We just had two TM1000 TimeMachine brand GPS NTP servers lose clock sync at 
> the
> same time, in two different cities (LA and Santa Barbara). The  outage lasted
> about five minutes, during which the NTP servers were responding, but with 
> time
> that was 1900 seconds out of sync. The devices showed satellite lock on 8 
> birds
> (not all the same ones). I've never seen this behavior before with years of 
> NTP
> clock experience.
> 
> It could be that these inexpensive NTP servers aren't very selective about 
> bogus
> inputs, as I would have expected them to lose synch in the event of a GPS
> signal failure. Instead they produced garbage. Our PRTG NTP monitor logged the
> problem this way:
> 
>  
> Sensor SNTP (SNTP) ***
> Device  10.2.10.90-TimeMachine NTP server (10.2.10.90)
> New Status at 5/10/2024 12:49:52 PM (Pacific Standard Time):
> Down
> Last Message:
> The target server did not return a valid time. To resolve this issue, use a
> packet analyzing tool and do a trace of the NTP packets to check if all fields
> are correctly populated. (code: PE085)
> 
> 
> From: NANOG  on behalf of John Curran
> 
> Sent: Friday, May 10, 2024 10:54 AM
> To: NANOG 
> Subject: NOAA Space Weather Prediction Center issued a Severe (G4) Geomagnetic
> Storm Watch
> 
> 
> <https://www.swpc.noaa.gov/news/swpc-issues-its-first-g4-watch-2005>
> SWPC Issues Its First G4 Watch Since 2005 | NOAA / NWS Space Weather 
> Prediction
> Center<https://www.swpc.noaa.gov/news/swpc-issues-its-first-g4-watch-2005>
> swpc.noaa.gov<https://www.swpc.noaa.gov/news/swpc-issues-its-first-g4-watch-2005>
> [favicon.ico]<https://www.swpc.noaa.gov/news/swpc-issues-its-first-g4-watch-2005>
> 
> "Multiple CMEs erupted associated with flare activity from Region 3664 on 
> 07-09
> May. These CMEs are expected to merge with potential arrival expected by early
> May 11 on the UTC day.”
> 
> (Low but distinct possibility of effects to radio and transmission systems)
> 
> FYI,
> /John
> 
> John Curran
> President and CEO
> American Registry for Internet Numbers

-- 
Jay R. Ashworth  Baylink   j...@baylink.com
Designer The Things I Think   RFC 2100
Ashworth & Associates   http://www.bcp38.info  2000 Land Rover DII
St Petersburg FL USA  BCP38: Ask For It By Name!   +1 727 647 1274

[llvm-branch-commits] [llvm] release/18.x: [AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622) (PR #91034)

2024-05-10 Thread Jay Foad via llvm-branch-commits


jayfoad wrote:

> Fixed encoding of AMDGPU instructions

I don't think the release notes should say that. It makes it sound like all 
encodings were wrong.

https://github.com/llvm/llvm-project/pull/91034
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[webkit-changes] [WebKit/WebKit] 12f6c2: REGRESSION (278473@main): [ iOS ] http/tests/site-...

2024-05-10 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 12f6c2c302248585c51793227b2a7b829464e81d
  
https://github.com/WebKit/WebKit/commit/12f6c2c302248585c51793227b2a7b829464e81d
  Author: Jay Stfleur 
  Date:   2024-05-09 (Thu, 09 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (278473@main): [ iOS ] 
http/tests/site-isolation/window-open-with-name-cross-site.html is a consistent 
timeout
https://bugs.webkit.org/show_bug.cgi?id=273984
rdar://127848665

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278605@main



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Re: [RBW] Upright / Relaxed / Swept-Back - Style of Riding

2024-05-09 Thread Jay

More great points, thanks!

Some responses:
- I would convert my Salsa Fargo to drop bar.  It has Apex 1x drivetrain, 
and there is an inexpensive MTB shifter that works well, plus this bike is 
designed with drops and flat/swept in mind
- I'm liking the look of the Albatross bar, not too extreme (walk before 
you can run!)
- I agree Bill that diet is important, and while mine is generally quite 
good, on a bad eating evening/day, the next day or later day ride does 
suffer (that includes if I had a beer, which doesn't work for me close to a 
ride, let alone on one...though it did last year on a 3-day tour, so who 
knows!)
- I also agree re: mental health, however, sometimes a ride greatly helps 
my mental health, so it's often worth the trade off (if I'm a bit sore, but 
that's not often case after a stressful time in my life)
- I like a lot of things about drop bars, but I feel like trying something 
different, and with the Fargo being like a drop bar mountain bike, I 
thought it would be a good candidate for convert

I went for a ride at lunch today.  Just 75 minutes.  I focused on keeping 
my pelvis upright/straight, and having my upper back/etc tip over a bit, 
vs. tilting from the pelvis (bike fitter I spoke to recently called this 
being like asparagus coming out of the microwave, trunk is solid, top folds 
over a bit, make sense?).  I was on the Roadini and the hoods are above the 
bars, and the shallow drop to the drops is comfortable and I felt good as I 
moved hand positions, not tilting too much forward.  Was a bind windy on 
the way back and did feel that space between my shoulder blades tightening 
a bit, but no worse than a 2/10 on the pain scale.

On Thursday, May 9, 2024 at 4:30:15 PM UTC-4 campyo...@me.com wrote:

> Quick thought regarding drop bars in response to LuckTurnip:
>
> Almost all of my bikes have drop bars. I have one bike with Soma’s 
> “Oxford” bars (a milder version of theAlbatross?) and a Brompton with a 
> straight handlebar to which I added forward-facing grip extensions.
>
> On my bikes with drop bars, I ride probably 99% of the time on the tops, 
> usually with my hands wrapped around the brake hoods. I find that 
> comfortable and it gives me easy access to the brake levers. 
>
> I spend the other 1% of my time in the drops because I’m not concerned 
> about aerodynamics. There are plenty of things slowing me down, and 
> assuming an aero posture isn’t going to do anything about most of those.
>
> This is of course personal preference, but I like the way drop bars look. 
> I have several classic bikes (Alex Singer, Cinelli, Masi) that were set up 
> with drop bars and which, I think, would look kinda dumb with upright bars. 
> Kind of like a Rambouillet with a polo seat and sissy bar (although some 
> might really like that look).
>
> Ride what you want and pick the bike/seat/handlebars that make you feel 
> comfortable. But don’t assume that drop bars are going to force you into am 
> uncomfortable, crouched posture. 
>
> --Eric Norris
> campyo...@me.com
> Insta: @CampyOnlyGuy
> YouTube: YouTube.com/CampyOnlyGuy 
>
> On May 9, 2024, at 11:00 AM, lucky...@gmail.com wrote:
>
> Fellow older person here. I have avoided owning a “fast bike” for years 
> due to drops killin’ me, but I recently acquired this sporty XO-1 and the 
> Albatross bar is perfect for it! I might not actually be fast but I *feel* 
> fast now (compared to my racked and fat-tired Atlantis) so that’s really 
> what matters. Albatross is the GOAT. 
>
> 
>
> On May 9, 2024, at 09:50, Wesley  wrote:
>
> Hi Jay,
> I'll second what's been said here and by Rivendell: the Albatross is the 
> swept-back bar that is least radical / closest to a drop bar.
>
> I first put an Albatross bar on a bike of mine in 2007 and have kept them 
> on at least one bike ever since. Unlike the other swept-back bars that Riv 
> sells, they have a great hand position that is slightly forward of the stem 
> clamp (demonstrated here): 
> 
>
>
> It's comfy for long hours on the bike. Like you, I find flat bars 
> uncomfortable (they pain my wrists). With Albatross bars, my wrist position 
> feels neutral and natural, a lot like on the lever tops on drop bars. The 
> Albatross bar is on my everyday bike, with the drop bar road bike being 
> used only when I want a lighter bike.
> -Wes 
> On Wednesday, May 8, 2024 at 6:28:41 PM UTC-7 Jay wrote:
>
>> I was always aware of bikes with a very relaxed geometry / setup, and it 
>> wasn't until I started seeing Rivendell bikes and watching youtube videos 
>> of people riding them that I really thought about it - is it more 
>> comfortable than drop bars, even if I have a more neutral (not aggressive) 
>> position on the bike (i.e., bars close to level with saddle)?  Would thi

[webkit-changes] [WebKit/WebKit] 4a07d8: REGRESSION (278522@main): [ MacOS iOS ] http/wpt/w...

2024-05-09 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 4a07d8d33e0ad3b9ca1d46212d56b69540f2ad27
  
https://github.com/WebKit/WebKit/commit/4a07d8d33e0ad3b9ca1d46212d56b69540f2ad27
  Author: Jay Stfleur 
  Date:   2024-05-09 (Thu, 09 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  REGRESSION (278522@main): [ MacOS iOS ] http/wpt/webauthn/idl.https.html is a 
consistent failure
https://bugs.webkit.org/show_bug.cgi?id=273963
rdar://127827007

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/ios/TestExpectations:
* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278581@main



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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits



@@ -493,8 +493,8 @@ Value *AMDGPUAtomicOptimizerImpl::buildScan(IRBuilder<> ,
 if (!ST->isWave32()) {
   // Combine lane 31 into lanes 32..63.
   V = B.CreateBitCast(V, IntNTy);
-  Value *const Lane31 = B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {},
-  {V, B.getInt32(31)});
+  Value *const Lane31 = B.CreateIntrinsic(
+  Intrinsic::amdgcn_readlane, B.getInt32Ty(), {V, B.getInt32(31)});

jayfoad wrote:

Changes like this should disappear if we merge #91583 first.

https://github.com/llvm/llvm-project/pull/89217
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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits


https://github.com/jayfoad edited 
https://github.com/llvm/llvm-project/pull/89217
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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits



@@ -5386,6 +5386,153 @@ bool 
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper ,
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper ,
+ MachineInstr ,
+ Intrinsic::ID IID) const {
+
+  MachineIRBuilder  = Helper.MIRBuilder;
+  MachineRegisterInfo  = *B.getMRI();
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register Src0 = MI.getOperand(2).getReg();
+
+  Register Src1, Src2;
+  if (IID == Intrinsic::amdgcn_readlane || IID == Intrinsic::amdgcn_writelane) 
{
+Src1 = MI.getOperand(3).getReg();
+if (IID == Intrinsic::amdgcn_writelane) {
+  Src2 = MI.getOperand(4).getReg();
+}
+  }
+
+  LLT Ty = MRI.getType(DstReg);
+  unsigned Size = Ty.getSizeInBits();
+
+  if (Size == 32) {
+if (Ty.isScalar())
+  // Already legal
+  return true;
+
+Register Src0Valid = B.buildBitcast(S32, Src0).getReg(0);

jayfoad wrote:

I think you can just reuse Src0 instead of declaring a new Src0Valid. Same for 
Src2, and same for the SDAG code.

https://github.com/llvm/llvm-project/pull/89217
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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits



@@ -5386,6 +5386,130 @@ bool 
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper ,
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper ,
+ MachineInstr ,
+ Intrinsic::ID IID) const {
+
+  MachineIRBuilder  = Helper.MIRBuilder;
+  MachineRegisterInfo  = *B.getMRI();
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register Src0 = MI.getOperand(2).getReg();
+
+  auto createLaneOp = [&](Register , Register ,
+  Register ) -> Register {
+auto LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0);
+if (Src2.isValid())
+  return (LaneOpDst.addUse(Src1).addUse(Src2)).getReg(0);
+if (Src1.isValid())
+  return (LaneOpDst.addUse(Src1)).getReg(0);
+return LaneOpDst.getReg(0);
+  };
+
+  Register Src1, Src2, Src0Valid, Src2Valid;
+  if (IID == Intrinsic::amdgcn_readlane || IID == Intrinsic::amdgcn_writelane) 
{
+Src1 = MI.getOperand(3).getReg();
+if (IID == Intrinsic::amdgcn_writelane) {
+  Src2 = MI.getOperand(4).getReg();
+}
+  }
+
+  LLT Ty = MRI.getType(DstReg);
+  unsigned Size = Ty.getSizeInBits();
+
+  if (Size == 32) {
+if (Ty.isScalar())
+  // Already legal
+  return true;
+
+Register Src0Valid = B.buildBitcast(S32, Src0).getReg(0);
+if (Src2.isValid())
+  Src2Valid = B.buildBitcast(S32, Src2).getReg(0);
+Register LaneOp = createLaneOp(Src0Valid, Src1, Src2Valid);
+B.buildBitcast(DstReg, LaneOp);
+MI.eraseFromParent();
+return true;
+  }
+
+  if (Size < 32) {
+Register Src0Cast = MRI.getType(Src0).isScalar()
+? Src0
+: B.buildBitcast(LLT::scalar(Size), 
Src0).getReg(0);
+Src0Valid = B.buildAnyExt(S32, Src0Cast).getReg(0);
+
+if (Src2.isValid()) {
+  Register Src2Cast =
+  MRI.getType(Src2).isScalar()
+  ? Src2
+  : B.buildBitcast(LLT::scalar(Size), Src2).getReg(0);
+  Src2Valid = B.buildAnyExt(LLT::scalar(32), Src2Cast).getReg(0);
+}
+Register LaneOp = createLaneOp(Src0Valid, Src1, Src2Valid);
+if (Ty.isScalar())
+  B.buildTrunc(DstReg, LaneOp);
+else {
+  auto Trunc = B.buildTrunc(LLT::scalar(Size), LaneOp);
+  B.buildBitcast(DstReg, Trunc);
+}
+
+MI.eraseFromParent();
+return true;
+  }
+
+  if ((Size % 32) == 0) {
+SmallVector PartialRes;
+unsigned NumParts = Size / 32;
+auto Src0Parts = B.buildUnmerge(S32, Src0);
+
+switch (IID) {
+case Intrinsic::amdgcn_readlane: {
+  Register Src1 = MI.getOperand(3).getReg();
+  for (unsigned i = 0; i < NumParts; ++i)
+PartialRes.push_back(
+(B.buildIntrinsic(Intrinsic::amdgcn_readlane, {S32})
+ .addUse(Src0Parts.getReg(i))
+ .addUse(Src1))
+.getReg(0));

jayfoad wrote:

Yes, separate patch

https://github.com/llvm/llvm-project/pull/89217
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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits



@@ -5386,6 +5386,153 @@ bool 
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper ,
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper ,
+ MachineInstr ,
+ Intrinsic::ID IID) const {
+
+  MachineIRBuilder  = Helper.MIRBuilder;
+  MachineRegisterInfo  = *B.getMRI();
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register Src0 = MI.getOperand(2).getReg();
+
+  Register Src1, Src2;
+  if (IID == Intrinsic::amdgcn_readlane || IID == Intrinsic::amdgcn_writelane) 
{
+Src1 = MI.getOperand(3).getReg();
+if (IID == Intrinsic::amdgcn_writelane) {
+  Src2 = MI.getOperand(4).getReg();
+}
+  }
+
+  LLT Ty = MRI.getType(DstReg);
+  unsigned Size = Ty.getSizeInBits();
+
+  if (Size == 32) {
+if (Ty.isScalar())
+  // Already legal
+  return true;
+
+Register Src0Valid = B.buildBitcast(S32, Src0).getReg(0);
+MachineInstrBuilder LaneOpDst;
+switch (IID) {

jayfoad wrote:

Can you use a `createLaneOp` helper to build the intrinsic, like you do in the 
SDAG path?

https://github.com/llvm/llvm-project/pull/89217
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[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

2024-05-09 Thread Jay Foad via cfe-commits


https://github.com/jayfoad commented:

LGTM overall.

> add f32 pattern to select read/writelane operations

Why would you need this? Don't you legalize f32 to i32?

https://github.com/llvm/llvm-project/pull/89217
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[RBW] Upright / Relaxed / Swept-Back - Style of Riding

2024-05-08 Thread Jay

I was always aware of bikes with a very relaxed geometry / setup, and it 
wasn't until I started seeing Rivendell bikes and watching youtube videos 
of people riding them that I really thought about it - is it more 
comfortable than drop bars, even if I have a more neutral (not aggressive) 
position on the bike (i.e., bars close to level with saddle)?  Would this 
be a good option for just cruising around, but for 1-2 hours?  If I didn't 
get along well with flat bars on mountain bike, would swept back bars be 
better?

I'm going to ramble a bit here, my apologies in advance.  I haven't thought 
long enough about this to formulate my question succinctly.  Hopefully you 
get where I'm coming from.

*Quick background*
- been riding a little over 20 years (closing in on 50!)
- started with mountain biking (hardtail, singletrack); moved to road; 
tried mountain biking two more times (I love being in nature) but didn't 
like the thrill/danger, and hated the idea of driving to the trail head; 
have been mainly on the road for last 15 years, though with 10 years of 
'gravel' bikes/riding
- I've had ongoing issues with my cervical spine (nothing serious) and this 
leads to some problems when riding in any sort of aggressive position on 
the bike; I see a chiro regularly; stretch a lot; workout / strength 
training; have had numerous bike fits
- I have a Roadini, Salsa Fargo and a road bike (25mm tires, but custom 
made and really does fit like a glove, for road)
- I don't care about performance at all, I just love riding bikes, in 
particular when roads are not busy, or on trails, gravel roads, etc.

On a good day (75% of the time), I can ride any of these bikes and during 
the ride I feel pretty good (little to no pain), maybe a bit of pain after 
(could be neck/shoulders, but anywhere else really), and after stretching I 
feel great in a 1/2 to full day.  I ride 4-5x a week, workout 1-2 times 
spring-fall and more in the winter.  

But at least once a week, and maybe twice, I'll be riding, sometimes tired 
as it's after work, and within an hour I'm running low on energy and 
probably start to develop a bad posture on the bike, over-using my arms 
which causes problems in my neck and shoulders, leading to upper body 
aches/pains (while riding, and after).  Takes a lot of stretching and 
awareness to reset.  *This is what I'm trying to resolve (move from 75% to 
99%)*

My guess is that even with a bike like the Roadini or Salsa, with bars 
about level with the saddle, and even with a professional fitting on each, 
when I want to ride but I'm lacking energy, it goes poorly.  But is that 
because these bikes are "kind of" aggressive (when compared to say a spine 
angle closer to 70% and swept back bars)?  Or is it simply a combination of 
age, history of some 'issues', low on energy and thus bad posture kicks in, 
and would any bike be a joy to ride, or should I just go for a walk on 
those days!?

I would love to hear from those who ride both drop bars and also swept back 
(or similar) in a way more relaxed geometry, or those who transitioned to 
mainly this style, because it almost fully resolved your issues, if they're 
anyway similar to mine.  *On a day when you're not feeling it, but you have 
to commute or just love to ride, do you leave the drop bar bike in the 
garage and hop on your more relaxed bike, and thus avoid most of the issues 
you would have had on the other (slightly more aggressive) bike?*

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Re: [RE-wrenches] Bootstrapping and AC Coupled Sunny Island

2024-05-08 Thread jay via RE-wrenches

HI William,

Yes the FM-100 has no problem with keeping the volts pretty tight and i’ve not 
heard of any lithium related issues, and someone is bound to chime in if there 
are.

jay



> On May 8, 2024, at 9:39 AM, William Miller  wrote:
> 
> Jay:
> 
> I am considering ditching the Sunny Boys and installing 2 Outback FM100s.  It 
> seems to me this might solve a few problems:
> 
> 1. The cc should voltage clamp and prevent over voltage when the batteries go 
> higher Z. 
> 2. The CCs should start up at lower voltages as soon as the sun comes out.  
> 3. One of the FM 100s could be configured to drive an AGS relay. 
> 4. The operation would be voltage dependent, not SOC dependent. 
> 
> My concern is the shallow voltage/charge curve. Can I set this system fine 
> enough to work reliably?
> 
> Has anyone used Outback charge controllers with lithium batteries?  Any 
> advice?
> 
> 
> William Miller
> Miller Solar.com
> 805-438-5600
> www.millersolar.com <http://www.millersolar.com/>
> 
> 
> On Wed, May 8, 2024 at 8:30 AM jay  <mailto:jay.pe...@gmail.com>> wrote:
> Hi William,
> 
> Since the SOC isn’t being reliable maybe due to not charging correctly?
> 
> I would recommend going to volts for the relay driver.  Thats why I suggested 
> the tristar with RD-1.
> Because really volts at full is the most accurate.
> Not knowing how many PV inputs you could do a cascade.
> 
> 
> jay
> 
>> On May 8, 2024, at 9:00 AM, William Miller > <mailto:will...@millersolar.com>> wrote:
>> 
>> Jay:
>> 
>> Thank you for taking the time. 
>> 
>> We are doing just what you suggest as an interim solution. 
>> 
>> The shortcoming of this work-around is that the highest setting for this 
>> relay function is 90% SOC. This may not be high enough to recalibrate the 
>> BMS units. And again, relying on SOC to drive operational decisions becomes 
>> problematic when one can’t rely on the accuracy of the SOC value. 
>> 
>> 
>> William Miller
>> Miller Solar.com <http://solar.com/>
>> 805-438-5600
>> www.millersolar.com <http://www.millersolar.com/>
>> 
>> 
>> On Wed, May 8, 2024 at 7:16 AM jay > <mailto:jay.pe...@gmail.com>> wrote:
>> A possible fix.
>> 
>> You could run a DC relay on the SB PV input that would be voltage triggered 
>> to prevent the battery volts from getting higher than you want.
>> 
>> The SI has 2 aux relays I think?  Or could do a tristar with RD-1 relay that 
>> has 4 channels.
>> 
>> Just a thought
>> 
>> jay
>> 
>>> On May 7, 2024, at 11:11 PM, William Miller via RE-wrenches 
>>> >> <mailto:re-wrenches@lists.re-wrenches.org>> wrote:
>>> 
>>> Friends:
>>>  
>>> I am still wrestling with problems integrating a Sunny Island / Sunny Boy 
>>> AC coupled system to a set of 5 E-vault Max battery cabinets.  
>>>  
>>> As a refresher, with closed loop comms, the Frequency Shift Power Control 
>>> system is not working, or not working quickly enough, and when nearing full 
>>> charge, the voltage can spike up to 66 volts and the SI system shuts down.  
>>> Fortress has told me in a roundabout way that they agree this is a real 
>>> problem and they are working on a solution.
>>>  
>>> Another problem has reared its head:  If the E-Vaults do not get charged 
>>> fully every 5 to 7 days, the BMS units SOC value becomes radically out of 
>>> calibration.  The E-vault will report a higher SOC than is realistic.  The 
>>> SI system starts the generator based on SOC and if the SOC is reported as 
>>> high the generator don’t start.  Sooner rather than later the battery 
>>> voltage gets too low and the system shuts down.
>>>  
>>> I have been tweaking on the settings like days-since-full-charge to attempt 
>>> to get this cycle to stop.  No definitive answer yet.
>>>  
>>> Here is the reason I am writing:  Yesterday I could not get the Sunny 
>>> Islands to start.  The battery voltage was 46 which should have been enough 
>>> but for some reason they just would not start.  Because of this I could not 
>>> charge the batteries from generator or from AC coupled solar.  I called SMA 
>>> but they told me they could not advise because of the non-compatible 
>>> batteries.  I asked about the emergency charging procedure in the manual 
>>> but I was told this does not work with lithium batteries.  The process is 
>>> pretty scary anyway so I was not inclined to try.
>>&g

Re: [RE-wrenches] Bootstrapping and AC Coupled Sunny Island

2024-05-08 Thread jay via RE-wrenches

Hi William,

Since the SOC isn’t being reliable maybe due to not charging correctly?

I would recommend going to volts for the relay driver.  Thats why I suggested 
the tristar with RD-1.
Because really volts at full is the most accurate.
Not knowing how many PV inputs you could do a cascade.


jay

> On May 8, 2024, at 9:00 AM, William Miller  wrote:
> 
> Jay:
> 
> Thank you for taking the time. 
> 
> We are doing just what you suggest as an interim solution. 
> 
> The shortcoming of this work-around is that the highest setting for this 
> relay function is 90% SOC. This may not be high enough to recalibrate the BMS 
> units. And again, relying on SOC to drive operational decisions becomes 
> problematic when one can’t rely on the accuracy of the SOC value. 
> 
> 
> William Miller
> Miller Solar.com
> 805-438-5600
> www.millersolar.com <http://www.millersolar.com/>
> 
> 
> On Wed, May 8, 2024 at 7:16 AM jay  <mailto:jay.pe...@gmail.com>> wrote:
> A possible fix.
> 
> You could run a DC relay on the SB PV input that would be voltage triggered 
> to prevent the battery volts from getting higher than you want.
> 
> The SI has 2 aux relays I think?  Or could do a tristar with RD-1 relay that 
> has 4 channels.
> 
> Just a thought
> 
> jay
> 
>> On May 7, 2024, at 11:11 PM, William Miller via RE-wrenches 
>> > <mailto:re-wrenches@lists.re-wrenches.org>> wrote:
>> 
>> Friends:
>>  
>> I am still wrestling with problems integrating a Sunny Island / Sunny Boy AC 
>> coupled system to a set of 5 E-vault Max battery cabinets.  
>>  
>> As a refresher, with closed loop comms, the Frequency Shift Power Control 
>> system is not working, or not working quickly enough, and when nearing full 
>> charge, the voltage can spike up to 66 volts and the SI system shuts down.  
>> Fortress has told me in a roundabout way that they agree this is a real 
>> problem and they are working on a solution.
>>  
>> Another problem has reared its head:  If the E-Vaults do not get charged 
>> fully every 5 to 7 days, the BMS units SOC value becomes radically out of 
>> calibration.  The E-vault will report a higher SOC than is realistic.  The 
>> SI system starts the generator based on SOC and if the SOC is reported as 
>> high the generator don’t start.  Sooner rather than later the battery 
>> voltage gets too low and the system shuts down.
>>  
>> I have been tweaking on the settings like days-since-full-charge to attempt 
>> to get this cycle to stop.  No definitive answer yet.
>>  
>> Here is the reason I am writing:  Yesterday I could not get the Sunny 
>> Islands to start.  The battery voltage was 46 which should have been enough 
>> but for some reason they just would not start.  Because of this I could not 
>> charge the batteries from generator or from AC coupled solar.  I called SMA 
>> but they told me they could not advise because of the non-compatible 
>> batteries.  I asked about the emergency charging procedure in the manual but 
>> I was told this does not work with lithium batteries.  The process is pretty 
>> scary anyway so I was not inclined to try.
>>  
>> SMA told me I may need an external 48 volt charging system.  I have heard of 
>> this being required in certain scenarios by wrenches.  This would be a huge 
>> pain in the ass: ordering one, waiting for it, hooking it up, etc.
>>  
>> Here is what I did:  I initiated the Quick Start Configuration mode and told 
>> the SI system there was a new battery bank.  I told it the bank was a very 
>> small VRLA battery.   The SI system accepted the 46 volts, started up and 
>> allowed a generator charge.  After an hour or so we reprogrammed the system 
>> for lithium and problem resolved, at least for now.
>>  
>> Hopefully this trick may help one of you some day.  If it does, it was worth 
>> my time typing it out.
>>  
>> William
>>  
>> Miller Solar
>> 17395 Oak Road, Atascadero, CA 93422
>> 805-438-5600
>> www.millersolar.com <http://www.millersolar.com/>
>> CA Lic. 773985
>>  
>>  
>> ___
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>> 
>> Pay optional member dues here: http://re-wrenches.org 
>> <http://re-wrenches.org/>
>> 
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Re: [RE-wrenches] Bootstrapping and AC Coupled Sunny Island

2024-05-08 Thread jay via RE-wrenches

A possible fix.

You could run a DC relay on the SB PV input that would be voltage triggered to 
prevent the battery volts from getting higher than you want.

The SI has 2 aux relays I think?  Or could do a tristar with RD-1 relay that 
has 4 channels.

Just a thought

jay

> On May 7, 2024, at 11:11 PM, William Miller via RE-wrenches 
>  wrote:
> 
> Friends:
>  
> I am still wrestling with problems integrating a Sunny Island / Sunny Boy AC 
> coupled system to a set of 5 E-vault Max battery cabinets.  
>  
> As a refresher, with closed loop comms, the Frequency Shift Power Control 
> system is not working, or not working quickly enough, and when nearing full 
> charge, the voltage can spike up to 66 volts and the SI system shuts down.  
> Fortress has told me in a roundabout way that they agree this is a real 
> problem and they are working on a solution.
>  
> Another problem has reared its head:  If the E-Vaults do not get charged 
> fully every 5 to 7 days, the BMS units SOC value becomes radically out of 
> calibration.  The E-vault will report a higher SOC than is realistic.  The SI 
> system starts the generator based on SOC and if the SOC is reported as high 
> the generator don’t start.  Sooner rather than later the battery voltage gets 
> too low and the system shuts down.
>  
> I have been tweaking on the settings like days-since-full-charge to attempt 
> to get this cycle to stop.  No definitive answer yet.
>  
> Here is the reason I am writing:  Yesterday I could not get the Sunny Islands 
> to start.  The battery voltage was 46 which should have been enough but for 
> some reason they just would not start.  Because of this I could not charge 
> the batteries from generator or from AC coupled solar.  I called SMA but they 
> told me they could not advise because of the non-compatible batteries.  I 
> asked about the emergency charging procedure in the manual but I was told 
> this does not work with lithium batteries.  The process is pretty scary 
> anyway so I was not inclined to try.
>  
> SMA told me I may need an external 48 volt charging system.  I have heard of 
> this being required in certain scenarios by wrenches.  This would be a huge 
> pain in the ass: ordering one, waiting for it, hooking it up, etc.
>  
> Here is what I did:  I initiated the Quick Start Configuration mode and told 
> the SI system there was a new battery bank.  I told it the bank was a very 
> small VRLA battery.   The SI system accepted the 46 volts, started up and 
> allowed a generator charge.  After an hour or so we reprogrammed the system 
> for lithium and problem resolved, at least for now.
>  
> Hopefully this trick may help one of you some day.  If it does, it was worth 
> my time typing it out.
>  
> William
>  
> Miller Solar
> 17395 Oak Road, Atascadero, CA 93422
> 805-438-5600
> www.millersolar.com <http://www.millersolar.com/>
> CA Lic. 773985
>  
>  
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Re: [RE-wrenches] Bootstrapping and AC Coupled Sunny Island

2024-05-08 Thread Jay via RE-wrenches

Hi WilliamHave you talked to fortress about the SOC getting so out of calibration in such a short period of time?JayOn May 7, 2024, at 11:16 PM, William Miller via RE-wrenches  wrote:Friends: I am still wrestling with problems integrating a Sunny Island / Sunny Boy AC coupled system to a set of 5 E-vault Max battery cabinets.   As a refresher, with closed loop comms, the Frequency Shift Power Control system is not working, or not working quickly enough, and when nearing full charge, the voltage can spike up to 66 volts and the SI system shuts down.  Fortress has told me in a roundabout way that they agree this is a real problem and they are working on a solution. Another problem has reared its head:  If the E-Vaults do not get charged fully every 5 to 7 days, the BMS units SOC value becomes radically out of calibration.  The E-vault will report a higher SOC than is realistic.  The SI system starts the generator based on SOC and if the SOC is reported as high the generator don’t start.  Sooner rather than later the battery voltage gets too low and the system shuts down. I have been tweaking on the settings like days-since-full-charge to attempt to get this cycle to stop.  No definitive answer yet. Here is the reason I am writing:  Yesterday I could not get the Sunny Islands to start.  The battery voltage was 46 which should have been enough but for some reason they just would not start.  Because of this I could not charge the batteries from generator or from AC coupled solar.  I called SMA but they told me they could not advise because of the non-compatible batteries.  I asked about the emergency charging procedure in the manual but I was told this does not work with lithium batteries.  The process is pretty scary anyway so I was not inclined to try. SMA told me I may need an external 48 volt charging system.  I have heard of this being required in certain scenarios by wrenches.  This would be a huge pain in the ass: ordering one, waiting for it, hooking it up, etc. Here is what I did:  I initiated the Quick Start Configuration mode and told the SI system there was a new battery bank.  I told it the bank was a very small VRLA battery.   The SI system accepted the 46 volts, started up and allowed a generator charge.  After an hour or so we reprogrammed the system for lithium and problem resolved, at least for now. Hopefully this trick may help one of you some day.  If it does, it was worth my time typing it out. William Miller Solar17395 Oak Road, Atascadero, CA 93422805-438-5600www.millersolar.comCA Lic. 773985  
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[plasmashell] [Bug 486756] fontconfig to turn antialiasing off freezes KDE plasma

2024-05-07 Thread Daniel Jay Haskin

https://bugs.kde.org/show_bug.cgi?id=486756

--- Comment #1 from Daniel Jay Haskin  ---
Indeed, having a fontconfig file there _at all_ seems to cause stability
issues. I got a lot further with anti aliasing on but had to remove it
altogether to stop the stability issues entirely.

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[plasmashell] [Bug 486756] New: fontconfig to turn antialiasing off freezes KDE plasma

2024-05-07 Thread Daniel Jay Haskin

https://bugs.kde.org/show_bug.cgi?id=486756

Bug ID: 486756
   Summary: fontconfig to turn antialiasing off freezes KDE plasma
Classification: Plasma
   Product: plasmashell
   Version: 6.0.4
  Platform: Other
OS: Linux
Status: REPORTED
  Severity: normal
  Priority: NOR
 Component: Application Menu (Kicker)
  Assignee: plasma-b...@kde.org
  Reporter: djhaskin...@gmail.com
  Target Milestone: 1.0

SUMMARY

fontconfig set to antialiasing freezes KDE and associated applications.
STEPS TO REPRODUCE
1. Place this in `~/.config/fontconfig/conf.d/10-no-anti-aliasing.conf`: ```


false

```
2. Reboot computer
3. Log in

OBSERVED RESULT

Opened the application "Konsole". It came up but stopped responding. I opened
the -- start menu? I guess that's "kicker" -- and typed "q", thinking to open
qutebrowser. It froze. I couldn't even pull up a tty (ctrl-alt-f3). I had to
power cycle the machine manually. The mouse worked, but the OS stopped
responding.

I changed the `false` to `true` in the fontconfig via boot to tty and _then_
logged in, and everything worked again.

ADDITIONAL INFORMATION

Operating System: Fedora Linux 40
KDE Plasma Version: 6.0.4
KDE Frameworks Version: 6.1.0
Qt Version: 6.7.0
Kernel Version: 6.8.8-300.fc40.x86_64 (64-bit)
Graphics Platform: Wayland
Processors: 8 × Intel® Core™ i7-1065G7 CPU @ 1.30GHz
Memory: 7.4 GiB of RAM
Graphics Processor: Mesa Intel® Iris® Plus Graphics
Manufacturer: HP
Product Name: HP Spectre x360 Convertible 13-aw0xxx

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Re: bookworm: When using gdm3 to start non-GNOME wayland sessions, PATH may be set differently

2024-05-06 Thread Jay

On Wed, May 1, 2024 at 6:13 PM Alban Browaeys  wrote:
> So you were right that reverting commit ccecd9c9 would fix your issue,
> but not because gdm added a bug but because it stopped hiding an
> underlying "bug" (well wrong default PATH value in systemd for Debian).
> It could be that systemd maintainers thing this is gdm job to overwrite
> their value, though it looks more correct to me to bug them first as
> they are the one setting the wrong default for Debian (or so I believe,
> I have not checked extensively if the wrong PATH default value could be
> fine at the systemd level and be changed afterwards).
Thanks again! I finally found some time to further investigate this.
I have reassigned this bug report to the systemd package,
but it looks like base-files and libpam-modules are the packages
involved.

My Debian system was installed in 2022-10. To be sure this wasn't
just a misconfigured system in 2022, I checked again with a fresh
Debian 12.5 install and found that the same defaults are present.

> The Debian specific defaults are shown in /etc/profile
Reading that made me check Ubuntu's defaults:
/etc/environment
PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
/etc/profile
(no mention of PATH)

It looks like Ubuntu sets PATH in /etc/environment through libpam-modules
and /usr/lib/environment.d/99-environment.conf is symlinked to it.
Debian sets PATH in /etc/profile through base-files and its
/usr/lib/environment.d/99-environment.conf
is symlinked to an empty /etc/environment also created by libpam-modules.

Ubuntu's libpam-modules runs a postinst script:
# Add PATH to /etc/environment if it's not present there or in
# /etc/security/pam_env.conf
if [ "$1" = "configure" ] && dpkg --compare-versions "$2" lt
1.3.1-5ubuntu5; then
if ! grep -qs ^PATH "$DPKG_ROOT"/etc/security/pam_env.conf; then
if ! grep -qs ^PATH= "$DPKG_ROOT"/etc/environment; then
echo
'PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"'
>> "$DPKG_ROOT"/etc/environment
fi
fi
fi

Debian's libpam-modules postinst:
if dpkg --compare-versions "$2" lt 0.99.9.0-1 && ! [ -f
"$DPKG_ROOT"/etc/environment ]
then
 touch "$DPKG_ROOT"/etc/environment
fi

I think we can narrow this down to base-files and/or libpam-modules.
I'm not sure if doing the same thing as the Ubuntu package would be
the right thing
so I'm CC'ing the maintainers for both packages and the debian-desktop
mailing list
for advice instead of reassigning the bug report again.

Bug#1037084: bookworm: When using gdm3 to start non-GNOME wayland sessions, PATH may be set differently

2024-05-06 Thread Jay

On Wed, May 1, 2024 at 6:13 PM Alban Browaeys  wrote:
> So you were right that reverting commit ccecd9c9 would fix your issue,
> but not because gdm added a bug but because it stopped hiding an
> underlying "bug" (well wrong default PATH value in systemd for Debian).
> It could be that systemd maintainers thing this is gdm job to overwrite
> their value, though it looks more correct to me to bug them first as
> they are the one setting the wrong default for Debian (or so I believe,
> I have not checked extensively if the wrong PATH default value could be
> fine at the systemd level and be changed afterwards).
Thanks again! I finally found some time to further investigate this.
I have reassigned this bug report to the systemd package,
but it looks like base-files and libpam-modules are the packages
involved.

My Debian system was installed in 2022-10. To be sure this wasn't
just a misconfigured system in 2022, I checked again with a fresh
Debian 12.5 install and found that the same defaults are present.

> The Debian specific defaults are shown in /etc/profile
Reading that made me check Ubuntu's defaults:
/etc/environment
PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
/etc/profile
(no mention of PATH)

It looks like Ubuntu sets PATH in /etc/environment through libpam-modules
and /usr/lib/environment.d/99-environment.conf is symlinked to it.
Debian sets PATH in /etc/profile through base-files and its
/usr/lib/environment.d/99-environment.conf
is symlinked to an empty /etc/environment also created by libpam-modules.

Ubuntu's libpam-modules runs a postinst script:
# Add PATH to /etc/environment if it's not present there or in
# /etc/security/pam_env.conf
if [ "$1" = "configure" ] && dpkg --compare-versions "$2" lt
1.3.1-5ubuntu5; then
if ! grep -qs ^PATH "$DPKG_ROOT"/etc/security/pam_env.conf; then
if ! grep -qs ^PATH= "$DPKG_ROOT"/etc/environment; then
echo
'PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"'
>> "$DPKG_ROOT"/etc/environment
fi
fi
fi

Debian's libpam-modules postinst:
if dpkg --compare-versions "$2" lt 0.99.9.0-1 && ! [ -f
"$DPKG_ROOT"/etc/environment ]
then
 touch "$DPKG_ROOT"/etc/environment
fi

I think we can narrow this down to base-files and/or libpam-modules.
I'm not sure if doing the same thing as the Ubuntu package would be
the right thing
so I'm CC'ing the maintainers for both packages and the debian-desktop
mailing list
for advice instead of reassigning the bug report again.

Bug#1037084: bookworm: When using gdm3 to start non-GNOME wayland sessions, PATH may be set differently

2024-05-06 Thread Jay

On Wed, May 1, 2024 at 6:13 PM Alban Browaeys  wrote:
> So you were right that reverting commit ccecd9c9 would fix your issue,
> but not because gdm added a bug but because it stopped hiding an
> underlying "bug" (well wrong default PATH value in systemd for Debian).
> It could be that systemd maintainers thing this is gdm job to overwrite
> their value, though it looks more correct to me to bug them first as
> they are the one setting the wrong default for Debian (or so I believe,
> I have not checked extensively if the wrong PATH default value could be
> fine at the systemd level and be changed afterwards).
Thanks again! I finally found some time to further investigate this.
I have reassigned this bug report to the systemd package,
but it looks like base-files and libpam-modules are the packages
involved.

My Debian system was installed in 2022-10. To be sure this wasn't
just a misconfigured system in 2022, I checked again with a fresh
Debian 12.5 install and found that the same defaults are present.

> The Debian specific defaults are shown in /etc/profile
Reading that made me check Ubuntu's defaults:
/etc/environment
PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
/etc/profile
(no mention of PATH)

It looks like Ubuntu sets PATH in /etc/environment through libpam-modules
and /usr/lib/environment.d/99-environment.conf is symlinked to it.
Debian sets PATH in /etc/profile through base-files and its
/usr/lib/environment.d/99-environment.conf
is symlinked to an empty /etc/environment also created by libpam-modules.

Ubuntu's libpam-modules runs a postinst script:
# Add PATH to /etc/environment if it's not present there or in
# /etc/security/pam_env.conf
if [ "$1" = "configure" ] && dpkg --compare-versions "$2" lt
1.3.1-5ubuntu5; then
if ! grep -qs ^PATH "$DPKG_ROOT"/etc/security/pam_env.conf; then
if ! grep -qs ^PATH= "$DPKG_ROOT"/etc/environment; then
echo
'PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"'
>> "$DPKG_ROOT"/etc/environment
fi
fi
fi

Debian's libpam-modules postinst:
if dpkg --compare-versions "$2" lt 0.99.9.0-1 && ! [ -f
"$DPKG_ROOT"/etc/environment ]
then
 touch "$DPKG_ROOT"/etc/environment
fi

I think we can narrow this down to base-files and/or libpam-modules.
I'm not sure if doing the same thing as the Ubuntu package would be
the right thing
so I'm CC'ing the maintainers for both packages and the debian-desktop
mailing list
for advice instead of reassigning the bug report again.

Re: [edk2-devel] [Question] VM failed to start with secure boot and TPM 2.0

2024-05-06 Thread Zhoujian (jay) via groups.io

Add Maintainers and Reviewers:
Jiewen Yao mailto:jiewen@intel.com>>
Rebecca Cran mailto:rebe...@bsdio.com>>
Corvin Köhne mailto:corv...@freebsd.org>>

Could you give us some advice?

Thanks

From: Zhoujian (jay)
Sent: Monday, April 29, 2024 12:07 PM
To: 'devel@edk2.groups.io' 
Cc: zhengyaohui (A) ; Wangxin (Alexander) 

Subject: [Question] VM failed to start with secure boot and TPM 2.0

Hi all,

We encountered a problem that the virtual machine failed to start. Our
Configuration is as follows:
1. Use qemu 4.1.0 and edk2 202011 for x86 test, and qemu 7.1.0 and edk2 202011
for arm test
2. Enable secure boot and TPM 2.0.
3. Import the PK [1]\KEK [2]\db [3]\dbx [4]certificates.
4. VM started with 60 disks and 7 network cards

The log of serial port reported the errors:
```
Could not create MokListRT: Volume full
Could not create MokListXRT: Volume full
Could not create SbatlevelRT: Volume full
Could not create MokListTrustedRT: Volume full
Something has gone seriously wrong: import_mok_state() failed : Volume Full
```

TPM measures part of UEFI variables, include PK/KEK/db/dbx, BootOrder and so
on. It calls Tcg2HashLogExtendEvent (edk2 SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c)
to write to event log. Currently the event log length is 64 KB, if full,
Tcg2HashLogExtendEvent returned EFI_VOLUME_FULL which caused the VM
failed to start.

I found some description about variable area length and event log area length.
After using tpm2-tool to parse the event logs, we found that event log of a
variable contains variable data. Theoretically, the variable size can exceed
64KB, as long as it does not exceed 256KB. Maybe event log area length
should be greater than variable area length ?

In section 9.2 of TCG PC Client Platform Firmware Profile Specification [5]:
```
The Log Area Minimum Length for the TCG event log MUST be at least 64KB.
```

In source code [6] of edk2:
```
## This PCD defines minimum length(in bytes) of the system preboot TCG event 
log area(LAML).
# For PC Client Implementation spec up to and including 1.2 the minimum log 
size is 64KB.
# @Prompt Minimum length(in bytes) of the system preboot TCG event log 
area(LAML).
gEfiSecurityPkgTokenSpaceGuid.PcdTcgLogAreaMinLen|0x1|UINT32|0x00010017
```

In source code [7] of edk2:
```
!if $(FD_SIZE_IN_KB) == 4096 <- - - - - -  # it is true in our configuration
# Size: 0x4 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
# 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
# This can speed up the Variable Dispatch a bit.
0xB8, 0xFF, 0x03, 0x00,
!endif
```

Based on the above analysis, We tried two solutions:
1. We modify the TcgCommLogEvent function in edk2 to ignore the
EFI_VOLUME_FULL error, return EFI_SUCCESS but not write event log. This idea
refers to [8].
2. We increase the value of PcdTcgLogAreaMinLen because TCG only defines
minimum length. And tpm2-tools has supported event logs longer than 64KB [9].

Both solutions can make the virtual machine start successfully but not sure if
they introduce other problems. For the first solution, we are worried that
the missing part of the event log will affect the TPM's function. For the
second solution, we are not sure if this change will have any impact on other
components.

Could you give us some advices?

Thanks

References:
[1] https://go.microsoft.com/fwlink/?linkid=2255361
[2] https://go.microsoft.com/fwlink/p/?linkid=321185
[3] https://go.microsoft.com/fwlink/?LinkId=321192
[4] https://uefi.org/sites/default/files/resources/x64_DBXUpdate.bin
[5] 
https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/
[6] https://github.com/tianocore/edk2/blob/master/SecurityPkg/SecurityPkg.dec
[7] https://github.com/tianocore/edk2/blob/master/OvmfPkg/Bhyve/VarStore.fdf.inc
[8] https://github.com/rhboot/shim/pull/657
[9] https://github.com/tpm2-software/tpm2-tools/pull/2683


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[llvm-branch-commits] [llvm] release/18.x: [AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622) (PR #91034)

2024-05-06 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad approved this pull request.


https://github.com/llvm/llvm-project/pull/91034
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[cctalk] Re: Help request with fundraising campaign to save historic computers

2024-05-05 Thread Jay Jaeger via cctalk


On 5/3/2024 5:35 AM, Gianluca Bonetti via cctalk wrote:

Hello everyone


I am helping Museo del Computer with this fundraising effort in order to
save a large number of machines with significant historic value, including
some Sperry Univac systems.
Museo del Computer is a non-profit organization in northern Italy, run
solely by volunteer work and donors' money since governments are still not
interested in computer history.
Museo del Computer is one of the largest computer history museums
worldwide, with 4000 sqm between exhibition area and storage space, open to
the public upon booking.

This recovery expedition will go as far as 750km to load 100+ machines onto
3 lorries.
Gianluca Bonetti


Is there a list somewhere of the machines?

Also, if there are EXEC OS tapes there, make sure those are treated with 
care.  If they need help reading 7 track tapes and are willing to ship 
them to the US, I can recommend a contact who recently read a 7 track 
tape for me that dated back to the 1960s.


As far as vetting the legitimacy of the fund raising campaign, I did a 
little diggging.


First I saw that there is a website that folks may find useful.

http://www.museodelcomputer.org/

That website has a donations page, but the translation process makes it 
hard to find the link on that donation page, but I did see a link on the 
Italian version, and it does seem to point to the same place, so it 
seems legit.  (There is a link I found on that page near the end of this 
posting).


https://fundrazr.com/computermuseum?ref=ab_62Z1p5MB63862Z1p5MB638

Also, I followed a link from the above fundrazr that points back to 
their website donation page, which is reassuring:


http://www.museodelcomputer.org/index.php/nav=Informazioni.35/Language=ITA/MD=/SD=/Pagina=4

JRJ

[cctalk] Re: Help request with fundraising campaign to save historic computers

2024-05-05 Thread Jay Jaeger via cctalk


On 5/4/2024 11:46 AM, Sellam Abraham via cctalk wrote:

On Sat, May 4, 2024 at 9:28 AM Gianluca Bonetti via cctalk <
cctalk@classiccmp.org> wrote:


...
I am helping Museo del Computer with this fundraising effort in order to
save a large number of machines with significant historic value, including
some Sperry Univac systems.
...


I would want to know more of the story and also to see more photos before I
would consider donating.

Sellam


I'm on the same page with you, Sellam.  I would want to see a website, 
and a link to the donation page on that website before I would consider 
donating.


JRJ

Re: [RE-wrenches] 120 Vac and 12Vdc mixed distribution system

2024-05-04 Thread Jay via RE-wrenches

I wanted to follow up on this thread. According to the sol Ark website. The US 8 kw is rated at 120/240. Which I’ve always thought mean 3 wire. L1,L2,N. The US 5kw is 120v only. L1, N Do I have this correct?JayOn May 4, 2024, at 9:15 AM, Tom McCalmont via RE-wrenches  wrote:It does not do split-phase.  You either configure it for 120V or 240V, both single-phase (no neutral).On May 4, 2024, at 6:45 AM, Dana Orzel  wrote:& from what I was told this week split you only get 1/2 the power per leg? Please clarify if different _Dana OrzelGREAT SOLAR WORKS! C – 208.721.7003  E – d...@solarwork.comW - www. greatsolarworks.com www.solarwork.com“Responsible Technologies for Responsible People since 1988!” ___List sponsored by Redwood AlliancePay optional member dues here: http://re-wrenches.orgList Address: RE-wrenches@lists.re-wrenches.orgChange listserver email address & settings:http://lists.re-wrenches.org/options.cgi/re-wrenches-re-wrenches.orgThere are two list archives for searching. When one doesn't work, try the other:https://www.mail-archive.com/re-wrenches@lists.re-wrenches.org/http://lists.re-wrenches.org/pipermail/re-wrenches-re-wrenches.orgList rules & etiquette:http://www.re-wrenches.org/etiquette.htmCheck out or update participant bios:http://www.members.re-wrenches.org___
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Re: [EVDL] [External] Re: EVLN: Tesla cuts 3 major departments

2024-05-04 Thread Jay Summet via EV





On 5/4/24 15:41, EV List Lackey via EV wrote:


Anyway, we're those folks who stay behind the slow traffic because we don't
want or need to go faster.  If we're not in a hurry, which is most of the
time, we'd rather go slower and save electricity, range, and battery life.


Heh, I guess I'm not the only one who sits well behind a slow semi 
truck, letting everyone behind me blame them for my slow speed, and 
knowing that anybody who whips around me to pass won't pull right in 
front of me because they don't want to be behind the semi truck


Jay
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[webkit-changes] [WebKit/WebKit] 415ec2: [ iOS wk2 ] webgl/1.0.3/conformance/uniforms/out-o...

2024-05-03 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 415ec24722aedbfd49f21e9a5dd41347a7136bd4
  
https://github.com/WebKit/WebKit/commit/415ec24722aedbfd49f21e9a5dd41347a7136bd4
  Author: Jay Stfleur 
  Date:   2024-05-03 (Fri, 03 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  [ iOS wk2 ] 
webgl/1.0.3/conformance/uniforms/out-of-bounds-uniform-array-access.html is a 
flaky/consistent timeout
https://bugs.webkit.org/show_bug.cgi?id=269321
rdar://122912491

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278355@main



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[webkit-changes] [WebKit/WebKit] 8d47e9: [ Sonoma+ wk2 Release ] inspector/console/console-...

2024-05-03 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 8d47e90a96db05b0f771ea5453685b29ef55d496
  
https://github.com/WebKit/WebKit/commit/8d47e90a96db05b0f771ea5453685b29ef55d496
  Author: Jay Stfleur 
  Date:   2024-05-03 (Fri, 03 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  [ Sonoma+ wk2 Release ] inspector/console/console-screenshot.html is a flaky 
text failure
https://bugs.webkit.org/show_bug.cgi?id=268200
rdar://121695395

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278354@main



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[webkit-changes] [WebKit/WebKit] 3c4552: REGRESSION: [ Ventura+ Release x86_64 ] fast/canva...

2024-05-03 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 3c4552d23e72054a1b0f9839447a1813f9aa3a4a
  
https://github.com/WebKit/WebKit/commit/3c4552d23e72054a1b0f9839447a1813f9aa3a4a
  Author: Jay Stfleur 
  Date:   2024-05-03 (Fri, 03 May 2024)

  Changed paths:
M LayoutTests/platform/mac/TestExpectations

  Log Message:
  ---
  REGRESSION: [ Ventura+ Release x86_64 ] 
fast/canvas/image-buffer-backend-variants.html  is a flaky failure
https://bugs.webkit.org/show_bug.cgi?id=267612
rdar://121081110

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac/TestExpectations:

Canonical link: https://commits.webkit.org/278353@main



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Re: [RE-wrenches] 120 Vac and 12Vdc mixed distribution system

2024-05-03 Thread Jay via RE-wrenches

Maybe the new 5kw 120v unit is the 8kw at 120v?JayOn May 3, 2024, at 4:22 PM, Tom McCalmont via RE-wrenches wrote:David is correct. We have some experience with Sol-Ark’s inverter, and it’s a good product. However, be aware that you can configure it either as a 120V inverter with a max. output of about 5 kW or as a 240V inverter with a max. output of about 8 kW. However, it does NOT do split-phase, meaning if you configure it for 240V, it cannot run loads that require a neutral.Tom McCalmontPaired PowerOn May 3, 2024, at 4:12 PM, david quattro via RE-wrenches wrote:I think SolArk makes an 8K 120V-only versionDavidOn Fri, May 3, 2024 at 3:13 PM Jason Szumlanski via RE-wrenches wrote:For this application I was originally thinking about a 48V inverter with 120V output, but there are not many options in the size range I was considering. It hit me that I could potentially get a 120/240V split-phase inverter and run the DC converter from one leg and the 120V loads from the other leg. The Sol-Ark 8K would probably be the right size for this application. Despite there being no 240V loads, they "could" add them in the future if needed. I know about imbalance issues with the 12k, but have not heard this same feedback about the 8k, so please let me know if you know otherwise. I really doubt there will be enough imbalance here to cause issues. The biggest load on the DC side is a tiny 12V DC pump and the largest load on the AC side will be the new refrigerator, or maybe a big ceiling fan starting up. The inductive loads are almost negligible. Really the only reason I want an inverter this large is for the charger capacity. The owner wants a 9.6kWh LiPo battery minimum, so I want a sizable charger.BUT, the client would need to replace their 120V portable generator with a split-phase unit. That could be a sticking point taking me back to a 120V inverter.I was hoping for an all-in-one for this particular job, but the only one I can find that is 48Vdc and 120Vac is the EG4 6500EX-48. At the price point they offer it, I guess it can't hurt to try! I can even have a spare on the shelf for less in total than the cost of a Victron inverter charger and separate charge controller, and still have money to spare. I have been dabbling into the EG4 brand, mostly with clients that went ahead and bought EG4 batteries before they ever met me, and I haven't had any real issues other than battery to inverter closed loop comms. It's too early to say I'm impressed, but the prices are in the too-good-to-be-true category. I don't want to get off topic here with batteries and manufacturer reliability, but I wanted to mention the EG4 6500EX-48, which seems like perfect specs for this job.And... I know... someone is probably thinking that we're up to a 9.6kWh battery with a small 120V generator, and that's probably not a good match. I get that, but the client expects the PV to handle all of their needs with the generator only serving as an emergency backup. I have alerted them to the potential mismatch. I still want a sizeable charger in case they upgrade their generator for faster battery recharges.Jason SzumlanskiPrincipal Solar Designer | Florida Solar Design GroupNABCEP Certified Solar Professional (PVIP)Florida State Certified Solar Contractor CVC56956Florida Certified Electrical Contractor EC13013208On Wed, Apr 24, 2024 at 1:52 PM John Blittersdorf via RE-wrenches wrote:Jason, Just using the converter works fine. They are considered a battery charger or a regulated power supply. I am currently running that way now with the battery cables going nowhere. I was thinking of putting the battery back in the system just for triple redundancy when my inverter hits low battery cutoff voltage on a cold winter night and no fuel for the generator (or it won't start).My Iota DLS puts out a regulated 13.4 volts up to 30 amps. JohnOn Wed, Apr 24, 2024 at 8:25 AM Jason Szumlanski via RE-wrenches wrote:Ah ha! I didn't consider using a small 12V battery with a charger. I was thinking of just using a 120V -> 12V converter to handle the DC loads. Is the 12V battery really necessary, or can I just power the DC loads directly with a converter? If I just have lights and fans on the DC system, the load should be pretty minimal. I could use a separate 12V battery, but I would like to eliminate that cost and complexity if possible.And yeah, I am not considering this a money making opportunity. It's really just a challenge to ward off boredom from the daily grind.Jason SzumlanskiPrincipal Solar Designer | Florida Solar Design GroupNABCEP Certified Solar Professional (PVIP)Florida State Certified Solar Contractor CVC56956Florida Certified Electrical Contractor EC13013208On Wed, Apr 24, 2024 at 8:01 AM John Blittersdorf via RE-wrenches wrote:Jason, I have a customer with the same situation except he already has a

[RBW] Re: Blue Lug Build Catalog

2024-05-03 Thread Jay

Before I purchased a Riv I spent some time on their site, and those builds; 
really well done.  I watched their videos, including those in Japanese, and 
they're very enjoyable.

On Thursday, May 2, 2024 at 3:14:41 PM UTC-4 eric...@gmail.com wrote:

> If you're wondering "How do I tastefully build and specify a bike?" this 
> is the *perfect* place to start. They also do a great job with the 
> photographs, some of the best out there. 
>
> On Thursday, May 2, 2024 at 3:13:45 PM UTC-4 Eric Marth wrote:
>
>> Oh yeah, this is a gallery I have bookmarked. So many great builds and 
>> lots and lots of inspiration. They always nail it, great ideas abound! 
>>
>> On Wednesday, May 1, 2024 at 10:27:09 AM UTC-4 drewfi...@gmail.com wrote:
>>
>>> Many of you may already be aware of this, but Blue Lug has a nice 
>>> catalog of all it's Riv Builds for customers. In the even you want some 
>>> inspiration for your next build, or just want to see some different takes 
>>> on each frame, have a look:
>>>
>>> https://bluelug.com/bike-catalog/model/rivendell-bicycle-works/
>>>
>>> If you click the dropdown in the top right corner and scroll down to the 
>>> Riv section you can even filter for specific models. Been super helpful as 
>>> I accrue the things needed for my upcoming 56cm 2TT Sam I scored from Abe 
>>> on here.
>>>
>>> Hopefully helpful for folks looking to build out that next frame or 
>>> rebuild your old favorite!
>>>
>>> - Drew
>>>
>>>

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Re: [RBW] Re: Scam alert? I'm so confused. Blue Homer in LA? ND?

2024-05-03 Thread Jay

I feel for those of you who have been scammed.  Hopefully, karma plays out 
for them, and perhaps you'll have a 'win' in the near future that makes up 
for it.

I'm almost to the point of quoting any online used buy/sell activity.

I've bought/sold bike stuff, and a few other categories of items, on kijiji 
for 10-15 years.  Pre-covid, didn't do too bad.  Most items would go in 1-2 
weeks, a lot of views, responses were generally positive even if a sale 
didn't occur.  Most who did respond, got back to you even if they decided 
to pass on the item.  Likewise, I would message on things I was interested 
in, and most sellers were respectful and good to deal with.  During covid, 
selling was a piece of cake.  Now, sigh, about 90% of the interactions I've 
had are with pinheads.  People who in one minute seem so interested "I can 
be there today between 3-4pm", and when you say you're working, how about 
after dinner, you never here another word from them (this has happened with 
8 out of the last 10 interactions).  I've had items listed for months with 
no activity.  I may donate a bunch of things to a bike collective or 
not-for-profit and hopefully the old parts (mainly saddles and stems) will 
go to a good home.  I'm a really positive person, but it's hard to be 
positive with a lot the online activity these days (and these are not 
scammers, just, pinheads!).

Buy/Sell looks great on this site.  I'm in Canada though so that's a bit of 
a challenge (though I do use cross border pick up site, and it works fine, 
both directions), plus I'm at my budget for spending on bike things, for 
now, and I have most of what I want.

On Friday, May 3, 2024 at 11:07:48 AM UTC-4 krhe...@gmail.com wrote:

> @Roberta and Eric -
> Let me clarify how I was scammed. I posted here last July wanting to buy 
> Blue Lug's
> *REW10 WORKS* hex brass valve caps here in the states to save myself some 
> monies in overseas shipping costs. 
>
> Anita Batya saw my post and claimed that she had a pair. Anita told me 
> that she lived in Seattle, of which is relatively close to me (This was a 
> lie. She lived in Pennsylvania after doing some online homework after the 
> fact). If I wanted them, she requested me to make a payment through a third 
> party email address of which she claimed it was her bookkeeper. Anita told 
> me that she was waiting for an answer from Paypal for a refund. I sent 
> her money (I forgot what amount it was $50.00~?) several times. This kept 
> going in circles over and over again. By then, I felt that there was 
> something mighty strange and peculiar going on. I caught on that I was 
> being scammed. I did not respond back to her. This was my first time being 
> scammed over something that I really wanted. My apologies for there might 
> be some holes left out from my recollection of my interaction with Anita. 
>
> Later down the road, there was other members herein and over on the IBOB 
> group being scammed by Anita. Skip Montanaro, the administrator accepted 
> Anita 
> Batya's membership. When I told Skip that she was/is a scammer, he quickly 
> took action and denied her membership.
>
> https://groups.google.com/g/internet-bob/c/5FXmDXVSG6c/m/yGCjPQ3KBAAJ
> https://groups.google.com/g/rbw-owners-bunch/c/WRzS3bBRKcc
>
> Kim Hetzel. 
>
> On Friday, May 3, 2024 at 7:24:11 AM UTC-7 drewfi...@gmail.com wrote:
>
>> The "Jeff" in question reached out to me in response to a WTB post. I 
>> asked what his "Friend" was selling and he said a 60cm Homer, which I 
>> thought was strange considering my post specifically said 54/55/56cm. 
>>
>> A quick check to see that he'd never posted in the forum and I assumed it 
>> was nefarious. 
>>
>> On Friday, May 3, 2024 at 9:20:37 AM UTC-4 eric...@gmail.com wrote:
>>
>>> Kim: I don't see how the administrator of this forum has any bearing on 
>>> someone's Facebook post. The scam is potentially occurring via Facebook, 
>>> not our forum. You reposted the FB listing here with a link. 
>>>
>>> Regarding the Blue Lug purchase, how on earth were you "scammed" by Blue 
>>> Lug? They are one of the best bike shops in the universe and I'm sure they 
>>> would correct any mistake or problem with your purchase. I dislike like the 
>>> implication that Blue Lug would scam anyone. 
>>>
>>> Regarding scams and buying/selling: If anything about the listing or 
>>> your interactions with a seller makes you uncomfortable or sets off 
>>> *any* alarms just drop the exchange and walk away. It's easy! If it's 
>>> too good to be true, it probably is. Although sometimes you have to know 
>>> when to snag a deal like when someone posts a Nitto S83 seatpost for $30. 
>>> Sellers should be happy and eager to share photos or details about frames 
>>> or bikes for sale. 
>>>
>>> Here on the forum it's easy to check someone's history simply by 
>>> searching their email address and reviewing their past posts to see if they 
>>> participate in discussions, buy and sell goods and you can get a

[mou-net] Request for assistance – song recordings of migrating Mourning Warblers

2024-05-03 Thread Jay Pitocchelli

Request for assistance – song recordings of migrating Mourning Warblers

I am posting my annual opportunity to participate in a Citizens Science Project
that involves recording migrating Mourning Warbler songs. I am trying to
determine the nature of migratory pathways taken by different song populations
of Mourning Warbler males during their spring migration. I am continuing to
collect your recordings and plot them on a map of North America to determine if
and where birds with different song types (regiolects) separate from each other
during spring migration. The most current map of songs of migrants is at the
web site below.

https://www.google.com/maps/d/viewer?hl=en=1voXjBhvHZ0nwAv93_OBC_vCPuxQ=38.8925160098804%2C-85.09712735=5

All you need is a Smartphone and a singing Mourning Warbler. You can send the
recordings to my e-mail address (jpitocch AT anselm.edu). The web page link
below describes the project and how to make recordings on your Smartphone in
more detail.

https://mowasongmapper.weebly.com/

This year is the 10th and final year of data collection. I very much
appreciate your past and present contributions to this Citizens Science
Project.

Dr. Jay Pitocchelli
Professor Emeritus
Biology Department
Saint Anselm College
Manchester, NH 03102

General information and guidelines for posting:
https://moumn.org/listservice.html
Archives: http://lists.umn.edu/archives/mou-net.html

During the pandemic, the MOU encourages you to stay safe, practice social
distancing, and continue to bird responsibly.

[webkit-changes] [WebKit/WebKit] 113d94: REGRESSION (273737@main): [ iOS 17 ] imported/w3c/...

2024-05-02 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 113d9483bb8a07751c5d91d1b241ac72533c3b6b
  
https://github.com/WebKit/WebKit/commit/113d9483bb8a07751c5d91d1b241ac72533c3b6b
  Author: Jay Stfleur 
  Date:   2024-05-02 (Thu, 02 May 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (273737@main): [ iOS 17 ] 
imported/w3c/web-platform-tests/css/css-flexbox/negative-overflow-002.html  is 
a consistent text failure
https://bugs.webkit.org/show_bug.cgi?id=269116
rdar://122678250

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278289@main



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[webkit-changes] [WebKit/WebKit] 21cf72: [ Gardening ]: [ Monterey+ wk2 Release ] media/tra...

2024-05-02 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 21cf72f8ddcc0419ba46e354296bb184483c60ba
  
https://github.com/WebKit/WebKit/commit/21cf72f8ddcc0419ba46e354296bb184483c60ba
  Author: Jay Stfleur 
  Date:   2024-05-02 (Thu, 02 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  [ Gardening ]: [ Monterey+ wk2 Release ] 
media/track/media-element-enqueue-event-crash.html  is a flaky image crash
https://bugs.webkit.org/show_bug.cgi?id=268494
rdar://122040288

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278281@main



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[webkit-changes] [WebKit/WebKit] 7eb995: [ Sonoma wk2 release ] fast/forms/listbox-padding-...

2024-05-02 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 7eb99553daaade6b449b6e221907e3ea62dd8106
  
https://github.com/WebKit/WebKit/commit/7eb99553daaade6b449b6e221907e3ea62dd8106
  Author: Jay Stfleur 
  Date:   2024-05-02 (Thu, 02 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  [ Sonoma wk2 release ] fast/forms/listbox-padding-clip-selected.html is a 
flaky image failure
https://bugs.webkit.org/show_bug.cgi?id=267778
rdar://121275821

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278279@main



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[nysbirds-l] Request for assistance – song recordings of migrating Mourning Warblers

2024-05-02 Thread Jay Pitocchelli

Request for assistance – song recordings of migrating Mourning Warblers

I am posting my annual opportunity to participate in a Citizens Science 
Project that involves recording migrating Mourning Warbler songs.I am 
trying to determine the nature of migratory pathways taken by different 
song populations of Mourning Warbler males during their spring 
migration.I am continuing to collect your recordings and plot them on a 
map of North America to determine if and where birds with different song 
types (regiolects) separate from each other during spring migration.The 
most current map of songs of migrants is at the web site below.

https://www.google.com/maps/d/viewer?hl=en=1voXjBhvHZ0nwAv93_OBC_vCPuxQ=38.8925160098804%2C-85.09712735=5
 
<https://www.google.com/maps/d/viewer?hl=en=1voXjBhvHZ0nwAv93_OBC_vCPuxQ=38.8925160098804%2C-85.09712735=5>

All you need is a Smartphone and a singing Mourning Warbler.You can send 
the recordings to my e-mail address (jpitocch AT anselm.edu).The web 
page link below describes the project and how to make recordings on your 
Smartphone in more detail.

https://mowasongmapper.weebly.com/ <https://mowasongmapper.weebly.com/>

This year is the 10^th and final year of data collection.I very much 
appreciate your past and present contributions to this Citizens Science 
Project.

Dr. Jay Pitocchelli

Professor Emeritus

Biology Department

Saint Anselm College

Manchester, NH 03102

--

(copy & paste any URL below, then modify any text "_DOT_" to a period ".")

NYSbirds-L List Info:
NortheastBirding_DOT_com/NYSbirdsWELCOME_DOT_htm
NortheastBirding_DOT_com/NYSbirdsRULES_DOT_htm
NortheastBirding_DOT_com/NYSbirdsSubscribeConfigurationLeave_DOT_htm

ARCHIVES:
1) mail-archive_DOT_com/nysbirds-l@cornell_DOT_edu/maillist_DOT_html
2) surfbirds_DOT_com/birdingmail/Group/NYSBirds-L
3) birding_DOT_aba_DOT_org/maillist/NY01

Please submit your observations to eBird:
ebird_DOT_org/content/ebird/

--

Re: Please forgive a blatant plug: I reviewed v10 for the Reg

2024-05-02 Thread Jay Patel

https://archive.fosdem.org/2023/schedule/event/bsd_driver_harmony/attachments/slides/5976/export/events/attachments/bsd_driver_harmony/slides/5976/BSD_Driver_Harmony_FOSDEM.pdf
Talk from Last year 
Yahoo Mail: Search, organise, conquer 

  On Thu, 2 May 2024 at 3:14 pm, Liam Proven wrote:   On 
Wed, 1 May 2024 at 12:31, Greg Troxel  wrote:
>
> Liam Proven  writes:
>
> > Step 1: a binary interoperability standard, so apps from any BSD can
> > execute on any other BSD (on the same CPU architecture, obviously.)
>
> This is not so much about the binaries about about the ABI for libc and
> other core libs.  But I suspec this works better than you think, if one
> arranges for the other libs and deals with elf tags.

You are missing my point.

I am not asking "are they close?" or "are they compatible?" I am
saying: let's work out the differences, make a detailed specific list,
and see if it would be possible to work out a specific standard API so
that *the same binaries* could run on them all.

A modern BSD equivalent of the iBCS 2:
https://en.wikipedia.org/wiki/Intel_Binary_Compatibility_Standard

> All BSDs come from 386BSD and Net/2, said in a very broad brush way.

I know that. I have been working in the Unix industry and thus
watching this sector closely since half a decade before 386BSD was
released.

> It's not accurate to say that the kernels are unique. [...]

Again, you misunderstand and do not see my point.

I am saying: let us try to isolate and work out which parts of the 3
or 4 main BSD projects are specific to each OS and which are shared.

Each BSD's kernel is its own. Yes they are all related. We know that.
The clue is in the BSD name. But they are not the same any more and
merging the kernels would be both an epic job, as well as one that
nobody would want to do or to happen.

> > * Coreutils?
>
> coreutils is a term for a GNU package, and many/most of those
> utilities in BSDs aren't from that.  Really, coreutils is the linux
> reimplementation of traditional utilities.

I dispute that. It's just a name. Don't fixate on the name. Thing
about the thing that the name refers to.

Here is one set of BSD coreutils, ported to Linux:

https://github.com/DiegoMagdaleno/BSDCoreUtils

Here is another:

https://github.com/dcantrell/bsdutils

Here's a modernised port of that:

https://github.com/chimera-linux/chimerautils

It is an identifiable, discrete thing.

FWIW I have written about this subject as part of this article:

https://www.theregister.com/2023/02/13/chimera_non_gnu_linux/

> Lots of things are the same because they are from the same upstream,
> eg. OpenSSH.  But others are differnet.  Again you can't really slice it
> that way so easily.

I submit that there is a very important difference between "you can't
slice it" and "nobody has tried to slice it".

> Mostly these are the same upstreams, perhaps packaged differently.

I know. That is my point.

> emacs runs on all of them.  I'm not sure what your point is here.

My point is to try to reduce the maintenance load of the 4 separate
BSD projects by identifying where they overlap and moving those
duplicated sections into a shared codebase, which can be
collaboratively maintained by all the teams, reducing the maintenance
burden on those parts by, conservatively, 75%.

-- 
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Email: lpro...@cix.co.uk ~ gMail/gTalk/FB: lpro...@gmail.com
Twitter/LinkedIn: lproven ~ Skype: liamproven
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[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

2024-05-02 Thread Jay Foad via llvm-branch-commits


jayfoad wrote:

> Hi @jayfoad (or anyone else). If you would like to add a note about this fix 
> in the release notes (completely optional). Please reply to this comment with 
> a one or two sentence description of the fix. When you are done, please add 
> the release:note label to this PR.

I don't think this fix is particularly noteworthy. Would there already be a 
list of bugs fixed in the release notes?

https://github.com/llvm/llvm-project/pull/90204
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Partitions thought

2024-05-02 Thread Jay Patel

Hello,

Just an idea of partitions if this is possible and good to implement!

For eg. Default install will partition HDD as -> wd0a / "main" where base
NetBSD system files and folders resides

-> wd0b /N/ where "/home" and extended custom configs of system /etc for
rc.local. most important why this seperation is whenever user updates or
upgrades NetBSD based system or even reinstall all data and custom configs
won't be erased or merged during upgrading. For custom rc.conf arguments or
wpa supplicant configurations.


->wd0s Swap partition


Thanks,
Jay

[webkit-changes] [WebKit/WebKit] 139fe6: [ Ventura WK1 ] http/tests/media/hls/track-webvtt-...

2024-05-01 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 139fe6341785549039de1d359da5ac10cc7ab8fd
  
https://github.com/WebKit/WebKit/commit/139fe6341785549039de1d359da5ac10cc7ab8fd
  Author: Jay Stfleur 
  Date:   2024-05-01 (Wed, 01 May 2024)

  Changed paths:
M LayoutTests/platform/mac-wk1/TestExpectations

  Log Message:
  ---
  [ Ventura WK1 ] http/tests/media/hls/track-webvtt-multitracks.html is a 
mostly timeout/crash
https://bugs.webkit.org/show_bug.cgi?id=273577
rdar://127384137

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/mac-wk1/TestExpectations:

Canonical link: https://commits.webkit.org/278228@main



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Re: [RBW] FS: Supernova dynamo lights

2024-05-01 Thread Jay Lonner

Both sets of lights have been claimed. Thanks for all the interest.Jay LonnerBellingham, WASent from my Atari 400On Apr 28, 2024, at 7:43 PM, Jay Lonner wrote:Up for sale here are two sets of Supernova lights that are takeoffs from our Bike Fridays (Bikes Friday? What would William Safire say…). Each set includes a black anodized E3 Pro 2 headlight and Tail Light 2. The headlights are on Multimounts , and have spade connectors for a SON dynohub along with factory wiring to power the taillights. Mounted once, never used. Great lights, but dealing with the taillight wires really isn’t practical for bikes that will be broken down and reassembled frequently. We’re going to stick with dynamo headlights and USB rechargeable taillights. Each set would run ~$250 new, I’m looking for $125 per set, and I’ll cover the shipping. Willing to sell them separately.Jay LonnerBellingham, WA

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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-05-01 Thread Jay Foad via llvm-branch-commits


jayfoad wrote:

> Let's not backport this yet since @pendingchaos has pointed out a problem 
> with #90201.

Fixed by #90710 which I have added to this PR.

https://github.com/llvm/llvm-project/pull/90582
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-05-01 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad ready_for_review 
https://github.com/llvm/llvm-project/pull/90582
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-05-01 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad updated 
https://github.com/llvm/llvm-project/pull/90582

>From 17b75a9517891d662e677a357713c920bb79c43c Mon Sep 17 00:00:00 2001
From: David Stuttard 
Date: Tue, 30 Apr 2024 10:41:51 +0100
Subject: [PATCH 1/2] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load
 (#90201)

image_msaa_load is actually encoded as a VSAMPLE instruction and
requires the appropriate waitcnt variant.
---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp   |  8 --
 .../AMDGPU/llvm.amdgcn.image.msaa.load.ll | 26 +--
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp 
b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 6ecb1c8bf6e1db..97c55e4d9e41c2 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -187,8 +187,12 @@ VmemType getVmemType(const MachineInstr ) {
   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode());
   const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo =
   AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
-  return BaseInfo->BVH ? VMEM_BVH
-   : BaseInfo->Sampler ? VMEM_SAMPLER : VMEM_NOSAMPLER;
+  // The test for MSAA here is because gfx12+ image_msaa_load is actually
+  // encoded as VSAMPLE and requires the appropriate s_waitcnt variant for 
that.
+  // Pre-gfx12 doesn't care since all vmem types result in the same s_waitcnt.
+  return BaseInfo->BVH ? VMEM_BVH
+ : BaseInfo->Sampler || BaseInfo->MSAA ? VMEM_SAMPLER
+   : VMEM_NOSAMPLER;
 }
 
 unsigned (AMDGPU::Waitcnt , InstCounterType T) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
index 1348315e72e7bc..8da48551855570 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
@@ -12,7 +12,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg 
%rsrc, i32 %s, i32 %t,
 ; GFX12-LABEL: load_2dmsaa:
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 
dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: 
[0x06,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, 
i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -32,7 +32,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> 
inreg %rsrc, ptr addrsp
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:4], [v0, v1, v2], s[0:7] dmask:0x2 
dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ; encoding: 
[0x0e,0x20,0x86,0xe4,0x00,0x01,0x00,0x00,0x00,0x01,0x02,0x00]
 ; GFX12-NEXT:v_mov_b32_e32 v5, 0 ; encoding: [0x80,0x02,0x0a,0x7e]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:global_store_b32 v5, v4, s[8:9] ; encoding: 
[0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x05,0x00,0x00,0x00]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
@@ -53,7 +53,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> 
inreg %rsrc, i32 %s, i3
 ; GFX12-LABEL: load_2darraymsaa:
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0x4 
dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: 
[0x07,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i32(i32 
4, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -73,7 +73,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> 
inreg %rsrc, ptr ad
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:4], [v0, v1, v2, v3], s[0:7] dmask:0x8 
dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: 
[0x0f,0x20,0x06,0xe6,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
 ; GFX12-NEXT:v_mov_b32_e32 v5, 0 ; encoding: [0x80,0x02,0x0a,0x7e]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:global_store_b32 v5, v4, s[8:9] ; encoding: 
[0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x05,0x00,0x00,0x00]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
@@ -94,7 +94,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa_glc(<8 x i32> inreg 
%rsrc, i32 %s, i32
 ; GFX12-LABEL: load_2dmsaa_glc:
 ; GFX12:   ;

[llvm-branch-commits] [llvm] [AMDGPU] Enhance s_waitcnt insertion before barrier for gfx12 (#90595) (PR #90719)

2024-05-01 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad milestoned 
https://github.com/llvm/llvm-project/pull/90719
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[llvm-branch-commits] [llvm] [AMDGPU] Enhance s_waitcnt insertion before barrier for gfx12 (#90595) (PR #90719)

2024-05-01 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad created 
https://github.com/llvm/llvm-project/pull/90719

Code to determine if a waitcnt is required before a barrier instruction
only
considered S_BARRIER.
gfx12 adds barrier_signal/wait so need to enhance the existing code to
look for
a barrier start (which is just an S_BARRIER for earlier architectures).

>From e31113098e4669850f3ff924bead9e0fb9618f20 Mon Sep 17 00:00:00 2001
From: David Stuttard 
Date: Wed, 1 May 2024 11:37:13 +0100
Subject: [PATCH] [AMDGPU] Enhance s_waitcnt insertion before barrier for gfx12
 (#90595)

Code to determine if a waitcnt is required before a barrier instruction
only
considered S_BARRIER.
gfx12 adds barrier_signal/wait so need to enhance the existing code to
look for
a barrier start (which is just an S_BARRIER for earlier architectures).
---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp   |  2 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.h  | 11 ++
 .../CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll   |  2 ++
 .../AMDGPU/llvm.amdgcn.s.barrier.wait.ll  | 22 +++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp 
b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 6ecb1c8bf6e1db..7a3198612f86fc 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1832,7 +1832,7 @@ bool 
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr ,
   // not, we need to ensure the subtarget is capable of backing off barrier
   // instructions in case there are any outstanding memory operations that may
   // cause an exception. Otherwise, insert an explicit S_WAITCNT 0 here.
-  if (MI.getOpcode() == AMDGPU::S_BARRIER &&
+  if (TII->isBarrierStart(MI.getOpcode()) &&
   !ST->hasAutoWaitcntBeforeBarrier() && !ST->supportsBackOffBarrier()) {
 Wait = Wait.combined(
 AMDGPU::Waitcnt::allZero(ST->hasExtendedWaitCounts(), ST->hasVscnt()));
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h 
b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1c9dacc09f8154..626d903c0c6958 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -908,6 +908,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
   }
 
+  // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
+  // S_BARRIER, but after support for S_BARRIER_SIGNAL* / S_BARRIER_WAIT we 
want
+  // to check for the barrier start (S_BARRIER_SIGNAL*)
+  bool isBarrierStart(unsigned Opcode) const {
+return Opcode == AMDGPU::S_BARRIER ||
+   Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
+   Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
+   Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
+   Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
+  }
+
   static bool doesNotReadTiedSource(const MachineInstr ) {
 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
   }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
index a7d3115af29bff..47c021769aa56f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
@@ -96,6 +96,7 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) 
%out, i32 %size) #0 {
 ; VARIANT4-NEXT:s_wait_kmcnt 0x0
 ; VARIANT4-NEXT:v_xad_u32 v1, v0, -1, s2
 ; VARIANT4-NEXT:global_store_b32 v3, v0, s[0:1]
+; VARIANT4-NEXT:s_wait_storecnt 0x0
 ; VARIANT4-NEXT:s_barrier_signal -1
 ; VARIANT4-NEXT:s_barrier_wait -1
 ; VARIANT4-NEXT:v_ashrrev_i32_e32 v2, 31, v1
@@ -142,6 +143,7 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) 
%out, i32 %size) #0 {
 ; VARIANT6-NEXT:v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
 ; VARIANT6-NEXT:v_sub_nc_u32_e32 v1, s2, v0
 ; VARIANT6-NEXT:global_store_b32 v5, v0, s[0:1]
+; VARIANT6-NEXT:s_wait_storecnt 0x0
 ; VARIANT6-NEXT:s_barrier_signal -1
 ; VARIANT6-NEXT:s_barrier_wait -1
 ; VARIANT6-NEXT:v_ashrrev_i32_e32 v2, 31, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
index 4ab5e97964a857..38a34ec6daf73c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
@@ -12,6 +12,7 @@ define amdgpu_kernel void @test1_s_barrier_signal(ptr 
addrspace(1) %out) #0 {
 ; GCN-NEXT:v_sub_nc_u32_e32 v0, v1, v0
 ; GCN-NEXT:s_wait_kmcnt 0x0
 ; GCN-NEXT:global_store_b32 v3, v2, s[0:1]
+; GCN-NEXT:s_wait_storecnt 0x0
 ; GCN-NEXT:s_barrier_signal -1
 ; GCN-NEXT:s_barrier_wait -1
 ; GCN-NEXT:global_store_b32 v3, v0, s[0:1]
@@ -28,6 +29,7 @@ define amdgpu_kernel void @test1_s_barrier_signal(ptr 
addrspace(1) %out) #0 {
 ; GLOBAL-ISEL-NEXT:v_sub_nc_u32_e32 v0, v1, v0
 ; GLOBAL-ISEL-NEXT:s_wait_kmcnt 0x0
 ; GLOBAL-ISEL-NEXT:

Steve Bellovin retires

2024-04-30 Thread Jay Ashworth

Steve Bellovin retires:

https://mastodon.lawprofs.org/@SteveBellovin/112362015712050310
-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

[webkit-changes] [WebKit/WebKit] 008a00: [ Ventura WK1 Debug ] 2x imported/w3c/web-platform...

2024-04-30 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 008a006df2707ebec59620aacbe3156b86224df4
  
https://github.com/WebKit/WebKit/commit/008a006df2707ebec59620aacbe3156b86224df4
  Author: Jay Stfleur 
  Date:   2024-04-30 (Tue, 30 Apr 2024)

  Changed paths:
M LayoutTests/platform/mac-wk1/TestExpectations

  Log Message:
  ---
  [ Ventura WK1 Debug ] 2x 
imported/w3c/web-platform-tests/html/semantics/embedded-content/media-elements/track/track-element/track-mode
 are constant crashes
https://bugs.webkit.org/show_bug.cgi?id=273501
rdar://127302101

Unreviewed test gardening.

Adding test expectation.

* LayoutTests/platform/mac-wk1/TestExpectations:

Canonical link: https://commits.webkit.org/278174@main



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Re: [Histonet] Alcohol

2024-04-30 Thread Jay Lundgren via Histonet

Call StatLab,
1-800-442-3573



On Mon, Apr 29, 2024 at 6:49 PM Naira Margaryan via Histonet <
histonet@lists.utsouthwestern.edu> wrote:

> Hello,
>
> What type of ALCOHOL ETHYL you’re using in your histology lab.?
>
> We are thinking to get 20-30-gal drum.
>
> Could you please help me with that?
>
>
>
> Your suggestion is appreciated,
>
> Naira
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[clang] [compiler-rt] [libc] [libclc] [libcxxabi] [lld] [lldb] [llvm] [mlir] Add clarifying parenthesis around non-trivial conditions in ternary expressions. (PR #90391)

2024-04-30 Thread Jay Foad via cfe-commits


jayfoad wrote:

AMDGPU changes are fine.

https://github.com/llvm/llvm-project/pull/90391
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[Lldb-commits] [clang] [compiler-rt] [libc] [libclc] [libcxxabi] [lld] [lldb] [llvm] [mlir] Add clarifying parenthesis around non-trivial conditions in ternary expressions. (PR #90391)

2024-04-30 Thread Jay Foad via lldb-commits


jayfoad wrote:

AMDGPU changes are fine.

https://github.com/llvm/llvm-project/pull/90391
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-04-30 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad converted_to_draft 
https://github.com/llvm/llvm-project/pull/90582
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-04-30 Thread Jay Foad via llvm-branch-commits


jayfoad wrote:

Let's not backport this yet since @pendingchaos has pointed out a problem with 
#90201.

https://github.com/llvm/llvm-project/pull/90582
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-04-30 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad milestoned 
https://github.com/llvm/llvm-project/pull/90582
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[llvm-branch-commits] [llvm] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201) (PR #90582)

2024-04-30 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad created 
https://github.com/llvm/llvm-project/pull/90582

image_msaa_load is actually encoded as a VSAMPLE instruction and
requires the appropriate waitcnt variant.


>From 17b75a9517891d662e677a357713c920bb79c43c Mon Sep 17 00:00:00 2001
From: David Stuttard 
Date: Tue, 30 Apr 2024 10:41:51 +0100
Subject: [PATCH] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load (#90201)

image_msaa_load is actually encoded as a VSAMPLE instruction and
requires the appropriate waitcnt variant.
---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp   |  8 --
 .../AMDGPU/llvm.amdgcn.image.msaa.load.ll | 26 +--
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp 
b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 6ecb1c8bf6e1db..97c55e4d9e41c2 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -187,8 +187,12 @@ VmemType getVmemType(const MachineInstr ) {
   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode());
   const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo =
   AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
-  return BaseInfo->BVH ? VMEM_BVH
-   : BaseInfo->Sampler ? VMEM_SAMPLER : VMEM_NOSAMPLER;
+  // The test for MSAA here is because gfx12+ image_msaa_load is actually
+  // encoded as VSAMPLE and requires the appropriate s_waitcnt variant for 
that.
+  // Pre-gfx12 doesn't care since all vmem types result in the same s_waitcnt.
+  return BaseInfo->BVH ? VMEM_BVH
+ : BaseInfo->Sampler || BaseInfo->MSAA ? VMEM_SAMPLER
+   : VMEM_NOSAMPLER;
 }
 
 unsigned (AMDGPU::Waitcnt , InstCounterType T) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
index 1348315e72e7bc..8da48551855570 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
@@ -12,7 +12,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg 
%rsrc, i32 %s, i32 %t,
 ; GFX12-LABEL: load_2dmsaa:
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:3], [v0, v1, v2], s[0:7] dmask:0x1 
dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: 
[0x06,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x00]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, 
i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -32,7 +32,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> 
inreg %rsrc, ptr addrsp
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:4], [v0, v1, v2], s[0:7] dmask:0x2 
dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ; encoding: 
[0x0e,0x20,0x86,0xe4,0x00,0x01,0x00,0x00,0x00,0x01,0x02,0x00]
 ; GFX12-NEXT:v_mov_b32_e32 v5, 0 ; encoding: [0x80,0x02,0x0a,0x7e]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:global_store_b32 v5, v4, s[8:9] ; encoding: 
[0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x05,0x00,0x00,0x00]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
@@ -53,7 +53,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> 
inreg %rsrc, i32 %s, i3
 ; GFX12-LABEL: load_2darraymsaa:
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0x4 
dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: 
[0x07,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i32(i32 
4, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
@@ -73,7 +73,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> 
inreg %rsrc, ptr ad
 ; GFX12:   ; %bb.0: ; %main_body
 ; GFX12-NEXT:image_msaa_load v[0:4], [v0, v1, v2, v3], s[0:7] dmask:0x8 
dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: 
[0x0f,0x20,0x06,0xe6,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03]
 ; GFX12-NEXT:v_mov_b32_e32 v5, 0 ; encoding: [0x80,0x02,0x0a,0x7e]
-; GFX12-NEXT:s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf]
+; GFX12-NEXT:s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
 ; GFX12-NEXT:global_store_b32 v5, v4, s[8:9] ; encoding: 
[0x08,0x80,0x06,0xee,0x00,0x00,0x00,0x02,0x05,0x00,0x00,0x00]
 ; GFX12-NEXT:; return to shader part epilog
 main_body:
@@ -94,7 +94,7 @@ define amdgpu_ps <4 x float>

Bug#1036183:

2024-04-29 Thread Jay

It took me a while to wrap my mind around what was going on with PATH, gdm,
wayland sessions, X sessions, and systemd environment generators.

I'll try to summarize my findings here.

I initially found this change[0] to be the cause, but I am still not exactly
sure why or how it works.

I have been informed that we may be better off using systemd environment
generators[1][2] and import PATH from systemd which pulls from Debian's
/etc/profile.

Another suggestion is that we stop using /usr/games[3].


0: 
https://gitlab.gnome.org/GNOME/gdm/-/merge_requests/92/diffs?commit_id=ccecd9c975d04da80db4cd547b67a1a94fa83292
1: https://gitlab.gnome.org/GNOME/gdm/-/issues/846
2: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1037084#10
3: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1028543#15

Re: [Cake] [Bloat] [Rpm] [Starlink] [LibreQoS] the grinch meets cloudflare'schristmas present

2024-04-29 Thread Jay Moran via Cake

Quick note from reading your blog entry.

Last night, I played with the Cloudflare Speedtest a little. It downloads
25MB and a 50MB (or 100MB, can’t remember) as well on a “speedier” network
after it does the 10MB file.

I was getting 1.2Gbs down and 760Mbs up, 4ms of LUL, and seeing those
larger file sizes. I was trying to screenshot and noticed I had those extra
file sizes I had to scroll down for. I ended up getting distracted and not
taking the shot to send. But, it will do a longer/bigger test under right
conditions.

Network here at the house is AT Fiber, 5Gbs up/down - limited to 3.6Gbs
down from Ubiquity UDM SE router/firewall with all IPS/Geo-blocking turned
on. 4.7Gbs non-blocking up. I am building a pfSense box to eliminate the
bottleneck. Couldn’t be happier, good job AS7018.

The machine I was testing from was Win10 wired 10Gbs and gets ~2.2Gbs
up/down for fast.com/speedtest.net. I haven’t take time to test internally
or try and tune that system, or might be CAT5e cabling issue… is fast
enough for me for that system.

Jay

On Wed, Jan 11, 2023 at 12:07 AM Dave Taht via Bloat <
bl...@lists.bufferbloat.net> wrote:

> Dear Luis:
>
> You hit 17 seconds of delay on your test.
>
> I got you beat, today, on my LTE connection, I cracked 182 seconds.
>
> I'd like to thank Verizon for making it possible for me to spew 4000
> words on my kvetches about the current speedtest regimes of speedtest,
> cloudflare, and so on, by making my network connection so lousy today
> that I sat in front of emacs to rant - and y'all for helping tone
> down, a little, this blog entry:
>
> https://blog.cerowrt.org/post/speedtests/
>
> On Tue, Jan 10, 2023 at 9:25 AM Luis A. Cornejo via Rpm
>  wrote:
> >
> > Here is my VZ HSI
> >
> >
> > No SQMm on
> >
> > On Sat, Jan 7, 2023 at 6:38 PM Dick Roy via Bloat <
> bl...@lists.bufferbloat.net> wrote:
> >>
> >>
> >>
> >>
> >>
> >> -Original Message-
> >> From: rjmcmahon [mailto:rjmcma...@rjmcmahon.com]
> >> Sent: Friday, January 6, 2023 3:45 PM
> >> To: dick...@alum.mit.edu
> >> Cc: 'MORTON JR., AL'; 'IETF IPPM WG'; 'libreqos'; 'Cake List'; 'Rpm';
> 'bloat'
> >> Subject: Re: [Starlink] [Rpm] [LibreQoS] the grinch meets
> cloudflare'schristmas present
> >>
> >>
> >>
> >> yeah, I'd prefer not to output CLT sample groups at all but the
> >>
> >> histograms aren't really human readable and users constantly ask for
> >>
> >> them. I thought about providing a distance from the gaussian as output
> >>
> >> too but so far few would understand it and nobody I found would act upon
> >>
> >> it.
> >>
> >> [RR] Understandable until such metrics are “actionable”, and that’s “up
> to us to find/define/figure out” it seems to me. Metrics that are not
> actionable are write-only memory and good for little but historical recordJ
> >>
> >> The tool produces the full histograms so no information is really
> >>
> >> missing except for maybe better time series analysis.
> >>
> >> [RR] Isn’t that in fact what we are trying to extract from the e2e
> stats we collect?  i.e., infer the time evolution of the system from its
> I/O behavior? As you point out, it’s really hard to do without probes in
> the guts of the system, nd yes, synchronization is important J
> >>
> >>
> >>
> >> The open source flows python code also released with iperf 2 does use
> >>
> >> the komogorov-smirnov distances & distance matrices to cluster when the
> >>
> >> number of histograms are just too much. We've analyzed 1M runs to fault
> >>
> >> isolate the "unexpected interruptions" or "bugs" and without statistical
> >>
> >> support it is just not doable. This does require instrumentation of the
> >>
> >> full path with mapping to a common clock domain (e.g. GPS) and not just
> >>
> >> e2e stats. I find an e2e complaint by an end user about "poor speed" as
> >>
> >> useful as telling a pharmacist I have a fever. Not much diagnostically
> >>
> >> is going on. Take an aspirin.
> >>
> >> [RR] That’s AWESOME!! I love that analogy!
> >>
> >>
> >>
> >> RR
> >>
> >>
> >>
> >> https://en.wikipedia.org/wiki/Kolmogorov%E2%80%93Smirnov_test
> >>
> >> https://sourceforge.net/p/iperf2/code/ci/master/tree/flows/flows.py
> >>
> >>
> >>
> >> Bob
> >>
>

Re: [PATCH] drm/amdkfd: update buffer_{store,load}_* modifiers for gfx940

2024-04-29 Thread Jay Cornwall


On 4/29/2024 06:06, Lancelot SIX wrote:

Instruction modifiers of the untyped vector memory buffer instructions
(MUBUF encoded) changed in gfx940.  The slc, scc and glc modifiers have
been replaced with sc0, sc1 and nt.

The current CWSR trap handler is written using pre-gfx940 modifier
names, making the source incompatible with a strict gfx940 assembler.

This patch updates the cwsr_trap_handler_gfx9.s source file to be
compatible with all gfx9 variants of the ISA.  The binary assembled code
is unchanged (so the behaviour is unchanged as well), only the source
representation is updated.

Signed-off-by: Lancelot SIX 
---
  .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 24 ---
  1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm 
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
index bb26338204f4..a2d597d7fb57 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
@@ -48,6 +48,12 @@ var ACK_SQC_STORE=   1   
//workaround for suspected SQC store bug causing
  var SAVE_AFTER_XNACK_ERROR=   1   //workaround for 
TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
  var SINGLE_STEP_MISSED_WORKAROUND   = (ASIC_FAMILY <= CHIP_ALDEBARAN)  
//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
  
+#if ASIC_FAMILY < CHIP_GC_9_4_3

+#define VMEM_MODIFIERS slc:1 glc:1
+#else
+#define VMEM_MODIFIERS sc0:1 nt:1
+#endif
+
  /**/
  /*variables */
  /**/
@@ -581,7 +587,7 @@ end
  L_SAVE_LDS_LOOP_VECTOR:
ds_read_b64 v[0:1], v2  //x =LDS[a], byte address
s_waitcnt lgkmcnt(0)
-  buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset 
offen:1  glc:1  slc:1
+  buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset 
VMEM_MODIFIERS offen:1
  //s_waitcnt vmcnt(0)
  //v_add_u32 v2, vcc[0:1], v2, v3
v_add_u32 v2, v2, v3
@@ -979,17 +985,17 @@ L_TCP_STORE_CHECK_DONE:
  end
  
  function write_4vgprs_to_mem(s_rsrc, s_mem_offset)

-   buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
-   buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256
-   buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1  
offset:256*2
-   buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1  
offset:256*3
+   buffer_store_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS
+   buffer_store_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 
offset:256
+   buffer_store_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 
offset:256*2
+   buffer_store_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 
offset:256*3
  end
  
  function read_4vgprs_from_mem(s_rsrc, s_mem_offset)

-   buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
-   buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
-   buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
-   buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
+   buffer_load_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS
+   buffer_load_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256
+   buffer_load_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 
offset:256*2
+   buffer_load_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 
offset:256*3
s_waitcnt vmcnt(0)
  end
  


base-commit: cf743996352e327f483dc7d66606c90276f57380


Reviewed-by: Jay Cornwall

Bug#1037084:

2024-04-29 Thread Jay

On Sat, Jun 17, 2023 at 4:55 AM Alban Browaeys  wrote:
> This bug would likely be fixed by Debian (the systemd package?)
> shipping a /usr/lib/systemd/user-environment-generators/ systemd user
> environment generator with the default PATH Debian already set in
> /etc/profile.
I plan to check with the Debian systemd package maintainers about this option.

But
> Or ship an  /usr/lib/environment.d/*.conf file (which itself is read by
> a systemd user environment generator : /usr/lib/systemd/user-
> environment-generators/30-systemd-environment-d-generator).
This might be the solution we're looking for. A
/usr/lib/environment.d/??-gdm3.conf file
provided by the gdm3 package?

Bug#1037084:

2024-04-29 Thread Jay

On Sat, Jun 17, 2023 at 4:55 AM Alban Browaeys  wrote:
> This bug would likely be fixed by Debian (the systemd package?)
> shipping a /usr/lib/systemd/user-environment-generators/ systemd user
> environment generator with the default PATH Debian already set in
> /etc/profile.
I plan to check with the Debian systemd package maintainers about this option.

But
> Or ship an  /usr/lib/environment.d/*.conf file (which itself is read by
> a systemd user environment generator : /usr/lib/systemd/user-
> environment-generators/30-systemd-environment-d-generator).
This might be the solution we're looking for. A
/usr/lib/environment.d/??-gdm3.conf file
provided by the gdm3 package?

[edk2-devel] [Question] VM failed to start with secure boot and TPM 2.0

2024-04-29 Thread Zhoujian (jay) via groups.io

Hi all,

We encountered a problem that the virtual machine failed to start. Our
Configuration is as follows:
1. Use qemu 4.1.0 and edk2 202011 for x86 test, and qemu 7.1.0 and edk2 202011
for arm test
2. Enable secure boot and TPM 2.0.
3. Import the PK [1]\KEK [2]\db [3]\dbx [4]certificates.
4. VM started with 60 disks and 7 network cards

The log of serial port reported the errors:
```
Could not create MokListRT: Volume full
Could not create MokListXRT: Volume full
Could not create SbatlevelRT: Volume full
Could not create MokListTrustedRT: Volume full
Something has gone seriously wrong: import_mok_state() failed : Volume Full
```

TPM measures part of UEFI variables, include PK/KEK/db/dbx, BootOrder and so
on. It calls Tcg2HashLogExtendEvent (edk2 SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c)
to write to event log. Currently the event log length is 64 KB, if full,
Tcg2HashLogExtendEvent returned EFI_VOLUME_FULL which caused the VM
failed to start.

I found some description about variable area length and event log area length.
After using tpm2-tool to parse the event logs, we found that event log of a
variable contains variable data. Theoretically, the variable size can exceed
64KB, as long as it does not exceed 256KB. Maybe event log area length
should be greater than variable area length ?

In section 9.2 of TCG PC Client Platform Firmware Profile Specification [5]:
```
The Log Area Minimum Length for the TCG event log MUST be at least 64KB.
```

In source code [6] of edk2:
```
## This PCD defines minimum length(in bytes) of the system preboot TCG event 
log area(LAML).
# For PC Client Implementation spec up to and including 1.2 the minimum log 
size is 64KB.
# @Prompt Minimum length(in bytes) of the system preboot TCG event log 
area(LAML).
gEfiSecurityPkgTokenSpaceGuid.PcdTcgLogAreaMinLen|0x1|UINT32|0x00010017
```

In source code [7] of edk2:
```
!if $(FD_SIZE_IN_KB) == 4096 <- - - - - -  # it is true in our configuration
# Size: 0x4 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
# 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
# This can speed up the Variable Dispatch a bit.
0xB8, 0xFF, 0x03, 0x00,
!endif
```

Based on the above analysis, We tried two solutions:
1. We modify the TcgCommLogEvent function in edk2 to ignore the
EFI_VOLUME_FULL error, return EFI_SUCCESS but not write event log. This idea
refers to [8].
2. We increase the value of PcdTcgLogAreaMinLen because TCG only defines
minimum length. And tpm2-tools has supported event logs longer than 64KB [9].

Both solutions can make the virtual machine start successfully but not sure if
they introduce other problems. For the first solution, we are worried that
the missing part of the event log will affect the TPM's function. For the
second solution, we are not sure if this change will have any impact on other
components.

Could you give us some advices?

Thanks

References:
[1] https://go.microsoft.com/fwlink/?linkid=2255361
[2] https://go.microsoft.com/fwlink/p/?linkid=321185
[3] https://go.microsoft.com/fwlink/?LinkId=321192
[4] https://uefi.org/sites/default/files/resources/x64_DBXUpdate.bin
[5] 
https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/
[6] https://github.com/tianocore/edk2/blob/master/SecurityPkg/SecurityPkg.dec
[7] https://github.com/tianocore/edk2/blob/master/OvmfPkg/Bhyve/VarStore.fdf.inc
[8] https://github.com/rhboot/shim/pull/657
[9] https://github.com/tpm2-software/tpm2-tools/pull/2683


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[RBW] FS: Supernova dynamo lights

2024-04-28 Thread Jay Lonner

Up for sale here are two sets of Supernova lights that are takeoffs from 
our Bike Fridays (Bikes Friday? What would William Safire say…). Each set 
includes a black anodized E3 Pro 2 headlight and Tail Light 2. The 
headlights are on Multimounts , and have spade connectors for a SON dynohub 
along with factory wiring to power the taillights. Mounted once, never 
used. Great lights, but dealing with the taillight wires really isn’t 
practical for bikes that will be broken down and reassembled frequently. 
We’re going to stick with dynamo headlights and USB rechargeable 
taillights. 

Each set would run ~$250 new, I’m looking for $125 per set, and I’ll cover 
the shipping. Willing to sell them separately.

Jay Lonner
Bellingham, WA

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Bug#1067196: qpdf: contrary to the documentation, fix-qdf aborts on removed objects

2024-04-28 Thread Jay Berkenbilt

(Sorry for the duplicate -- I inadvertently failed to cc the bug report on my 
private reply.)

On Sun, Apr 14, 2024, at 1:50 PM, Thorsten Glaser wrote:
> Jay Berkenbilt dixit:
> 
> >As it happens, I am upstream.
> 
> Oh, nice ☻ in that case, thanks for qpdf.
> 
> >---
> >It is not generally practical to remove objects from QDF files without
> >messing up object numbering, but if you remove all indirect references
> >to an object (without removing the object itself), this will leave the
> >object unreferenced. Then you can run qpdf on the file (after running
> >:command:`fix-qdf`), and qpdf will omit the now-orphaned object.
> >---
> 
> That fixes the ambiguity but leaves the reader¹ wondering, on two
> reading passes, what other references than indirect there are.
> The reader who has not digested the PDF spec in and out, at least.
> 
> If you s/ indirect//, would it still be correct? That would be
> less possibly-ambiguous, I think.

If it triggers this thought in you, it will trigger it in others. New wording:

It is not generally practical to remove objects from QDF files without
messing up object numbering, but if you remove all references to an
object without removing the object itself (by removing all indirect
objects that point to it), this will leave the object unreferenced.
Then you can run qpdf on the file (after running :command:`fix-qdf`),
and qpdf will omit the now-orphaned object.

> bye,
> //mirabilos
> ① or at least me right now
> -- 
>  Beware of ritual lest you forget the meaning behind it.
>  yeah but it means if you really care about something, don't
> ritualise it, or you will lose it. don't fetishise it, don't
> obsess. or you'll forget why you love it in the first place.
>

[RBW] Re: Rivendell (Roadini) Geometry

2024-04-28 Thread Jay

Thanks for the messages.

I still have about 15mm I can push the saddle forward, just have to switch 
saddle bags.

I've been between sizes before, always made the larger one work.  Smaller 
bike, not as well (25mm setback post and 120mm stem make for a strange 
ride).

I've had bike fits, as recently as two months ago; how I sit on a saddle 
always surprises the fitter and we push the saddle forward.

I've been on some 3-4 hour rides and it's pretty comfy, just need to make 
this tweak.

On Sunday, April 28, 2024 at 11:43:11 AM UTC-4 Tony Lockhart wrote:

> Hi Jay,
> Sorry to hear that things aren't working at the moment. Have you thought 
> about getting a professional bike fit? Or perhaps making various 
> adjustments and documenting them over and extended period time?
>
> FWIW, I'm also on a 57cm Roadini with 170mm S!lver Cranks, Nitto 65 seat 
> post, and Brooks Professional saddle (86pbh, 5'9", longer legs shorter 
> torso). When I called Riv last winter, Grant mentioned that I'd be happy on 
> a 54 or 57 Leo depending on how much exposed seat post I'd be willing to 
> live with. In practice, I find that I need to push the saddle all the way 
> back in order to get comfy. I'm surprised to hear that you're pushing it 
> forward, but I'm guessing not all Brooks' are made the same. Like Brent, 
> I've also got a Hillborne (mine is a 56cm frame from 2009; same saddle, 
> crank, seat post as my Leo) and I'm super comfy on it. Keep in mind that 
> I've figured out what works for me during the past 14 years of ownership of 
> the Sam, and the Leo is very similar in size and riding characteristics. 
>
> I hope you get things dialed in.
> Tony
>
> On Saturday, April 27, 2024 at 7:23:08 PM UTC-7 Jay wrote:
>
>> I've been enjoying my first Riv, a Roadini, since getting it in February. 
>>  Just one thing I feel like I'm struggling with, saddle set back.
>>
>> It's a size 57, I'm 5'11 and my PHB meant a 57 or 54 would work.  It came 
>> with the setback seat post and that put me really far behind the BB 
>> compared to my other bikes, so I got a zero offset post and that helped 
>> things, but I'm still running my Brooks C17 pushed 3/4 of the way forward 
>> on the rails.  Funny thing is my Salsa Fargo, which has a 73 degree ST 
>> angle, vs. 72 on the Roadini, running the same saddle, and less set back 
>> (also on a zero offset post).  I can feel the difference when I'm pedaling; 
>> on the Fargo, my pedal stroke feels really good.  On the Roadini it feels 
>> like the pedals are out in front and I'm over-using posterior chain in an 
>> unnatural pedal stroke.  I measure setback on both bikes and the Fargo is 
>> coming out as saddle 5.5cm setback from BB, 7cm on the Roadini.
>>
>> Anyone else notice this?  I may try pushing the saddle all the way 
>> forward on the rails, then maybe set post up a bit, but wanted to ask this 
>> question first.
>>
>> Thanks!
>>
>

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[RBW] Rivendell (Roadini) Geometry

2024-04-27 Thread Jay

I've been enjoying my first Riv, a Roadini, since getting it in February.
Just one thing I feel like I'm struggling with, saddle set back.

It's a size 57, I'm 5'11 and my PHB meant a 57 or 54 would work. It came
with the setback seat post and that put me really far behind the BB
compared to my other bikes, so I got a zero offset post and that helped
things, but I'm still running my Brooks C17 pushed 3/4 of the way forward
on the rails. Funny thing is my Salsa Fargo, which has a 73 degree ST
angle, vs. 72 on the Roadini, running the same saddle, and less set back
(also on a zero offset post). I can feel the difference when I'm pedaling;
on the Fargo, my pedal stroke feels really good. On the Roadini it feels
like the pedals are out in front and I'm over-using posterior chain in an
unnatural pedal stroke. I measure setback on both bikes and the Fargo is
coming out as saddle 5.5cm setback from BB, 7cm on the Roadini.

Anyone else notice this? I may try pushing the saddle all the way forward
on the rails, then maybe set post up a bit, but wanted to ask this question
first.

Thanks!

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Re: [RE-wrenches] Large transformer losses

2024-04-26 Thread Jay via RE-wrenches

According to the nameplate 6% @ 170°cOn Apr 26, 2024, at 4:33 PM, Darryl Thayer via RE-wrenches  wrote:Do you know the transformer impedance?On Fri, Apr 26, 2024, 5:54 PM Jay via RE-wrenches <re-wrenches@lists.re-wrenches.org> wrote:Hi all. 

Anyone know what the tare loss and efficiency is of a 75 kw transformer?
And it would be run mostly at 1-10kw max. 

This one specifically. 
hammond SG3L0075PE

I’m just curious about it. The situation is 240vac grid at the street, 600’ to the house 400 amps. 


Why 400 amps on a house with propane heat, cooking, water heater, dryer and no AC. 
I don’t know. 

Thanks
Jay



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[llvm-branch-commits] [llvm] b544217 - [AMDGPU] Fix setting nontemporal in memory legalizer (#83815)

2024-04-26 Thread Jay Foad via llvm-branch-commits


Author: Mirko Brkušanin
Date: 2024-04-26T13:35:58+01:00
New Revision: b544217fb31ffafb9b072de53a28c71acc169cf8

URL: 
https://github.com/llvm/llvm-project/commit/b544217fb31ffafb9b072de53a28c71acc169cf8
DIFF: 
https://github.com/llvm/llvm-project/commit/b544217fb31ffafb9b072de53a28c71acc169cf8.diff

LOG: [AMDGPU] Fix setting nontemporal in memory legalizer (#83815)

Iterator MI can advance in insertWait() but we need original instruction
to set temporal hint. Just move it before handling volatile.

Added: 


Modified: 
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll

Removed: 




diff  --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp 
b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 84b9330ef9633e..50d8bfa8750818 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -2358,6 +2358,11 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
 
   bool Changed = false;
 
+  if (IsNonTemporal) {
+// Set non-temporal hint for all cache levels.
+Changed |= setTH(MI, AMDGPU::CPol::TH_NT);
+  }
+
   if (IsVolatile) {
 Changed |= setScope(MI, AMDGPU::CPol::SCOPE_SYS);
 
@@ -2370,11 +2375,6 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
   Position::AFTER);
   }
 
-  if (IsNonTemporal) {
-// Set non-temporal hint for all cache levels.
-Changed |= setTH(MI, AMDGPU::CPol::TH_NT);
-  }
-
   return Changed;
 }
 

diff  --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll 
b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
index a59c0394bebe20..ca7486536cf556 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
@@ -582,5 +582,170 @@ entry:
   ret void
 }
 
+define amdgpu_kernel void @flat_nontemporal_volatile_load(
+; GFX7-LABEL: flat_nontemporal_volatile_load:
+; GFX7:   ; %bb.0: ; %entry
+; GFX7-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-NEXT:s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:v_mov_b32_e32 v0, s0
+; GFX7-NEXT:v_mov_b32_e32 v1, s1
+; GFX7-NEXT:flat_load_dword v2, v[0:1] glc
+; GFX7-NEXT:s_waitcnt vmcnt(0)
+; GFX7-NEXT:v_mov_b32_e32 v0, s2
+; GFX7-NEXT:v_mov_b32_e32 v1, s3
+; GFX7-NEXT:s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:flat_store_dword v[0:1], v2
+; GFX7-NEXT:s_endpgm
+;
+; GFX10-WGP-LABEL: flat_nontemporal_volatile_load:
+; GFX10-WGP:   ; %bb.0: ; %entry
+; GFX10-WGP-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-WGP-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-WGP-NEXT:v_mov_b32_e32 v0, s0
+; GFX10-WGP-NEXT:v_mov_b32_e32 v1, s1
+; GFX10-WGP-NEXT:flat_load_dword v2, v[0:1] glc dlc
+; GFX10-WGP-NEXT:s_waitcnt vmcnt(0)
+; GFX10-WGP-NEXT:v_mov_b32_e32 v0, s2
+; GFX10-WGP-NEXT:v_mov_b32_e32 v1, s3
+; GFX10-WGP-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-WGP-NEXT:flat_store_dword v[0:1], v2
+; GFX10-WGP-NEXT:s_endpgm
+;
+; GFX10-CU-LABEL: flat_nontemporal_volatile_load:
+; GFX10-CU:   ; %bb.0: ; %entry
+; GFX10-CU-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-CU-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-CU-NEXT:v_mov_b32_e32 v0, s0
+; GFX10-CU-NEXT:v_mov_b32_e32 v1, s1
+; GFX10-CU-NEXT:flat_load_dword v2, v[0:1] glc dlc
+; GFX10-CU-NEXT:s_waitcnt vmcnt(0)
+; GFX10-CU-NEXT:v_mov_b32_e32 v0, s2
+; GFX10-CU-NEXT:v_mov_b32_e32 v1, s3
+; GFX10-CU-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-CU-NEXT:flat_store_dword v[0:1], v2
+; GFX10-CU-NEXT:s_endpgm
+;
+; SKIP-CACHE-INV-LABEL: flat_nontemporal_volatile_load:
+; SKIP-CACHE-INV:   ; %bb.0: ; %entry
+; SKIP-CACHE-INV-NEXT:s_load_dwordx4 s[0:3], s[0:1], 0x0
+; SKIP-CACHE-INV-NEXT:s_waitcnt lgkmcnt(0)
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v0, s0
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v1, s1
+; SKIP-CACHE-INV-NEXT:flat_load_dword v2, v[0:1] glc
+; SKIP-CACHE-INV-NEXT:s_waitcnt vmcnt(0)
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v0, s2
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v1, s3
+; SKIP-CACHE-INV-NEXT:s_waitcnt lgkmcnt(0)
+; SKIP-CACHE-INV-NEXT:flat_store_dword v[0:1], v2
+; SKIP-CACHE-INV-NEXT:s_endpgm
+;
+; GFX90A-NOTTGSPLIT-LABEL: flat_nontemporal_volatile_load:
+; GFX90A-NOTTGSPLIT:   ; %bb.0: ; %entry
+; GFX90A-NOTTGSPLIT-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX90A-NOTTGSPLIT-NEXT:s_waitcnt lgkmcnt(0)
+; GFX90A-NOTTGSPLIT-NEXT:v_mov_b32_e32 v0, s0
+; GFX90A-NOTTGSPLIT-NEXT:v_mov_b32_e32 v1, s1
+; GFX90A-NOTTGSPLIT-NEXT:flat_load_dword v2, v[0:1] glc
+; GFX90A-NOTTGSPLIT-NEXT:s_waitcnt vmcnt(0)

[webkit-changes] [WebKit/WebKit] 5859cb: [ iOS 17 Debug ] ASSERTION FAILED: containingBlock...

2024-04-26 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 5859cb6b941d46247e2f57e589cd3202e6fa59b5
  
https://github.com/WebKit/WebKit/commit/5859cb6b941d46247e2f57e589cd3202e6fa59b5
  Author: Jay Stfleur 
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  [ iOS 17 Debug ] ASSERTION FAILED: containingBlock.isInFlowPositioned() on 
imported/w3c/web-platform-tests/html/dom/elements/global-attributes/the-anchor-attribute-003-crash.tentative.html
https://bugs.webkit.org/show_bug.cgi?id=268557
rdar://122108986

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278065@main



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[webkit-changes] [WebKit/WebKit] 276e11: REGRESSION ( 275227@main): [ MacOS Debug ] importe...

2024-04-26 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 276e11ba088ff5247fb2fc388e1030cf1e0a0b08
  
https://github.com/WebKit/WebKit/commit/276e11ba088ff5247fb2fc388e1030cf1e0a0b08
  Author: Jay Stfleur 
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
M LayoutTests/platform/mac-wk2/TestExpectations

  Log Message:
  ---
  REGRESSION ( 275227@main): [ MacOS Debug ] 
imported/w3c/web-platform-tests/css/css-view-transitions/offscreen-element-modified-before-coming-onscreen.html
 is a constant crash
https://bugs.webkit.org/show_bug.cgi?id=269996
rdar://123516775

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac-wk2/TestExpectations:

Canonical link: https://commits.webkit.org/278064@main



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[RE-wrenches] Large transformer losses

2024-04-26 Thread Jay via RE-wrenches

Hi all. 

Anyone know what the tare loss and efficiency is of a 75 kw transformer?
And it would be run mostly at 1-10kw max. 

This one specifically. 
hammond SG3L0075PE

I’m just curious about it. The situation is 240vac grid at the street, 600’ to 
the house 400 amps. 


Why 400 amps on a house with propane heat, cooking, water heater, dryer and no 
AC. 
I don’t know. 

Thanks
Jay



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Re: [RE-wrenches] 120 Vac and 12Vdc mixed distribution system

2024-04-26 Thread Jay via RE-wrenches

I’ve had no issues with qo over the years for 12v except if they get dirt in them from mud dobber wasps. JayOn Apr 26, 2024, at 9:05 AM, Darryl Thayer via RE-wrenches  wrote:I agree with John also.  one of the better-performing off-grid houses I worked on used a 48 to 12-V Samlex converter. The 12-volt thick-walled refrigerator was about 4 amps at 12 volts. The lights, radio, and small TV drew very few amps each/  I also used an Outback 3648 inverter, which the homeowner turned on only. when needed (wash machine, etc.), I used SQ-D QO panel board in case the owner wanted to go to 120 volt AC future breaker panel. All lighting was Edison base lamps, and all wiring was NMB Romex.  I wired like a normal house except for a 120-v panel and 12-v panel I relay and momentary switch by appliance for easy turning on of AC inverter.   On Wed, Apr 24, 2024 at 8:49 AM Jay via RE-wrenches <re-wrenches@lists.re-wrenches.org> wrote:I agree with John. Most 12v fridges have small compressors. But I don’t know what they have. Personally a major reason to go 120/ac is to get a normal refrigerator. But you can measure the surge/load  and then size the charger accordingly. One feature of going charger is the lights are a lot brighter at night and last longer because they are not at 15v during the day. JayOn Apr 24, 2024, at 5:01 AM, John Blittersdorf via RE-wrenches <re-wrenches@lists.re-wrenches.org> wrote:Jason,  I have a customer with the same situation except he already has a 12 V VFX inverter,  He has a sunfrost fridge and other small loads with a very fancy custom control boardoriginally set up to handle AC and DC systems.  We are adding a lot more solar and I was considering a dual battery system but the owner didn't like that idea.  We are going with and Iota 12v power supply (i use one at my house for my sunfrost) to power up all his DC loads and will be adding a large 48 V battery bank and over 4Kw of solar using a VFXR3648 directly in place of the 12V inverter.  He complained that the existing inverter would not handle all his current AC loads very well.  My own house is fully wired for 12VDC as well as AC (lots of #10 copper not being used) and I have been considering getting a small LFP 12V battery to put back on by DC System. Then use the Iota as a secondary charging method with some of my large stash of older modules hooked up for 12V direct with C40 charge controller to recreate my original system just for kicks. I'm only using DC for my Sunfrost and one "emergency light" in the livingroom right now.  For your customer, a small LFP 12v battery (approximately $500 or less) to replace his old battery bankm and more larger ones for the new AC side with 48V inverter fed by his generator or through an Iota 48 V charger ifusing a smaller non charging inverter. Unlike Dave, I like these challenges. Maybe thats why I never seem to make money.!!John Blittersdorfoffgridvermont.comOn Wed, Apr 24, 2024 at 7:22 AM Jason Szumlanski via RE-wrenches <re-wrenches@lists.re-wrenches.org> wrote:Fortunately, the owner is pretty handy and is willing to live with any negative consequences. That said, I want to offer him something as simple and bulletproof as possible. I am walking into this with eyes wide open, for sure.Jason SzumlanskiPrincipal Solar Designer | Florida Solar Design GroupNABCEP Certified Solar Professional (PVIP)Florida State Certified Solar Contractor CVC56956Florida Certified Electrical Contractor EC13013208On Tue, Apr 23, 2024 at 5:47 PM Dave Angelini Offgrid Solar via RE-wrenches <re-wrenches@lists.re-wrenches.org> wrote:

Not being helpful but I  walk away from these.  It will come back to you. 
Dave Angelini Offgrid Solar
"we go where powerlines don't"
  https://offgridsolar1.com/ 
e-mail  offgridso...@sti.net
text 209 813 0060


On 2024-04-23 2:40 pm, Jason Szumlanski via RE-wrenches wrote:


I have an off-grid client who is working on replacing old equipment at a cabin. He has a lot of 12 volt distribution in the house for lighting, fans, and a 12 volt refrigerator. He also has 120 volt AC loads that run through a separate distribution panel where the only source is a 2000 Watt Honda generator. There is no inverter present. The batteries are charged through a Trace C40.
 
He currently has a few ancient solar panels and a struggling Bank of AGM batteries. It's time for an upgrade. I can easily supply enough PV power for what he needs. He currently has a 9 kilowatt hour battery capacity that he was happy with when the batteries operated optimally. Nonetheless, I would probably future-proof him with a 10 to 15 kilowatt hour LiPo to double or triple his usable capacity.
 
For convenience, obviously it would be nice to have an inverter to eliminate or reduce the generator requirement. But he seems committed to keeping his 12 volt distribution because it would be costly to replace fixtures. I think he would consider replacing the 12 volt refrigerator if he has an inv

[webkit-changes] [WebKit/WebKit] 745a77: REGRESSION (274894@main): [ iOS Debug ] accessibil...

2024-04-26 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 745a77767bf2c116b74d62179fb68d431c9846c6
  
https://github.com/WebKit/WebKit/commit/745a77767bf2c116b74d62179fb68d431c9846c6
  Author: Jay Stfleur 
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (274894@main): [ iOS Debug ] 
accessibility/text-marker/text-marker-range-stale-node-crash.html is a constant 
crash
https://bugs.webkit.org/show_bug.cgi?id=270477
rdar://124030130

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278056@main



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[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

2024-04-26 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad milestoned 
https://github.com/llvm/llvm-project/pull/90204
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[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

2024-04-26 Thread Jay Foad via llvm-branch-commits


https://github.com/jayfoad created 
https://github.com/llvm/llvm-project/pull/90204

Iterator MI can advance in insertWait() but we need original instruction
to set temporal hint. Just move it before handling volatile.

>From b544217fb31ffafb9b072de53a28c71acc169cf8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mirko=20Brku=C5=A1anin?= 
Date: Mon, 4 Mar 2024 15:05:31 +0100
Subject: [PATCH] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815)

Iterator MI can advance in insertWait() but we need original instruction
to set temporal hint. Just move it before handling volatile.
---
 llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp  |  10 +-
 .../memory-legalizer-flat-nontemporal.ll  | 165 ++
 .../memory-legalizer-global-nontemporal.ll| 158 ++
 .../memory-legalizer-local-nontemporal.ll | 179 +++
 .../memory-legalizer-private-nontemporal.ll   | 203 ++
 5 files changed, 710 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp 
b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 84b9330ef9633e..50d8bfa8750818 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -2358,6 +2358,11 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
 
   bool Changed = false;
 
+  if (IsNonTemporal) {
+// Set non-temporal hint for all cache levels.
+Changed |= setTH(MI, AMDGPU::CPol::TH_NT);
+  }
+
   if (IsVolatile) {
 Changed |= setScope(MI, AMDGPU::CPol::SCOPE_SYS);
 
@@ -2370,11 +2375,6 @@ bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
   Position::AFTER);
   }
 
-  if (IsNonTemporal) {
-// Set non-temporal hint for all cache levels.
-Changed |= setTH(MI, AMDGPU::CPol::TH_NT);
-  }
-
   return Changed;
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll 
b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
index a59c0394bebe20..ca7486536cf556 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
@@ -582,5 +582,170 @@ entry:
   ret void
 }
 
+define amdgpu_kernel void @flat_nontemporal_volatile_load(
+; GFX7-LABEL: flat_nontemporal_volatile_load:
+; GFX7:   ; %bb.0: ; %entry
+; GFX7-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-NEXT:s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:v_mov_b32_e32 v0, s0
+; GFX7-NEXT:v_mov_b32_e32 v1, s1
+; GFX7-NEXT:flat_load_dword v2, v[0:1] glc
+; GFX7-NEXT:s_waitcnt vmcnt(0)
+; GFX7-NEXT:v_mov_b32_e32 v0, s2
+; GFX7-NEXT:v_mov_b32_e32 v1, s3
+; GFX7-NEXT:s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:flat_store_dword v[0:1], v2
+; GFX7-NEXT:s_endpgm
+;
+; GFX10-WGP-LABEL: flat_nontemporal_volatile_load:
+; GFX10-WGP:   ; %bb.0: ; %entry
+; GFX10-WGP-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-WGP-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-WGP-NEXT:v_mov_b32_e32 v0, s0
+; GFX10-WGP-NEXT:v_mov_b32_e32 v1, s1
+; GFX10-WGP-NEXT:flat_load_dword v2, v[0:1] glc dlc
+; GFX10-WGP-NEXT:s_waitcnt vmcnt(0)
+; GFX10-WGP-NEXT:v_mov_b32_e32 v0, s2
+; GFX10-WGP-NEXT:v_mov_b32_e32 v1, s3
+; GFX10-WGP-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-WGP-NEXT:flat_store_dword v[0:1], v2
+; GFX10-WGP-NEXT:s_endpgm
+;
+; GFX10-CU-LABEL: flat_nontemporal_volatile_load:
+; GFX10-CU:   ; %bb.0: ; %entry
+; GFX10-CU-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-CU-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-CU-NEXT:v_mov_b32_e32 v0, s0
+; GFX10-CU-NEXT:v_mov_b32_e32 v1, s1
+; GFX10-CU-NEXT:flat_load_dword v2, v[0:1] glc dlc
+; GFX10-CU-NEXT:s_waitcnt vmcnt(0)
+; GFX10-CU-NEXT:v_mov_b32_e32 v0, s2
+; GFX10-CU-NEXT:v_mov_b32_e32 v1, s3
+; GFX10-CU-NEXT:s_waitcnt lgkmcnt(0)
+; GFX10-CU-NEXT:flat_store_dword v[0:1], v2
+; GFX10-CU-NEXT:s_endpgm
+;
+; SKIP-CACHE-INV-LABEL: flat_nontemporal_volatile_load:
+; SKIP-CACHE-INV:   ; %bb.0: ; %entry
+; SKIP-CACHE-INV-NEXT:s_load_dwordx4 s[0:3], s[0:1], 0x0
+; SKIP-CACHE-INV-NEXT:s_waitcnt lgkmcnt(0)
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v0, s0
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v1, s1
+; SKIP-CACHE-INV-NEXT:flat_load_dword v2, v[0:1] glc
+; SKIP-CACHE-INV-NEXT:s_waitcnt vmcnt(0)
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v0, s2
+; SKIP-CACHE-INV-NEXT:v_mov_b32_e32 v1, s3
+; SKIP-CACHE-INV-NEXT:s_waitcnt lgkmcnt(0)
+; SKIP-CACHE-INV-NEXT:flat_store_dword v[0:1], v2
+; SKIP-CACHE-INV-NEXT:s_endpgm
+;
+; GFX90A-NOTTGSPLIT-LABEL: flat_nontemporal_volatile_load:
+; GFX90A-NOTTGSPLIT:   ; %bb.0: ; %entry
+; GFX90A-NOTTGSPLIT-NEXT:s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX90A-NOTTGSPLIT-NEXT:s_waitcnt lgkmcnt(0)
+; GFX90A-NOTTGSPLIT-NEXT:v_mov_b32_e32 v0, s0
+; GFX90A-NOTTGSPLIT-NEXT:v_mov_b32_e32 v1, s1
+; GFX90A-NOTTGSPLIT-NEXT:flat_load_dword v2, v[0:1] glc
+;

[webkit-changes] [WebKit/WebKit] 2f1dda: REGRESSION (275949@main): 18 imported WPT /i18n/.....

2024-04-25 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 2f1dda6fe41317ba964446411714684d5a13349d
  
https://github.com/WebKit/WebKit/commit/2f1dda6fe41317ba964446411714684d5a13349d
  Author: Jay Stfleur 
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
M LayoutTests/platform/ios/TestExpectations

  Log Message:
  ---
  REGRESSION (275949@main): 18 imported WPT /i18n/.../css-text-line-break* 
tests are consistent/flaky failures.
https://bugs.webkit.org/show_bug.cgi?id=270860
rdar://124463423

Unreviewed test gardening.

Removing test expectations.

* LayoutTests/platform/ios/TestExpectations:

Canonical link: https://commits.webkit.org/278008@main



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[webkit-changes] [WebKit/WebKit] d9c845: REGRESSION (274945@main): [ MacOS ] Multiple editi...

2024-04-25 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: d9c8459c947133f324cea71206199439558504ad
  
https://github.com/WebKit/WebKit/commit/d9c8459c947133f324cea71206199439558504ad
  Author: Jay Stfleur 
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
M LayoutTests/platform/mac/TestExpectations

  Log Message:
  ---
  REGRESSION (274945@main): [ MacOS ] Multiple editing/selection tests are 
constant failures
https://bugs.webkit.org/show_bug.cgi?id=269955
rdar://123478486

Unreviewed test gardening.

Removing test expectations.

* LayoutTests/platform/mac/TestExpectations:

Canonical link: https://commits.webkit.org/278007@main



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[webkit-changes] [WebKit/WebKit] 4762be: REGRESSION (274945@main): [ Ventura ] tables/mozil...

2024-04-25 Thread Jay Saintfleur

  Branch: refs/heads/main
  Home:   https://github.com/WebKit/WebKit
  Commit: 4762be135e427e93db1f2ba99ac84b597884b88b
  
https://github.com/WebKit/WebKit/commit/4762be135e427e93db1f2ba99ac84b597884b88b
  Author: Jay Stfleur 
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
M LayoutTests/platform/mac/TestExpectations

  Log Message:
  ---
  REGRESSION (274945@main): [ Ventura ] tables/mozilla/bugs/bug4527.html is a 
constant failure
https://bugs.webkit.org/show_bug.cgi?id=270303
rdar://123843785

Unreviewed test gardening.

Removing test expectation.

* LayoutTests/platform/mac/TestExpectations:

Canonical link: https://commits.webkit.org/278003@main



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