Re: [ARTIQ] Proposition for a units system

On 08/14/2014 09:16 AM, Robert Jordens wrote: Also that excerpt misses the point of the underlying question, which is when to best convert floating point physical quantities to integer device units. What about having soft floating point (and rational with e.g. 64-bit numerator and denominator)

Re: [ARTIQ] first experiments

On 08/20/2014 04:42 AM, Robert Jordens wrote: By the way, will we ever need multi-dimensional array support on the core device? I don't see a need for that. In case it ever comes up, I would just emulate it explicitly. Ok. And should we support anything else than 32-bit integers for the

Re: [ARTIQ] first experiments

On 08/20/2014 11:35 PM, Slichter, Daniel H. wrote: the core device will support these data types, as well as arrays of these data types: - booleans - chars - short ints (16 bit) - long ints (32 bit) - long long ints (64 bit) - doubles - rational numbers Is this correct? We can do

Re: [ARTIQ] August 2014 progress report

Hi, On 08/26/2014 07:31 AM, Britton, Joe wrote: * What is the resolution for the time stamps? That depends on the PHY (the logic part of the core makes abstraction of it). I'm aiming for 1ns on the KC705. * How many bits are used to represent the time stamp for each event? It's configurable

Re: [ARTIQ] August 2014 progress report

On 08/27/2014 12:44 AM, Britton, Joe wrote: With the Penning trap we are work with many more ions than the other labs. Often N=300 or more ions. In this case we collect many more photons to beat the projection noise limit (std_proj = 1/sqrt(N)). Often, N*10 so 30,000 events. In how much time,

Re: [ARTIQ] DDR3 status on KC705

On 09/05/2014 01:39 PM, Robert Jordens wrote: Works fine here. The windows look good with vivado as well as ise. Great! Temperature and/or vivado-ise differences change it by at most one bit time. I guess you meant a IODELAY tap? Sébastien ___

Re: [ARTIQ] first experiments

On 09/10/2014 01:17 AM, Slichter, Daniel H. wrote: What is the notion behind removing the explicitly stated parallel and sequential blocks? In this particular case, after the replacement of pulse() with on() to avoid zero-length turn-off times, those blocks are not needed anymore. Generally,

Re: [ARTIQ] DDS/TTL breakout boards

On 09/19/2014 10:55 PM, Slichter, Daniel H. wrote: This will mean running the I/O single-ended from FPGA onto the daughterboard and then translating to LVDS, as is done with the current system. Why not drive the LVDS signals directly from the FPGA? If doing that I suggest adding some

Re: [ARTIQ] DDS/TTL breakout boards

On 09/20/2014 06:38 AM, Robert Jordens wrote: A jitter of one parallel UI is unlikely. For transmission, yes. For reception, the SERDES needs to align the received data words with the parallel clock, which can cause a latency variation in that vicinity depending on the parallel clock/serial word

Re: [ARTIQ] Proposition for a units system

On 10/14/2014 05:47 AM, Robert Jordens wrote: The obvious performance optimization here is to have the constant folding transform work across statements. The llvm optimizer passes should be able to do that, right? As far as I can tell right now, not so much. In particular it does not work

[ARTIQ] PDQ2 driver - API refinements and questions

Hi, I have started implementing the PDQ2 driver and made some changes to the transport example. Please have a look. I have some points I'd like to clarify: * since we are accessing the segments/frames via the frame objects (self.transport.begin(), self.transport.xxx.advance(), ...), then those

Re: [ARTIQ] Sustained RTIO output switching speed

On 10/16/2014 11:12 PM, Slichter, Daniel H. wrote: For inputs, what is the deepest FIFO one could make given the resources on the Kintex7? Could one do a 65k FIFO? Yes, with 64-bit timestamps (a pessimistic estimate) that would make a ~4Mbit memory. The FPGA on KC705 has ~16Mbit of block RAM

Re: [ARTIQ] master architecture and Windows support

On 10/17/2014 01:44 AM, Joe Britton wrote: For IPC on a single machine I've successfully used a shared memory map mmap between two well-behaved processes. This is fast, simple but doesn't scale well. https://docs.python.org/3/library/mmap.html How do you tell the receiving process that a new

Re: [ARTIQ] Mojo board compatibility

Hi, As far as I know, there are no plans to stop the Papilio Pro production, but Jack can probably tell us about this. Porting ARTIQ to the Mojo board would mainly involve: 1. creating a new platform file in Mibuild with the pin assignments

[ARTIQ] TAACCS slides

I've put online a PDF version of Robert's slides: http://m-labs.hk/artiq/slides_taaccs.pdf Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] TTL/DDS breakout meeting report

On 10/30/2014 03:29 AM, Slichter, Daniel H. wrote: 1. If a DDS frequency needs to be changed, how long would it take to load the required data for reprogramming into the output queue of the RTIO core? Let’s assume we need to change freq, phase, and amplitude – thus 64 bits sent over

Re: [ARTIQ] Phase Control

On 11/03/2014 10:31 AM, Gaebler, John wrote: For the dds phase control I think there are three behaviors that we might want to easily be able to implement and switch between when describing experiments. What is the purpose of setting the DDS to sine output in absolute and track mode, and to

Re: [ARTIQ] November 2014 status report

Hello, On 11/25/2014 11:58 AM, Robert Jördens wrote: * JSON/PYON: As mentioned on IRC, you could still have used JSON with a bit of type annotation. The other arguments against JSON appear to only count if you want to build a fully bijective python data (de)serializer wich may not be needed.

[ARTIQ] controller management

Hi, I'd like to take to the mailing list a discussion that started in Github comments a while ago: https://github.com/m-labs/artiq/commit/57e25c7af1cd6a2839d491a772447bb8a2359a55#commitcomment-8728507 I propose to keep each controller simple and have one controller process connected to a single

Re: [ARTIQ] controller management

Hi, On 12/13/2014 01:36 PM, Robert Jördens wrote: Will the manager never restart or crash? The manager shouldn't have to be restarted unless its code is modified. Crashes may still happen, but it is a relatively simple and contained piece of software, so they should be rare. How does the

[ARTIQ] Fwd: Re: controller management

Forwarded Message Subject: Re: [ARTIQ] controller management Date: Fri, 19 Dec 2014 15:11:08 -0700 From: Robert Jördens jord...@gmail.com To: Sébastien Bourdeauducq s...@m-labs.hk Hello, On Sat, Dec 13, 2014 at 2:33 AM, Sébastien Bourdeauducq s...@m-labs.hk wrote

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

Hi, Happy new year to all! On 01/01/2015 01:21 AM, Slichter, Daniel H. wrote: For the RTIO clocking, I'm currently planning to put a 2.5V LVDS clock on the USER_CLK_P/USER_CLK_N SMA connectors directly on the KC705 board (goes to an MRCC pair in I/O Bank 15, pins L25 and K25). I'm not very

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

On 01/03/2015 06:47 AM, Slichter, Daniel H. wrote: I'm not very confident about this technique (and high speed LVDS signals on two separate SMA connectors in general). The differential impedance will not match the LVDS requirements on long sections of the transmission line. Another option

Re: [ARTIQ] GUI: controls

On 02/06/2015 03:36 PM, Robert Jördens wrote: Hmm. I fear that with this design the prevalent use case of a) taking an arbitrary experiment b) choosing an arbitrary parameter from the parameter db c) scanning the experiment over that parameter is more complicated than it should be. AFAICT

Re: [ARTIQ] PXI6733 controller

On 01/22/2015 02:08 AM, Joe Britton wrote: * The waveform advance pulse to the 6733 is what causes its output to transition from one ADC channel (voltage) to another. We usually generate this pulse from the FPGA not from a periodic clock (eg crystal oscillator). This makes it possible to a)

Re: [ARTIQ] driver integration

On 01/27/2015 10:03 AM, Joe Britton wrote: class LED(AutoDB): class DBKeys: led = Device() penning_rotating_wall = Device() penning_rotating_wall.set_freq_all_phase_continuous(0.05) DBKeys is only a description of what object attributes needs to be linked to the

Re: [ARTIQ] PXI6733 controller

On 01/27/2015 03:48 AM, Yann Sionneau wrote: Actually I was thinking about using the PyDAQmx project ( http://pythonhosted.org/PyDAQmx/ ) and provide a direct access to the PyDAQmx API through the ARTIQ RPC mechanism. The PyDAQmx API being itself a direct wrapping/binding of the NI DAQ mx

Re: [ARTIQ] logging in controllers

On 01/28/2015 09:56 PM, Yann Sionneau wrote: +from artiq.frontend.loglevel import verbosity_args, init_logger Looks good to me, but I'd rather put those two small functions in artiq.tools instead of creating another file. Sébastien ___ ARTIQ mailing

Re: [ARTIQ] artiq dependencies

On 01/29/2015 04:25 AM, Slichter, Daniel H. wrote: I think it would make sense to fork external dependencies into m-labs/artiq so that dependencies don't break over time. I second the motion. What about pointing out to known good version numbers of dependencies in the ARTIQ documentation?

Re: [ARTIQ] GUI: controls

Hi, Are you able to run the GUI - do you see the parameters, scheduler and explorer windows? You need to run artiq_master (in the examples directory, so that it finds pdb.pyon, ddb.pyon and explist.pyon) and then artiq_gui. I made several changes since Jan 20, so you may want to upgrade from

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

On 01/06/2015 03:26 PM, Sébastien Bourdeauducq wrote: Or sample SYNC_CLK with a discrete flip-flop or latch near each DDS chip and trigger them with a skew-matched on-board clocking network pulsed by the FPGA through a scanned ODELAY. Then low-performance multiplexers, shared buses and skew

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

Hi, On 01/06/2015 04:43 AM, Slichter, Daniel H. wrote: Is there an on-die 100-ohm differential termination for LVDS signals at VCCO = 2.5V? Yes. Either way, it's actually a physically shorter distance from the SMA connector to the FPGA (~5 cm) than from the FMC connector to the FPGA, so

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

On 01/09/2015 01:12 AM, Slichter, Daniel H. wrote: You mean to use essentially as a thresholding phase detector? In other words, directly measuring the phase of the output signal instead of the phase of the SYNC_CLK? Yes. We could potentially implement this, but I would do it in addition

Re: [ARTIQ] technical details for clocking and syncing with FMC/DDS system

On 01/07/2015 02:02 AM, Slichter, Daniel H. wrote: All SYNC_CLKs need to be matched (ideally to less than a SYSCLK cycle) so that the FPGA can properly detect when they are aligned, and a shared bus will not achieve that. This is not necessarily required, I had thought. What we need is to

Re: [ARTIQ] artiq complicated experiments

Hi, On 02/10/2015 07:04 AM, Gaebler, John wrote: I would like to describe a compound device from a combination of dds and rtioout devices that would do everything needed to set the frequency for a gate pulse and also switch on and off. The dds device is too simple since sometimes multiple

Re: [ARTIQ] controller management

Hello, On 01/03/2015 10:51 AM, Robert Jördens wrote: I would just point the managers to the master where they can get their (current, versioned) subset of the devicedb. They can cache that if really needed. Then the master depends on the controllers to be able to run experiments, and the

Re: [ARTIQ] KC705 support

Hi, Seems to work here, thanks for fixing! I found two other bugs while testing: * Vivado fails to generate the .bin raw binary bitstream file: https://github.com/m-labs/migen/issues/9 This breaks loading the bitstream into flash wish xc3sprog. Building with ISE works around the problem. *

Re: [ARTIQ] external triggering; optical dipole force beatnote

On 03/31/2015 07:13 AM, Joe Britton wrote: If the latency were deterministic and less than 1 us the scenarios I described would work fine When you receive a trigger, the RTIO core timestamps it and the CPU uses that timestamp as now value. Then you delay() it by a sufficient amount to account

Re: [ARTIQ] KC705 support

Hi, Thanks Florent, I didn't find the Vivado command to generate raw binaries in the manual. Direct load with xc3sprog still does not work, but the bitgen options solve another problem: booting the FPGA from flash was also broken. Sébastien On 03/29/2015 06:21 PM, Florent Kermarrec wrote:

Re: [ARTIQ] Pipistrello build process

On 04/21/2015 05:46 AM, Zach Smith wrote: I'll poke though the stack trace to see if I can find a problem somewhere in the morning, but in case this is a familiar error to anyone I thought I'd reach out. Did you build the runtime yourself? If you used a runtime binary in conjunction with ARTIQ

[ARTIQ] result management

On 04/21/2015 02:12 AM, Tan, Ting Rei wrote: On a similar note, is there any documentation on the workflow/communication between the GUI and the master? There are several things I'm curious about: 1. When the master receive data from the core devices, how does the data get to the GUI

Re: [ARTIQ] ARTIQ future details

Hi Joe, On 03/12/2015 01:43 AM, Joe Britton wrote: Goals by beginning of May === Aim is to run penning trap experiment on ARTIQ 1) run ARTIQ on KC705 with legacy TTL/DDS system (16 TTL, 8 DDS) Ethernet is working fine on the KC705 now - I have fixed the low throughput bug.

Re: [ARTIQ] Logger UI

On 04/14/2015 11:29 PM, Tan, Ting Rei wrote: List the logged values with time stamps. What kind of logged values? I thought the log was like a console where you output debug strings. Did you mean results? Sébastien ___ ARTIQ mailing list

Re: [ARTIQ] fire-and-forget RPC / inter-CPU communication

On 06/12/2015 11:17 PM, Robert Jördens wrote: it may make sense to make choices that optimize the inter-CPU communication speed in the SoC. (Florent and I are debating whether we should have a shared L2 cache for both CPUs, which would e.g. make the transfer of small messages between the

[ARTIQ] remote imports

On 06/03/2015 02:59 AM, Robert Jördens wrote: And as I have pointed out before, proper remote imports with asyncio are difficult (though not impossible) as they require modifying the AST of remotely imported modules to turn their own import statements into something asyncio-friendly. I

Re: [ARTIQ] KC705 DDS/TTL card status

Hi, On 08/12/2015 10:00 AM, Benjamin K. Stuhl wrote: I'm writing to inquire about the status of the DDS/TTL (really just the TTL) breakout cards that were described on this list back in Jan/Feb [1]: have the designs been finished? Have any been built, or tested? The hardware we ended up

[ARTIQ] AD9914 support status and questions

Hi, I've been doing some hardware tests on the QC2 AD9914 DDS system. Many things are working (tested using the runtime test mode): * basic read/write of the registers, reset values match the datasheet * 10 cycles of ddstest * selection of different slots on the backplane * reset - a modified

Re: [ARTIQ] some comments about artiq_gui

On 08/23/2015 12:48 AM, Tan, Ting Rei wrote: 2. Master Menu bar so user containing a list of the tabs, e.g. DDS, explorer, log…. - This is so that user can open these tabs from these menu bar after closing them. Currently there is no way for the user to do this. The fact that

Re: [ARTIQ] Building Artiq from source

Hi, On 08/04/2015 05:05 PM, Chris Ballance wrote: When I try to make the runtime I get unknown argument errors: $ cd ~/artiq-dev/artiq/soc/runtime make runtime.fbi CC isr.o clang: error: unknown argument: '-mhard-mul' clang: error: unknown argument: '-mhard-div' Those two arguments

[ARTIQ] TTL direction on I2C IO expander

On 08/14/2015 12:22 AM, Slichter, Daniel H. wrote: But then we won't be able to use the TTLs properly until I2C is implemented. What kind of time scale would you see for having the I2C running correctly? We can give you a demo board for the I2C chip (TCA6424A) to help with the I2C debugging,

[ARTIQ] automated cancellations

On 10/25/2015 02:48 AM, Robert Jördens wrote: > "dequeue all instances" would do it. Then you can fire two shortcuts. Ok. I guess that would be "request graceful termination of all instances". Are there other "automated cancellation" features that would be nice to have? As you point out,

Re: [ARTIQ] ARTIQ hotkeys

On 10/24/2015 01:17 AM, Tan, Ting Rei wrote: > 2. Can be programmed as a 'panic button'. Where this experiment will > stop whatever that is running and put the system back to a 'safe' > state. How exactly should that work? Request graceful termination of all experiments in a pipeline associated

Re: [ARTIQ] ARTIQ shortcuts

Hi, On 10/24/2015 01:16 AM, Robert Jördens wrote: > On Fri, Oct 23, 2015 at 6:56 PM, Sébastien Bourdeauducq <s...@m-labs.hk> > wrote: >> What exactly should the hotkeys do in ARTIQ, and what are their use cases? >> >> As I understand, the idea is to

Re: [ARTIQ] ARTIQ hotkeys

On 10/24/2015 05:38 AM, Britton, Joe wrote: > * Submit Experiment :: Submit to scheduler new instance of whatever program > is selected in Explorer. > * use case is obvious > * Say, CTRL-S Done. > * Re-submit Experiment :: P is whichever program has focus in > Explorer. Request graceful

Re: [ARTIQ] ARTIQ hotkeys

On 10/24/2015 01:30 AM, Robert Jördens wrote: > Ting Rei could bind a single high-prio panic-experiment and have that > experiment clear the queue in whichever way it wants and do whatever > cleanup it desires. The scheduler now exposes the relevant APIs:

Re: [ARTIQ] ARTIQ API Changes :: python3.5, datasets, setattr_*

On 10/16/2015 12:05 PM, Joe Britton wrote: > Due to changes in conda deployment use the main build channel instead of > the dev channel. Actually you should have both right now. The main channel is for stable/released software that is manually built, while the dev channel is for automatically

Re: [ARTIQ] API change: merger of results and parameters into "datasets"

On 10/21/2015 03:35 AM, Joe Britton wrote: > $ artiq_client does not have an option for specifying persistence flag It does: $ artiq_client.py set-dataset -h [...] -p, --persist make the dataset persistent ___ ARTIQ mailing list

Re: [ARTIQ] logging and log levels within an experiemtn

On 10/21/2015 03:05 AM, Joe Britton wrote: > As it stands I gather that it's all logged but only the subset that > matches the Minimum level choice in the Log GUI is displayed. This > is good but insufficient for monitoring log messages of importance to > a particular debugging session.

Re: [ARTIQ] AD9914 support status and questions

Hi Raghu, thanks for your helpful information. The DDS is working now :) Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] ClockGen TTL

On 08/27/2015 09:18 AM, Neal Pisenti wrote: What is the purpose of splitting out the `build` function (instead of setting acc_width, etc. in the `__init__` method) It's an oversight. A previous device management mechanism used build() and I missed that one when refactoring. Thanks for

Re: [ARTIQ] ARTIQ shortcuts

On 11/26/2015 11:34 AM, Robert Jördens wrote: > In many cases one just fires a calibration > or verification experiment without wanting a window to pop up then > having to close it again. What about using the shortcuts (which can have buttons in addition to the F-key mappings) instead of the

Re: [ARTIQ] GUI issues when running artiq_gui remotely via an ssh session

Hi, On Tuesday, June 07, 2016 03:34 PM, Hankin, Aaron M. (Assoc) wrote: The main attraction of the X11-forwarding-over-ssh approach is that it feels more responsive, which helps when working remotely from home rather than the office. What about running the ARTIQ GUI locally and passing the

Re: [ARTIQ] GUI issues when running artiq_gui remotely via an ssh session

Hi, Have you tried VNC? X is a flawed protocol that rarely works. Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] GUI working with conda packages

Hi, we have fixed all major problems with conda and Qt5. If you want to try out the new GUI, it should work with a regular ARTIQ installation as per the manual. Let me know of any problems. Sebastien ___ ARTIQ mailing list

[ARTIQ] turning experiment docks into MDI windows

Hi Ting Rei, what would you think about making the ARTIQ GUI look like this, with the experiment argument editors replacing the *.ui files: http://web.univ-pau.fr/~puiseux/enseignement/python/tutoQt-zero/images/10/fenetre-03.png The main differences with the pyqtgraph-based UI are: -

Re: [ARTIQ] turning experiment docks into MDI windows

On Monday, February 15, 2016 11:09 PM, Slichter, Daniel H. wrote: My main question: how long would it take to change the GUI implementation over to this proposed model? Not long I believe, the code in ARTIQ is rather modular and so far my experience with those parts of Qt has been relatively

[ARTIQ] ARTIQ-1.0 feature freeze

Hi, I think we are close to a point where we should make a stable branch of ARTIQ. The idea is to get a series of stable versions that contain a good set of features that at lab could use on a regular basis for a substantial period (>= 6 months), and that we would maintain (fix bugs) without

Re: [ARTIQ] ARTIQ-1.0 feature freeze

On Thursday, February 18, 2016 10:42 AM, Robert Jördens wrote: I am working on the PDQ2 related items. Yes, the PDQ2 is for 1.0 (and tagged accordingly in the issue tracker); AFAIK most labs need the PDQ? ___ ARTIQ mailing list

[ARTIQ] TTLInOut directions

Hi, On Friday, February 19, 2016 01:45 AM, Slichter, Daniel H. wrote: I haven't been able to test the clock generator (to look for phase slippage) because I can't get a signal from either the ClockGen pin AFAICT you are using the ClockGen correctly. Have you double-checked the gateware

[ARTIQ] ARTIQ hardware proposal

Hi, I've been collecting ideas about the new hardware we've been talking about for a while. Please see the attached document and let me know what you think. Sébastien artiq_hardware.pdf Description: Adobe PDF document ___ ARTIQ mailing list

Re: [ARTIQ] ARTIQ hardware proposal

On Friday, 18 March 2016 4:27:53 PM HKT Ben Keitch wrote: > This gives me a 404: > > http://ssl.serverraum.org/lists-archive/artiq/attachments/20160318/ce9d656c/ > attachment.pdf This links works fine here. Anyway, here is the slightly updated version. Change log:

Re: [ARTIQ] installing ARTIQ

Hi, On Tuesday, 15 March 2016 6:32:19 PM HKT Jonathan Mizrahi wrote: > I am trying to get ARTIQ installed on a Windows system using the KC705 > board, following the instructions > here. This has proven > difficult and frustrating (and not yet

Re: [ARTIQ] installing ARTIQ

On Wednesday, 16 March 2016 3:55:53 AM HKT Jonathan Mizrahi wrote: > Ah, adding the dev channel allowed me to install it. The installation > instructions say that the dev channel is only necessary to use the > development version of ARTIQ, so I had not added it. Well, there aren't any

Re: [ARTIQ] FW: initial specification of the project

On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > Well, you don't have to write it. > It is already available for RTOS and linux. We are not using RTOS or Linux. > But it's true - it occupies MIO bank and dedicated DDR port. But this is axi > and can be easily accessible

Re: [ARTIQ] FW: initial specification of the project

On Friday, 8 April 2016 11:53:25 AM HKT Grzegorz Kasprowicz wrote: > Btw, > ZU11 FPGA costs more or less the same as 7K325 and offers almost twice more > logic resources. The price of ZU11 is $1,376.00 at 100pcs. > Since we will buy such quantity for our CBM project (Fair facility in GSI), > we

Re: [ARTIQ] FW: initial specification of the project

On Friday, 8 April 2016 12:37:02 PM HKT Grzegorz Kasprowicz wrote: > Modification of the backplane is quite difficult and expensive. If we have a minimalistic backplane with just power, maybe IPMI, 4x differential pairs between MCH and each AMCs, and clock - why is that particularly expensive?

Re: [ARTIQ] FW: initial specification of the project

On Saturday, 9 April 2016 6:10:36 PM HKT Grzegorz Kasprowicz wrote: > Why do you think that CPUs have negative value? You don't have to use them > at all. I already explained that the MPSoC has to be dealt with and cannot be completely ignored. If we have two SDRAM systems, maybe we can to a

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 12 April 2016 1:55:45 AM HKT Slichter, Daniel H. (Fed) wrote: > On the DSP/"Sayma" boards, a hard SoC could have use for reducing the time > it takes to perform feedback calculations (e.g. shifts of output signal > frequency based on ADC readings). Can't this be done on the Metlino

Re: [ARTIQ] FW: initial specification of the project

he only think I worry about is performance of the DACs. > ZynQ US+ can run IOserdes with almost 2Gbit/s performance - one can make > 1000base-x directly on IO pins using oversampling technique. > Greg > > -Original Message- > From: Sébastien Bourdeauducq [mailto:s...@m-labs.

[ARTIQ] Fwd: RE: FW: initial specification of the project

-- Forwarded Message -- Subject: RE: FW: initial specification of the project Date: Friday, 25 March 2016, 12:24:02 PM HKT From: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl> To: 'Robert Jördens' <r...@m-labs.hk>, 'Sébastien Bourdeauducq' <s...@m-labs.hk>

Re: [ARTIQ] FW: initial specification of the project

On Saturday, 26 March 2016 4:06:17 PM HKT Slichter, Daniel H. (Fed) wrote: > The cost savings from using FMC, which might amount to $50 per AMC, are not > worth if the crosstalk will make the cards not useful for researchers. It's not only about cost of the connector - the RF daughter cards

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and GBE > MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific features

Re: [ARTIQ] FW: initial specification of the project

On Friday, 1 April 2016 5:25:19 PM HKT Thomas Harty wrote: > d) Something else I'm missing? Low-frequency jitter of the PLL? ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] ARTIQ 1.0rc2

Hi, ARTIQ 1.0rc2 is out and contains fixes for most of the problems reported so far. There is one API change from 1.0rc1: set_dataset in broadcast mode no longer returns a Notifier. Mutating datasets should be done with mutate_dataset instead (https://github.com/m-labs/artiq/issues/345).

Re: [ARTIQ] Setting up Pipistrello with ARTIQ

On Tuesday, May 24, 2016 12:47 PM, Ken Brown wrote: I am having a problem with the socket connection. After I run pppd, I receive a modem hangup message and the connection is terminated. It seems to connect fine based on the rcvd and sent commands logged in verbose. Please post the exact

[ARTIQ] ARTIQ 1.0rc3

Hi, ARTIQ 1.0rc3 is now in the main conda channel and contains a number of bugfixes and a faster compiler. Please upgrade. The last hardware test necessary before 1.0 is the PDQ: https://github.com/m-labs/artiq/issues/178 Sébastien ___ ARTIQ

Re: [ARTIQ] sayma gateware updates

Hi, On Sunday, July 24, 2016 07:59 AM, j arl wrote: The bitfiles for the sayma_motherboard FPGA will be stored in flash. We've discussed several ways of updating the bitfiles. a) serial JTAG b) DRTIO over microTCA Port4 c) Ethernet microTCA Port0. Update method (a) is implemented by a directly

Re: [ARTIQ] sayma gateware updates

On Sunday, July 24, 2016 11:27 AM, Sébastien Bourdeauducq wrote: It is reasonable to use the same approach to (a) and (c) on metlino_motherboard? I suggest (a) and (b) on all boards. (c) involves gadgetry. And by "all boards" I also mean Kasli, which (c) would not support.

Re: [ARTIQ] sayma gateware updates

On Sunday, July 24, 2016 10:04 PM, Grzegorz Kasprowicz wrote: This can be also done using single FLASH and multi boot. Xilinx has such option but never tested it. I have used some of the multiboot features on Spartan-6, and it worked fine. Never tried on other FPGAs. Well, we already have

Re: [ARTIQ] sayma gateware updates

Hi, On Sunday, July 24, 2016 07:33 PM, Grzegorz Kasprowicz wrote: > When receiving a bitfile, a board (Metlino/Sayma) writes it to its > flash memory (via a SPI master core inside the FPGA) and then reboots > (using ICAP) to load the new bitfile. We used this approach some time ago in AFC/AFCK

Re: [ARTIQ] sayma gateware updates

On Tuesday, July 26, 2016 06:20 AM, j arl wrote: Kintex UltraScale SYSMONE1 interface supports digitization of 4 power supply voltages and up to 17 external analog signals. The resulting data can be readout by FPGA (DRP), exposed to MMC using I2C and readout using JTAG. My read of the docs

Re: [ARTIQ] Applets and Datasets

On Tuesday, August 02, 2016 11:55 PM, Stevens, Kelly E. M. wrote: Double click the content in the "Command" column and edit the line such that "Y_DATASET" is replaced with "parabola". Also, you can remove --x, --error, and --fit options for this example. The problem with this kind of detail

[ARTIQ] ARTIQ 1.2 released

Hi, ARTIQ 1.2 is out and packages are available in our main Anaconda channel. This is a pure bugfix release and we recommend that all 1.0 and 1.1 users upgrade to 1.2. Thanks to everyone who submitted detailed bug reports. Best, Sébastien for the ARTIQ team List of changes: * pipistrello:

Re: [ARTIQ] uTCA backplane driver choices

On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote: For synchronisation over fibre we can use existing White Rabbit core. The card requires only 2 VCXO oscillators and FPGA logic. The WR core consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy. We probably won't use

[ARTIQ] "connection reset" bug

Hi, is anyone other than Chris having this problem: https://github.com/m-labs/artiq/issues/456 If yes: can you post your precise network setup and would you consider shipping us hardware that would allow us to reproduce the problem? If no, I will reduce the priority of this issue. Sébastien

Re: [ARTIQ] 7-series White Rabbit GTX settings

ted as good enough. Are you aiming for better precision than the 1 ns specification, and is this why you are concerned about latency variations? Cheers, Peter On 7-7-2016 10:24, Sébastien Bourdeauducq wrote: Hi, Yes. But how do you ensure that the phase relation between the two domains is

Re: [ARTIQ] 7-series White Rabbit GTX settings

Hi, On Monday, July 11, 2016 05:27 PM, Peter Jansweijer wrote: Both sides of the the tx and rx fifos are clocked with the same frequency so there are no under- or overflows. Yes, I understand this. For high speed devices the region where you would hit a jump point is extremely small, you

Re: [ARTIQ] script rename?

On Tuesday, July 05, 2016 09:34 PM, Stevens, Kelly E. M. wrote: I noticed that artiq_gui.py is not in the trunk git repository (2.0dev). What is the new equivalent? artiq_dashboard. See the release notes for the complete list of changes that break compatibility with 1.x. Sébastien

[ARTIQ] June 2016 status report

Please see the attached PDF. 2016-June.pdf Description: Adobe PDF document ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] uTCA backplane driver choices

On Tuesday, June 28, 2016 04:00 PM, Grzegorz Kasprowicz wrote: For Sayma board to not waste precious GTX we will add PHY with 1000Base-X. We can also route it to SATA connector and provide dedicated SATA-SFP cables. Most of these PHYs apart from RGMII to 1000base-X offer 1000base-T, so we can

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