age-
> From: IBM Mainframe Assembler List On
> Behalf Of Peter Relson
> Sent: Thursday, November 16, 2023 10:08 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: [EXTERNAL] Re: ASMA057E Undefined operation code SR 15,15
>
> Everyone came up with the right alternat
of Peter Relson
Sent: Thursday, November 16, 2023 10:07 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: ASMA057E Undefined operation code SR 15,15
Everyone came up with the right alternatives.
Among XR, SLR, and SR,
XR is thought best (not necessarily measurable better).
If you don't need
Everyone came up with the right alternatives.
Among XR, SLR, and SR,
XR is thought best (not necessarily measurable better).
If you don't need a condition code (and certainly if you need to preserve a
condition code), LHI is thought best.
I'm not sure to what extent the fact that the first
very well explained.
thanks
Em qua., 15 de nov. de 2023 às 12:08, Jonathan Scott <
jonathan_sc...@vnet.ibm.com> escreveu:
> I doubt whether there is much difference between methods of
> zeroing a register now. I would assume that if you want the
> condition code preserved, LHI is best,
On 11/15/23 06:39:33, Peter Relson wrote:
This was a very lengthy thread in which the OP multiple times ignored those who
correctly provided what was needed. I don't know why the OP would not simply
take the advice and proceed.
.
I suspect the OP supplied a distilled test case which did not
af
Bill Hitefield
Sendt: 15. november 2023 16:27
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
Peter,
I got the impression the OP desired to have a single LCLC variable containing
both the opcode and the operands. When the examples with multiple LCLC
M
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: ASMA057E Undefined operation code SR 15,15
>
> This was a very lengthy thread in which the OP multiple times ignored
> those who correctly provided what was needed. I don't know why the OP
> would not simply take the advice and p
LER-LIST@LISTSERV.UGA.EDU
> Subject: Re: ASMA057E Undefined operation code SR 15,15
>
> This was a very lengthy thread in which the OP multiple times ignored those
> who correctly provided what was needed. I don't know why the OP would not
> simply take the advice and proceed.
>
I doubt whether there is much difference between methods of
zeroing a register now. I would assume that if you want the
condition code preserved, LHI is best, otherwise use XR, but SR
on modern hardware probably takes the same time as XR anyway.
I would expect current hardware to detect XR with
_
> From: IBM Mainframe Assembler List on
> behalf of João Reginato
> Sent: Wednesday, November 15, 2023 8:44 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: ASMA057E Undefined operation code SR 15,15
>
> so, changing the subject, tell us, what is the b
Sent: Wednesday, November 15, 2023 8:44 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: ASMA057E Undefined operation code SR 15,15
so, changing the subject, tell us, what is the best choice for zeroing a
register?
xr, la, or the 3rd one?
Em qua., 15 de nov. de 2023 às 10:39, Peter Relson
Probably LHI
Best Regards
Ituriel do Nascimento Neto
z/OS System Programmer
Em quarta-feira, 15 de novembro de 2023 às 10:45:00 BRT, João Reginato
escreveu:
so, changing the subject, tell us, what is the best choice for zeroing a
register?
xr, la, or the 3rd one?
Em qua., 15 de
so, changing the subject, tell us, what is the best choice for zeroing a
register?
xr, la, or the 3rd one?
Em qua., 15 de nov. de 2023 às 10:39, Peter Relson
escreveu:
> This was a very lengthy thread in which the OP multiple times ignored
> those who correctly provided what was needed. I don't
This was a very lengthy thread in which the OP multiple times ignored those who
correctly provided what was needed. I don't know why the OP would not simply
take the advice and proceed.
The error has nothing to do with "label", although the lack of allowing "label"
is not typically good. The
I`ve appreciated all the messages received.
It is now clear to me that it must use separated SETCs: label, opcode,
arguments and comments.
Thank you all for the help.
best regards
João
Em qua., 15 de nov. de 2023 às 06:42, Binyamin Dissen <
bdis...@dissensoftware.com> escreveu:
> On Wed, 15 Nov
On Wed, 15 Nov 2023 03:39:00 -0500 John Dravnieks wrote:
:>The conditional assembly language is very simplistic and one aspect is that
it does NOT rescan. So if you code a SETC variable in a model statement as
the opcode, then that is what it will expect in that variable - just the opcode.
See the reference manual topic "Model statements" and the
following subtopics for how it works:
https://www.ibm.com/docs/en/hla-and-tf/1.6?topic=definitions-model-statements
Any model statement will initially be interpreted like a a macro
call, with any name field, operation code, operand fields
sorry it is not the variable but the content of the variable which is invalid.
Without the dot on line 6 between (1) and (2) this version of Paul(i
think) works:
MACRO
ZERO
LCLC (2)
(1) SETC 'SR '
(2) SETC ' ,'
(1) (2)
MEND
XYZ CSECT
ABC ZERO 15
END
Le mercredi 15 novembre 2023 à
Hi,
The problem is due tu use a variable name in the opcode in the macro definition.
Rene
The conditional assembly language is very simplistic and one aspect is that it
does NOT rescan. So if you code a SETC variable in a model statement as the
opcode, then that is what it will expect in that variable - just the opcode.
If you have extra data in the SETC value - as in this case
: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
yes, it worked too, but I still can't understand why. Maybe a bug?
Em ter., 14 de nov. de 2023 às 18:31, Willy Jensen <
willy.h.jen...@outlook.com> escreveu:
> You still have one veriable set to 2 c
g meddelelse-
:>> Fra: IBM Mainframe Assembler List På
:>> vegne af João Reginato
:>> Sendt: 14. november 2023 22:16
:>> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
:>> Emne: Re: ASMA057E Undefined operation code SR 15,15
:>>
:>> without the SETC it wo
. november 2023 23:18
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
Looks like it is taking 'SR' as a label and '1,15' as an op ode.
Michael
At 02:28 PM 11/14/2023, João Reginato wrote:
hi
I can't see the error on this simple code.
Can anyone help me pls?
TIA
On Tue, 14 Nov 2023 18:27:16 -0300, João Reginato wrote:
>** ASMA057E Undefined operation code - 6/SR 15,15
The message shows you exactly what is the problem. There is no opcode "SR
15,15". The assembler thinks " 15,15" is part of the instruction. Assembler
tokenization and macro
r List Pý
¥
> vegne af João Reginato
> Sendt: 14. november 2023 22:27
> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Emne: Re: ASMA057E Undefined operation code SR 15,15
>
> sublisted the same:
>
> Loc Object CodeAddr1 Addr2 Stmt Source Statement
>
operation code SR 15,15
Looks like it is taking 'SR' as a label and '1,15' as an op ode.
Michael
At 02:28 PM 11/14/2023, João Reginato wrote:
>hi
>I can't see the error on this simple code.
>Can anyone help me pls?
>
>TIA
>João Reginato
>(+55 61) 9911-55500
>
> Ac
Looks like it is taking 'SR' as a label and '1,15' as an op ode.
Michael
At 02:28 PM 11/14/2023, João Reginato wrote:
hi
I can't see the error on this simple code.
Can anyone help me pls?
TIA
João Reginato
(+55 61) 9911-55500
Active Usings: None
Loc Object CodeAddr1 Addr2 Stmt
On 11/14/23 14:44:48, Willy Jensen wrote:
I have sometimes used global variables with a recursive call to simulate a
macro subroutine to validate and set variables.
.
I doubt that's the simplification the OP is seeking.
-Oprindelig meddelelse-
Fra: IBM Mainframe Assembler List João
: ASMA057E Undefined operation code SR 15,15
No, your code uses one setc containing the entire 2nd part 'reg,reg', where
mine uses one variable just for the reg and then the macro uses that var twice
, Can't remember seeing it documented, but that is how I
experience it.
-Oprindelig meddelelse
På vegne af
João Reginato
Sendt: 14. november 2023 22:37
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
yes, it worked too, but I still can't understand why. Maybe a bug?
Em ter., 14 de nov. de 2023 às 18:31, Willy Jensen <
willy.h.jen...@outlook.
lclc (2)
> (1)setc 'SR'
> (2)setc ''
> (1) (2),(2)
> Mend
>
> -Oprindelig meddelelse-
> Fra: IBM Mainframe Assembler List På
> vegne af João Reginato
> Sendt: 14. november 2023 22:27
> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
n Tue, Nov 14, 2023 at 3:20 PM Willy Jensen >
> > wrote:
> >
> > > Would a sublisted SETC do, where P(1) is the instruction and P(2) is
> the
> > > register?
> > >
> > > -Oprindelig meddelelse-
> > > Fra: IBM Mainframe Assembler L
Mainframe Assembler List På vegne af
João Reginato
Sendt: 14. november 2023 22:27
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
sublisted the same:
Loc Object CodeAddr1 Addr2 Stmt Source Statement
HLASM R6.0 2023/11/14 18.26
> Fra: IBM Mainframe Assembler List På
> > vegne af João Reginato
> > Sendt: 14. november 2023 22:16
> > Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> > Emne: Re: ASMA057E Undefined operation code SR 15,15
> >
> > without the SETC it works but I need it to simplify the l
On 11/14/23 14:16:22, João Reginato wrote:
without the SETC it works but I need it to simplify the logic of a bigger
macro.
.
Please post an example of "a bigger macro" with an explanation of how
the SEtC simplifies it. If it doesn't work, simpler is *not* better.
--
gil
gt; Would a sublisted SETC do, where P(1) is the instruction and P(2) is the
>> register?
>>
>> -Oprindelig meddelelse-
>> Fra: IBM Mainframe Assembler List På
>> vegne af João Reginato
>> Sendt: 14. november 2023 22:16
>> Til: ASSEMBLER-LIST@LISTSERV
g meddelelse-
> Fra: IBM Mainframe Assembler List På
> vegne af João Reginato
> Sendt: 14. november 2023 22:16
> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Emne: Re: ASMA057E Undefined operation code SR 15,15
>
> without the SETC it works but I need it to simplify the logi
22:16
> Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Emne: Re: ASMA057E Undefined operation code SR 15,15
>
> without the SETC it works but I need it to simplify the logic of a bigger
> macro.
> .
> João Reginato
> (61) 9911-55500
>
>
> Em ter., 14 de nov. de 2
Would a sublisted SETC do, where P(1) is the instruction and P(2) is the
register?
-Oprindelig meddelelse-
Fra: IBM Mainframe Assembler List På vegne af
João Reginato
Sendt: 14. november 2023 22:16
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR
the logic is very complicated and full of AIFs.
So, to simplify and not repeat the same AIFs, the SETC sets the later
instruction to be used at the end of the macro call.
João Reginato
(61) 9911-55500
Em ter., 14 de nov. de 2023 às 18:16, João Reginato
escreveu:
> without the SETC it works
without the SETC it works but I need it to simplify the logic of a bigger
macro.
.
João Reginato
(61) 9911-55500
Em ter., 14 de nov. de 2023 às 18:08, Paul Gilmartin <
0014e0e4a59b-dmarc-requ...@listserv.uga.edu> escreveu:
> On 11/14/23 13:58:30, João Reginato wrote:
> > Gil
> >
> > I know
How do you need that SETC? An explanation might help us suggest something.
-Oprindelig meddelelse-
Fra: IBM Mainframe Assembler List På vegne af
Paul Gilmartin
Sendt: 14. november 2023 22:07
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
On 11
On 11/14/23 13:58:30, João Reginato wrote:
Gil
I know it works in the way you've proposed but I need to use the SETC in a
very bigger macro.
.
Please post an example showing the failure without the SETC.
Would it be better to have two separate MACROs, one of which
calls the other?
Em ter.,
Willy
I need the SETC
João Reginato
(61) 9911-55500
Em ter., 14 de nov. de 2023 às 18:02, João Reginato
escreveu:
> Lloyd
> I've already sent a try with a label and the same error occurred
>
> João Reginato
> (61) 9911-55500
>
>
> Em ter., 14 de nov. de 2023 às 17:58, João Reginato
>
Lloyd
I've already sent a try with a label and the same error occurred
João Reginato
(61) 9911-55500
Em ter., 14 de nov. de 2023 às 17:58, João Reginato
escreveu:
> Gil
>
> I know it works in the way you've proposed but I need to use the SETC in a
> very bigger macro.
>
> João Reginato
> (61)
@LISTSERV.UGA.EDU
Emne: SV: ASMA057E Undefined operation code SR 15,15
I'm pretty sure that you cannot have a variable for the entire expression, you
need one for each part. So one for the instruction and another for the register.
As someone mentioned
SR ,
-Oprindelig meddelelse-
Fra: IBM Mainframe
Gil
I know it works in the way you've proposed but I need to use the SETC in a
very bigger macro.
João Reginato
(61) 9911-55500
Em ter., 14 de nov. de 2023 às 17:49, João Reginato
escreveu:
> now with LCLC and CSECT. Same error
>
> João Reginato
> (61) 9911-55500
>
> Symbol Type Id
. november 2023 21:49
Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Emne: Re: ASMA057E Undefined operation code SR 15,15
now with LCLC and CSECT. Same error
João Reginato
(61) 9911-55500
Symbol Type Id Address Length Owner Id Flags Alias-of
HLASM R6.0 2023/11/14 17.46
XYZ SD
Try adding some blanks in front of your ‘SR…’ of the SETC.
I think the SR is being read as the label and the ,7N as the oppose.
Lloyd
Sent from AT Yahoo Mail for iPad
On Tuesday, November 14, 2023, 3:49 PM, João Reginato
wrote:
now with LCLC and CSECT. Same error
João Reginato
(61)
now I've added a label. Still the same error
João Reginato
(61) 9911-55500
Symbol Type Id Address Length Owner Id Flags Alias-of
HLASM R6.0 2023/11/14 17.50
XYZ SD 0001 00
Page3
now with LCLC and CSECT. Same error
João Reginato
(61) 9911-55500
Symbol Type Id Address Length Owner Id Flags Alias-of
HLASM R6.0 2023/11/14 17.46
XYZ SD 0001 00
Page3
Active
On 11/14/23 13:28:09, João Reginato wrote:
hi
I can't see the error on this simple code.
Can anyone help me pls?
TIA
João Reginato
(+55 61) 9911-55500
Active Usings: None
Loc Object CodeAddr1 Addr2 Stmt Source Statement
HLASM R6.0 2023/11/14 16.58
I've always had a LCLC in my macros. Never tried it without.
*Mark*
On Tue, Nov 14, 2023 at 2:28 PM João Reginato wrote:
> hi
> I can't see the error on this simple code.
> Can anyone help me pls?
>
> TIA
> João Reginato
> (+55 61) 9911-55500
>
>
> Active Usings: None
>
> Loc Object
hi
I can't see the error on this simple code.
Can anyone help me pls?
TIA
João Reginato
(+55 61) 9911-55500
Active Usings: None
Loc Object CodeAddr1 Addr2 Stmt Source Statement
HLASM R6.0 2023/11/14 16.58
1 MACRO
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