UTC-4 Mitch Burnett wrote:
Hi John,
On Mar 12, 2024, at 10:00 AM, John Swoboda wrote:
Hi Mitch,
Thanks for the reply. The 100 Gbe is working fine on my end. I also was able to
get the into my design.
Great to hear!
In terms of using the -es1 in the design files, I would suggest
for 100G to work?
Mitch
Thanks,
John
On Monday, March 11, 2024 at 1:21:39 AM UTC-4 Mitch Burnett wrote:
Hi John,
Now I think the trick is you have to change the block parameters for the yellow
block supplying the PPS to be single ended because I ran that and it got rid of
my error since
Hi John,
Now I think the trick is you have to change the block parameters for the yellow
block supplying the PPS to be single ended because I ran that and it got rid of
my error since in the zcu208/216 use single LVCMOS18 instead of LVDS_25.
Am I on the right track here?
Yes, this is correct.
Hi Ken,
The process starts in `mlib_devel/jasper_library/casper_platform.py` where the
yaml file is desearlized into an object that is then carried through the flow.
The pin information in that object is then used in other places.
Mitch
On Jan 3, 2024, at 3:53 PM, Ken Semanov wrote:
Which
Hi Wei,
The issue might be that the PDI you are attempting to use with `fpga_manager`
is considered a “base” PDI that is part of the BOOT PDI image loaded by the PLM
during boot. Since this PDI contains the PLM/PPU information these cores cannot
be reconfigured at run time (as indicated by
Hi Sebastian,
It is not possible on RFSoC 4x2 to switch from Dual to Quad tile. The
architecture is fixed and inherent to the FPGA. So this would be true of all
RFSoC platforms. A very brief overview of this is in the RFSoC
way anyone else who has encountered these issues
may provide guidance, and anyone who might encounter these issues in the future
will be able to find the thread in the mailing list archive.
Morag
On Tue, 31 Oct 2023, 07:17 Mitch Burnett,
mailto:mitch.burn...@byu.edu>> wrote:
Hi Heystek,
One thi
ekgrob...@gmail.com>
On Mon, Oct 30, 2023 at 4:50 AM Mitch Burnett
mailto:mitch.burn...@byu.edu>> wrote:
Hi Heystek,
This issue is most likely caused in a discrepancy between the python
environment you setup for mlib_devel and one that matlab/simulink is using. Can
you verify
of the help!
Heystek
-
Heystek Grobler
0832721009
heystekgrob...@gmail.com
On 25 Oct 2023, at 20:39, Mitch Burnett wrote:
Sorry, I should be more helpful to specifically point out which of the issues
in this list on the CASPER wiki link
:
https://strath-sdr.github.io/tools/matlab/sysgen/vivado/linux/2021/01/28/sysgen-on-20-04.html
Mitch
On Oct 25, 2023, at 12:34 PM, Mitch Burnett wrote:
Hi Heystek,
The full set of instructions and how to overcome different issues based on the
version of Ubuntu is documented on the CASPER wiki
but I can not find the solution.
@Kaj did you perhaps manage to find a way for the toolchain to work? In the
email list you and Mitch Burnett talked about posting a recipe somewhere for
this.
Thank you for the help.
Heystek
-
Heystek G
Hi Emiliano,
Debugging errors due to the axi4lite memory map can be difficult. I suggest a
different approach before we dive too much into that.
Are you building a the platform (tutorial 1) from scratch? Or are you trying to
compile the already completed platform tutorial file
Hi Ken,
It is a standalone utility. It does not accept any files on the input. There is
only one configuration and is the one provided by the executable. The utility
needs to have root permissions to run. The syntax would then be, ‘sudo
/home/casper/bin/prg_8a34001’
Mitch
On Aug 2, 2023, at
PM UTC-4 Mitch Burnett wrote:
By default, the tool will targeting the first CMAC location in this case it is
the 4x25 SFP28 cage for the ZCU216.
The 100G port option is the one you would want to select.
Best,
Mitch
On Jul 24, 2023, at 3:40 PM, Ken Semanov wrote:
A simulink model appears
By default, the tool will targeting the first CMAC location in this case it is
the 4x25 SFP28 cage for the ZCU216.
The 100G port option is the one you would want to select.
Best,
Mitch
On Jul 24, 2023, at 3:40 PM, Ken Semanov wrote:
A simulink model appears below with the hosting github.
been demonstrated in
Simulink for individual connections using the SFP28 cages. It would be feasible
to believe the ZCU216 can do this too, but I am not sure who may be working on
this.
Mitch
> On Jun 26, 2023, at 10:37 AM, Mitch Burnett wrote:
>
> Hi Ken,
>
> Yes, CA
Hi Ken,
Yes, CASPER interfaces with these using the 100GbE core in Simulink. The
transceivers attached to the four lanes of the 4x25 SFP28 cage are aggregated
to implement a single CAUI-4 100G PHY using the integrated CMAC on UltraScale+.
Currently, there is not a way, that I am aware of, to
Ken,
I understand a bit better what you are after now. Some more information inline
below.
Best,
Mitch
On Jun 7, 2023, at 1:43 PM, Ken Semanov wrote:
Dear Mitchell Burnett,
Thank you for the help with this matter. The manufacturer of the optical
transceiver is likely confused as to the
t_getting_started.html#setup-casperfpga>
[favicon.ico]<https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_getting_started.html#setup-casperfpga>
Mitch
On Jun 6, 2023, at 3:15 PM, Ken Semanov wrote:
Dear Mitch Burnett,
Thank you for the prompt response.
Hi Ken,
There are not any good examples in the CASPER Tutorials yet for how to
configure this, however the capability is there.
In CASPER tools the signals out of the comparator/ADS7885S/etc. in that diagram
and into the FPGA fabric are accessed via a GPIO yellow block using the name
given to
Hi Jason,
Yes you can use a 10 MHz ext. ref. clk with LMK on RFSoC 4x2. Yes, the LMK will
need to explicitly load another configuration. There are methods in casperfpga
to upload new exported register files from TICS and to program the LMK (
upload_clk_file(), progpll() ).
Attached is a zip
Hi Mayukh,
This issue is caused by library dependency differences between what Ubuntu
base uses and what the Xilinx Model Composer and MATLAB Simulink are wanting to
use. Particularly the various libgmp libraries used.
To side step this issue requires altering your Model Composer installation
Hi Jonathon,
I probably will not be answering your question completely. But perhaps just a
bit of input for some further searching?
My understanding is that the first generation 100G PHY standard was IEEE
802.3ba-2010 and that used 10 lanes at 10G line rates. However, I believe the
only
giorno venerdì 7 ottobre 2022 alle 05:03:30 UTC+2 Mitch Burnett ha scritto:
Hello all,
I am reaching to follow up with many of you, but also for others who may be
interested to know that a more proper wideband spectrometer and 100 GbE
tutorials for RFSoC have been completed. There have been model
be found here:
https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_100g.html#
Best,
Mitch Burnett
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Hi Giovanni,
Thanks for reaching out and jumping into using the new toolchain.
I am a rather surprised (and a little concerned) you are getting this issue
with a fresh Ubuntu 18.04.4LTS installation as this should be a very supported
configuration. These errors however are expected using
I seem to be having the same issue. Any card I use at the payment website comes
back with error messages.
Mitch
On Jun 30, 2022, at 11:02 AM, Dan Werthimer
mailto:d...@ssl.berkeley.edu>> wrote:
i haven't been able to pay for casper workshop registration using any of my
credit cards.
the
Hi Wang,
When editing your `/etc/exports` file, did you include the text “# Share
‘roach_boot’” in the file for the line you included in your message?
# Share 'roach_boot' directory/srv/roach_boot
192.168.100.0/24(rw,subtree_check,no_root_squash,insecure)
If you did, try removing it so
Nitika
From: Mitch Burnett mailto:mitch.burn...@byu.edu>>
Sent: Wednesday, March 30, 2022 5:08 PM
To: johnp via casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu>
mailto:casper@lists.berkeley.edu>>
Subject: Re: [casper] redpitaya tcpborphserver3 issues
Hi Nitika,
Hi Nitika,
Are you determining from this message alone that it is not started?
Have you manually checked if `tcpborphserver3` is running with something like
`ps aux | grep tcpborphserver` When logged into the RP? Or you have verified
you cannot connect to the RP with a client like
/home/comore/casper3/casper_venv/bin/python: symbol lookup error:
/home/comore/casper3/casper_venv/bin/python: undefined symbol: XML_SetHashSalt
Il giorno martedì 4 gennaio 2022 alle 23:45:28 UTC+1 Mitch Burnett ha scritto:
Sorry, I’m referring to this branch from the capser-astro mlib
rfsocs/merge-casper-astro/m2019a
Which one are you referring? The first looks like using Matlab2019a + VIvado
2019.1. Is it correct?
The LFS file requires an authorization, which failed. Do I have to specify some
credentials in retrieving git archive?
Gianni
Il 04/01/22 19:26, Mitch Burnett ha
Hi Gianni,
Sorry you are having issues getting started. Thanks for taking the time to go
through the material and identify the problem areas where the documentation can
be updated/improved/clarified. New year, new goals :)
When I wrote the tutorial our BYU gitlab repository is where I was
Hi Duan,
You are correct that `xdevcfg` is officially deprecated. At the time when zynq
7-series was released there was some overlap of `xdevcfg` as the linux
`fpga_manager` kernel was being added. This is why the red pitaya image will
support katcp as is as well as older linux images (what
Hi Jack, Adam, Benjamin,
I hope you do not mind me chime in a bit on the block diagram/IPI/RTL
discussion a bit. As you point out Jack, handling IPI/block designs in the
toolflow was clunky. But, adding RFSoC to the toolflow to fully support the
platform for any board with the part and add the
Hi Colm,
Good to hear from you. All is well provided the circumstances, I hope the same
for you.
There has been some good progress in getting the RFDC yellow block working, but
it still isn’t finished. I have some models in the toolflow with different
preset RFDC configurations that are able
of the CASPER-ized Linux image with
explanation and examples for using casperfgpa or as part of a future getting
started/tutorial for the ZCU111.
I am happy to field any other questions you have regarding the ZCU111 and
discuss with you the specifics of this in more detail if you like.
Best,
Mitch
Awesome!
>From what I understand it should be very similar if not exactly the same. The
>only difference (that your probably aware of) is that you will need the IO
>constraints in the yaml (like the red pitaya) for that board. We didn’t have
>to add them for the ZCU because the master
Hey Luke,
I assume you are working on the ADC for the ZCU111, right? If so, the
mlib-devel repo has a branch with the AXI Lite interface to the MPSoC and Brian
Bradfords forked version of that repo has the beginning workings of adding the
interface to the RFDC yellow block that he and I were
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