like
> the LAPIC base. That capability to deal with larger flash is only present on
> fairly recent hardware and in that case coreboot often supports it.
>
> Kind regards.
>
> On Tue, Feb 20, 2024 at 4:42 PM Mike Banon wrote:
>>
>> Dear friends, thank you very mu
the registers
>> in the SPI controller that I'd expect to be present if it supports the 4
>> byte address mode.
>>
>> Regards,
>> Felix
>>
>> On 19/02/2024 19:55, Mike Banon wrote:
>> > Theoretically - yes, if someone finds & solders there
;
> On Mon, Feb 19, 2024 at 07:05 Mike Banon wrote:
>>
>> Small bump, I am still having this error while (out of curiosity)
>> trying to build the Lenovo G505S ROM for 32 MB or 64 MB spi flash:
>>
>> OBJCOPYbootblock.raw.bin
>> Created CBFS (capacity
to cbfstool to tell it how to
> map areas below the top 16MB.
>
> On Thu, Jun 23, 2022 at 1:09 AM Paul Menzel wrote:
> >
> > Dear Mike,
> >
> >
> > Am 23.06.22 um 09:49 schrieb Mike Banon:
> > > If I use a default config for i440f
y" to specify
the config symbol type.
P.S. wrote about this problem under the change about ~1 month ago, but
maybe the notifications are not working for the merged changes - so
posting it here just in case
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n our Matrix or tiny-volume event notification newsletter:
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Thank you, the patch at https://review.coreboot.org/c/coreboot/+/79298
really helps, I +1 it now
On Wed, Nov 29, 2023 at 8:39 PM Mike Banon wrote:
>
> At the moment none of the suggestions work (tried make oldconfig, make
> olddefconfig, make menuconfig KCONFIG
ss this
> over at
> https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/M543FU2OIHEMLAFAFAPCFHAD36ISAEKO/?
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onfig/Makefile.real:47: menuconfig] Error 1
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; Florentin
>
> - Mail original -
> De: "Mike Banon"
> À: "coreboot"
> Envoyé: Samedi 2 Septembre 2023 00:03:01
> Objet: [coreboot] Re: Restoring the opensource AGESA boards takes just 1% of
> git reverts since their removal
>
> Now coreboo
Patrick, thank you so much for such a quick & working fix, it is
really appreciated ;-)
On Sun, Nov 26, 2023 at 9:20 PM Patrick Georgi wrote:
>
> Am 26.11.2023 um 18:15 schrieb Mike Banon:
> > /usr/bin/ld: build/util/kconfig/lxdialog/yesno.o: warning: relocation
> > aga
at this
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Now coreboot 4.21 boots flawlessly on AMD Lenovo G505S ! That's how we
get coreboot 4.21 there ;-)
a new "restore_agesa.sh" script compatible with coreboot master -
https://review.coreboot.org/c/coreboot/+/76832
On Sat, Aug 5, 2023 at 12:23 AM Mike Banon wrote:
>
> Dear frie
generations and their
> FSP's appearing.
>
> Kyösti
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11ba8ebbcc662ebd1dc8e14372a020eb32f26561 (3741 PoH) for G505S test only
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controller while you still can "
[2] https://review.coreboot.org/c/coreboot/+/40488 -
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
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[0m[SPEW ] AmdInitEarly: End[0m
[0m
[0m[INFO ] Time
Exceeding maximum number of comments: 5139 (existing) + 2
(new) > 5000
This issue might be blocking the further work on this change (and I
don't see why there should be any limit at all)
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hats will
be available for your convenience
More details and Join links are available here -
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wrote:
>
> Thank you for reply.
>
> I found CH341A and SOIC8.
> But CH341A is not green. It is black edition.
> Doesn't it work?
>
> And build is not difficult?
>
> On Tue, March 14, 2023 10:14 am, Mike Banon wrote:
> > Usually, to flash a coreboot to a coreboot-sup
it?
>
> And what are skulls and heads, and what is the difference between them and
> coreboot?
>
>
>
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uld be connected one-by-one after the PSU installation), this
is much easier to manage.
Please share your experiences ;-)
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ted build.log file, can anyone suggest how to resolve
> this issue?
>
> Thanks,
> Rafael
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Best rega
riginal manufacturer BIOS
> > doesn't supports booting from USB, does CoreBoot supports it?
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>
as being the best graphics card suitable for
> open firmware development? Are there still people working on this?
>
> Best,
> Nico
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least some possibility that someone
> else improves the code in case that makes sense.
>
>
> Kind regards
>
> //Peter
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all over the world! ;-)
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ist have experience flashing this board? I don't
> need anyone to hold my hand, but I would appreciate knowing what flashing
> method works, at least. Would hate to fry the chip.
>
>
> --
> Nicholas C. L. Ipsen
> ___
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(review.coreboot.org)|2a01:4f8:121:1254::2|:443... failed: Network is
unreachable.
WARNING: can't download a ./patch?zip file !
Please check your Internet connection and try again.
press [ENTER] to continue...
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Just a friendly reminder that our vPub event is going on right now ;-)
Join the fun at https://vpub.dasharo.com/
On Sun, Feb 13, 2022 at 11:32 PM Mike Banon wrote:
>
> Dear friends,
>
> on 17 February at 8 PM UTC we are having a Dasharo OSF vPub Winter
> 2022 opensour
designate
a special time for you.
In any case, we will be honoured to see you among us for a great time
together ;-)
[1] https://vpub.dasharo.com/
[2] https://matrix.to/#/#dasharo-osf-vpub:matrix.org
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-- Forwarded message -
From: Patrick Bratu
Date: Thu, Feb 10, 2022 at 1:56 PM
Subject: Re: [coreboot] T440P
To: Mike Banon
Hello Mr. Banon
here is my config
thankyou very much
Best regards
Am 29.01.22 um 16:09 schrieb Mike Banon:
> Please share your coreboot .con
ps://ticket.coreboot.org/issues/184
>
> Is there anyone working on it.
> Any inputs/hints would be appreciated.
>
> --sameer.
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o show up and
> when installing Arch also always come errors can you help me please?
>
> Best Regards
>
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ble
topics
[1] https://lists.fosdem.org/pipermail/fosdem/2021q4/003320.html
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it be ok with you to drop the board, and bring it back when it
> is working again?
>
> There is a cost to keeping boards too long when there is no one
> maintaining them. They may still build, but they can stop working.
> That's happened and in my view it's best not to let it ha
ter 4.18 (8.5 months from now). At that point, we'd create a branch and
>> set up a verification builder so that any deprecated platforms could be
>> continued in the 4.18 branch.
>>
>> Would this schedule work?
>>
>> Martin
>
Dear friends, our vPub v3 event starts in 15 minutes! :D Join us at
https://vpub.dasharo.com/
On Fri, Nov 12, 2021 at 1:25 PM Mike Banon wrote:
>
> Dear friends,
>
> Thank you for a wonderful time with us on our past v1 and v2 online
> parties! :D Now we at 3mdeb are organiz
A87XM-A is also supported?
>
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attendees
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On Fri, Aug 20, 2021 at 10:07 AM Keith Emery
wrote:
> Guy's if the WiKi is unmaintained can we just get rid of it. Google loves
> directing people to it, and it's incredibly confusing / misleading.
Before getting rid of the old Wiki, the community should look through it
page-by-page and move
myself (from
> https://review.coreboot.org/plugins/gitiles/board-status/) and place it
> in the directory?
>
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>
://blog.3mdeb.com/2021/2021-06-01-optiplex_part2/
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ersion -
https://newsletter.3mdeb.com/subscription/23ERA9Fb0
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ot@coreboot.org
> To unsubscribe send an email to coreboot-le...@coreboot.org
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ay7th , 7th May at 3PM UTC
[1] https://blog.3mdeb.com/2021/2021-02-23-osf_vpub_01/
[2] https://osfpga.org/osfpga-foundation-launched/
[3] https://beagleboard.org/beaglev
[4] https://corequest.limesurvey.net/274886?lang=en
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boot training
(because too expensive/rare/advanced/unique if compared to some other
variants)
On Sun, May 2, 2021 at 2:45 PM Nico Huber wrote:
>
> On 29.04.21 11:11, Mike Banon wrote:
> > Dear Friends, please share your thoughts to help us at 3mdeb to
> > advance a core
, Mike Banon
Open Source Community Manager of 3mdeb - https://3mdeb.com/
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> Finally, if the software approach fails, another method may be to look
> for the flash chip on the mainboard and read it out with hardware means.
>
>
> Kind regards
>
> //Peter
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Hi there Elyes,
Your "getpir" idea really helped me to implement a set of CB:48427
"AMD good IRQ" patches.
Thank you so much for your kind help! Wanted to thank you earlier but
it got lost in drafts ;-)
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ndy: +4915252667614
> Adresse: Hausener Weg 96, 60489, Frankfurt am Main
>
>
>
> From: Mike Banon
> Sent: 24 March 2021 13:40
> To: G. Nalin
> Cc: flash...@flashrom.org
> Subject: Re: [flashrom] Fail flashing
>
> Could you please verify that at least a part
/
[2] https://blog.3mdeb.com/tags/trenchboot/
[3] https://osfw.slack.com/
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ater?
> Best regards and thank you
> Gottfried
>
> --
> *
> Gottfried Kunze
> Telefon 03421 7732269
> Mobil 0160 91012179
>
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.
[1]
https://mail.coreboot.org/hyperkitty/list/seab...@seabios.org/thread/VQHRAEFYDRFFMAN5JEG4BUH666KJEZGS/
[2] https://review.coreboot.org/c/coreboot/+/51393
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cbfstool_get.sh
Description: application
dec8577a76bf190c72f69a4b7fe4f8ef53d53af19ac6890485311da7dd6eb2d5 ./coreflop.rom
coreboot revision - b77cf2299c516a7f5a9a4eccad2b21157278a283
You may also play with the other floppies inside if you'd like - it's fun!
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; Edvaldo Silva
> edvaldo@zohomail.com
> +55 12 9 8209 6114
>
>
>
>
> Ativado Ter, 02 mar 2021 13:24:31 -0300 Mike Banon
> escreveu
>
> Well, it looks like your flashing has failed. Why? Maybe your flashing
> setup wasn't reliable enough: long wire
modified in
> any way, thank you.
>
>
> Kindest regards,
>
> Louis
>
>
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has Intel BayTrail SoC, ValleyView chipset and VBIOS. The
> bios do not use GOP driver which replaces VBIOS
>
> Thanks
> Rao
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t; a T410 with success?
>
> Cheers, Daniel
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rking IOMMU on this laptop?
> Thanks,
> Lud
>
>
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_
https://review.coreboot.org/c/coreboot/+/48616 - without this tiny URL
fix, building a secondary tint payload results in an error (since the
old archive became unavailable). Would be nice if you can review this
patch to bring back a wonderful tint game
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://live.evenea.com/3mdeb-vbeer at 18th Feb 3PM GMT to have some
fun with us.
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abios to boot with USB storage.
>
> Thanks,
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Hi there friend,
For 1), did you plug a BIOS chip into a CH341A directly? Or using a
DIP-8 test clip? + would be nice if you have more than one CH341A and
could try with both of them to exclude a programmer's fault (one of my
ch341a had a missing capacitor and another had a badly soldered chip
Hi there Balazs, please tell why you'd need a 4.8.1 branch? Also you
may have to get some old LiveCD (i.e. CentOS 7 has both installation
DVD and a DVD with packages) and build the old coreboot under the
older Linux with everything older.
On Thu, Dec 24, 2020 at 12:03 PM Balázs Vinarz wrote:
>
>
Hi there Ale, two suggestions: 1) check this thread -
https://www.reddit.com/r/coreboot/comments/jdcn5y/latest_coreboot_for_the_asus_kcmad8/
, you may have to revert a specific commit for a fresher coreboot
build 2) try to backport my XMP / custom RAM timings patch to KGPE-D16
related sources and
limitation which prevents
from doing this?
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Mike Banon
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Mike Banon
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> changing the compiled-in offsets)?
>
> That way it would be easier to implement runtime selection and fallback
> mechanisms (e.g. use an nvram value to select the profile and use boot_count
> or "no XMP profile found" to fall back to a stable option)
>
>>
>
quot; list
of csb_patcher.sh growing. Please, could you take a look?
https://review.coreboot.org/c/coreboot/+/40488
https://review.coreboot.org/c/coreboot/+/40489
Best regards,
Mike Banon
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k at
https://review.coreboot.org/c/coreboot/+/47852 .
Maybe we can fix the IRQs for some other AMD fam15h boards in a similar way.
Best regards,
Mike Banon
On Wed, Nov 18, 2020 at 2:14 AM Felix Held wrote:
>
> Hi Mike!
>
> The PIRQ_MISC registers in the indirect I/O address space with 0xc00
>
2020 at 2:43 AM Nico Huber wrote:
>
> Hi Mike,
>
> On 10.11.20 19:22, Mike Banon wrote:
> > Thank you very much for your advice, dear Naresh, I will try matching
> > the UEFI routing.
>
> I wouldn't expect too much. If things are configurable in the chipset
> (the
e trouble understanding:
what is the relationship between mainboard_picr_data/_intr_data,
_pirq_data, and intel_irq_routing_table?
If I got the intel_irq_routing_table with getpir - how to convert its'
contents to these other tables so that they match each other?
Best regards,
Mike Banon
On Tue, Nov
>
> On Thu, 5 Nov, 2020, 6:29 pm Mike Banon, wrote:
>>
>> Still need your help, friend
>>
>> On Sat, Oct 24, 2020 at 11:15 AM Mike Banon wrote:
>> >
>> > Although I found this article
>> > https://www.coreboot.org/Creating_Valid_IRQ
Still need your help, friend
On Sat, Oct 24, 2020 at 11:15 AM Mike Banon wrote:
>
> Although I found this article
> https://www.coreboot.org/Creating_Valid_IRQ_Tables , I'm not sure if
> it applies to mainboard_picr_data/_intr_data : considering a problem
> from my previous msg
if this
article is still valid for these new data structures? If not, how to
get the correct values for mainboard_picr_data/_intr_data using Linux?
On Tue, Oct 20, 2020 at 6:23 PM Mike Banon wrote:
>
> Dear friends, I'm trying to properly program the IRQ tables for Lenovo
> G505S, because th
appreciated.
Best regards,
Mike Banon
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maybe Balazs could advise. However, to make sure you could easily
unbrick your A88XM-E in the case of a bad coreboot build, I really
recommend you to order a cheap USB CH341A programmer (preferably with
a Green PCB) - and PLCC clip to easily remove a DIP8 flash chip from a
motherboard's socket
e model : DCL X4
> DCL is for Daffodil Computers Limited
> X4 is the model
>
> It was running with,
> processor intel core i3 7th gen
> RAM single slot 4gb DDR4
> no optical drive
>
>
> On Wed, Oct 7, 2020, 3:46 PM Mike Banon wrote:
>>
>> Could you at least tell
Could you at least tell us, what's the hardware model of your laptop?
You may be able to extract a good BIOS image from the "BIOS image"
utility provided by the manufacturer of your laptop. I.e. in my case,
I opened a winflash exe with 7zip, found many files including a large
binary file, opened
Although not exactly on topic, this patch [1] contains a list of
Floppy-based OS that could be run by SeaBIOS from a coreboot's CBFS.
Even a PicoBSD is possible, if you have the skills to build it (quite
tricky to be honest).
https://review.coreboot.org/c/coreboot/+/33509
On Tue, Sep 29, 2020
Could be temporarily fixed by changing uintptr_t to unsigned int * :
...
GENbuild.h
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
In file included from src/arch/x86/memcpy.c:5:
src/include/asan.h:63:1: error: unknown type name 'uintptr_t'; did you
dGPU performance should be indifferent of a BIOS being used. Are you
confident that your program is really using a discrete GPU and not an
integrated one (with a poor performance in comparison). To ensure
this, please double check you're running it with DRI_PRIME=1 flag. One
of the easiest ways to
I think, first of all you need to either get a coreboot-supported
motherboard, or a motherboard the components of which are similar
enough to those already supported by coreboot and try to get this
board supported. Then you could: i.e. check what is working on this
board and try to fix what
Hi Grzegorz , please remind what Linux distro you're using and how
fresh is its' drivers/software. AMD drivers really improved during the
last couple of years, but if you're running some ancient "debian" - of
course GPU performance is lower than expected. Myself, I'm currently
using Artix Linux -
It's a bit not obvious, but by searching at
./coreboot/src/mainboard/lenovo$ find . -type f -print0 | xargs -0
grep -n "R500" - I could see that R500 is a variant of Thinkpad
T400: i.e. " ./t400/Kconfig.name:10:config BOARD_LENOVO_R500 " . Since
this board_status table mentions each board type
and enable new allocator
> for all other boards:
> https://review.coreboot.org/c/coreboot/+/41444
> https://review.coreboot.org/c/coreboot/+/41445
>
> This should give us some more time to fix the impacted chipsets and
> keep the boards working in upstream.
>
> On Fri, May 1
and it worked for fam15tn just by a
coincidence. Please take a look at change for a further review
https://review.coreboot.org/c/coreboot/+/41431
On Fri, May 15, 2020 at 1:30 PM Mike Banon wrote:
>
> Looking at your change 41369 - soc/amd/stoneyridge: add resources
> during read_resour
_read_resources,
- .set_resources= domain_set_resources,
+ .read_resources = domain_set_resources,
+ .set_resources= pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
};
On Fri, May 15, 2020 at 12:10 PM Mike Banon wrote:
>
> Although it's still
Nice to see a possible fix. Thank you very much, going to test it tomorrow.
On Thu, May 14, 2020 at 11:29 PM Aaron Durbin via coreboot
wrote:
>
>
>
> On Thu, May 14, 2020 at 2:25 PM Keith Hui wrote:
>>
>> Hi Aaron,
>>
>> I think I have success after applying 41363 as well. Please see
>>
nd other, unofficial patches could be
automatically obtained with a csb_patcher.sh script from 33509 change
to save your time - I'm trying my best to keep up this stuff with a
coreboot master, as well as to get merged at least some of these
changes to reduce this maintenance.
Best regards,
Mike B
It seems to be a common problem for AMD: I've seen it on fam15h
Richland boards. This problem might be possible to fix, I just never
had the time to investigate and solve it. Aside from these angry
messages at dmesg, don't know if there are any extra side effects.
On Wed, May 13, 2020 at 4:54 AM
On Thu, Apr 23, 2020 at 5:42 PM R S wrote:
>
> On Thu, Apr 23, 2020 at 6:46 AM Paul Menzel wrote:
>>
>> PS: By the way, Memtest86+ 5.31b was released [2].
>>
>> [1]: https://review.coreboot.org/c/coreboot/+/32613
>> [2]: https://www.memtest.org/
>
>
> That's huge! Thanks for picking up
i.e. would like to remove the worthless & abandoned 17439 , 17505 ,
17506 , 17507 changes I have done at 2016 year (this work has been
eventually merged, so nothing of a value will be lost) - but a Delete
button for them is not available.
Best regards,
Mike B
att
>
> On Wed, Mar 11, 2020 at 11:24 AM Mike Banon wrote:
>>
>> On Sun, Mar 8, 2020 at 6:56 PM Matt B wrote:
>> >
>> > To those who have a dual-GPU G505s and have enabled the recent support for
>> > the dGPU, does DRI_PRIME GPU offloading work?
&
On Sun, Mar 8, 2020 at 6:56 PM Matt B wrote:
>
> To those who have a dual-GPU G505s and have enabled the recent support for
> the dGPU, does DRI_PRIME GPU offloading work?
>
Yes, DRI_PRIME GPU offloading works on G505S - and actually I think
it's the only possible way of using a discrete GPU on
Is that something like a cable with two built-in FT232H chips ? (to
function as a USB dongle)
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Good day Zir,
It would've been helpful if your article had your e-mail in the end of
it or a reply form - I've stumbled upon your article some time ago,
but didn't find a quick way to share my feedback and got distracted by
something else, maybe the others did too...
1) Thanks for describing
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