Author: stuge
Date: Sat Jun 4 17:40:12 2011
New Revision: 6620
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6620
Log:
vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the
Author: stuge
Date: Sat Jun 4 17:43:15 2011
New Revision: 6621
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6621
Log:
Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall
Author: stuge
Date: Sat Jun 4 17:43:38 2011
New Revision: 6622
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6622
Log:
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from
Author: stuge
Date: Sat Jun 4 17:43:56 2011
New Revision: 6623
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6623
Log:
Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman mbusch...@lucidmachines.com
Author: stuge
Date: Sat Jun 4 17:44:14 2011
New Revision: 6624
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6624
Log:
Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge pe...@stuge.se
Author: stuge
Date: Sat Jun 4 17:44:31 2011
New Revision: 6625
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
Log:
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:44:54 2011
New Revision: 6626
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
Log:
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:45:12 2011
New Revision: 6627
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
Log:
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:45:29 2011
New Revision: 6628
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6628
Log:
Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:45:46 2011
New Revision: 6629
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6629
Log:
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:46:13 2011
New Revision: 6630
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6630
Log:
Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:46:32 2011
New Revision: 6631
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6631
Log:
Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman
Author: stuge
Date: Sat Jun 4 17:46:50 2011
New Revision: 6632
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6632
Log:
Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by:
Author: stuge
Date: Sat Jun 4 17:47:05 2011
New Revision: 6633
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
Log:
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman mbusch...@lucidmachines.com
Acked-by:
Author: stuge
Date: Sat Jun 4 17:47:30 2011
New Revision: 6634
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6634
Log:
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Marshall Buschman mbusch...@lucidmachines.com
Author: stuge
Date: Sat Jun 4 17:47:56 2011
New Revision: 6635
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6635
Log:
Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Marshall Buschman mbusch...@lucidmachines.com
Author: stuge
Date: Sat Jun 4 17:48:14 2011
New Revision: 6636
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6636
Log:
Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Marshall Buschman mbusch...@lucidmachines.com
Modified:
Author: stepan
Date: Sat Jun 4 18:30:27 2011
New Revision: 6637
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6637
Log:
WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer
Author: kerry
Date: Fri Jun 3 12:14:56 2011
New Revision: 6617
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6617
Log:
advansus/a785e-i mainboard enable warning as error
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Kerry She kerry@amd.com
Modified:
Author: oxygene
Date: Wed Jun 1 21:29:48 2011
New Revision: 6615
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6615
Log:
Report build result from abuild (did all requested boards build?)
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Patrick Georgi
Author: oxygene
Date: Wed Jun 1 21:54:16 2011
New Revision: 6616
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6616
Log:
Really fix iasl filename issues in our build system
There's a remaining issue that iasl cuts of \..*$ from
output paths, even if that substring contains / (ie.
Author: kerry
Date: Wed Jun 1 03:56:49 2011
New Revision: 6613
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6613
Log:
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header
Author: kerry
Date: Wed Jun 1 04:00:30 2011
New Revision: 6614
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6614
Log:
trivial remove blanks at the end of line
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Kerry She kerry@amd.com
Modified:
Author: stepan
Date: Mon May 23 19:16:44 2011
New Revision: 6609
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6609
Log:
exclude src/vendorcode from GPLv2 license checks.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer
Author: jakllsch
Date: Mon May 23 19:55:20 2011
New Revision: 6610
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6610
Log:
Correct implementation of r6608.
(.align actually takes its argument in bytes)
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-by: Jonathan Kollasch
Author: stepan
Date: Tue May 24 00:43:43 2011
New Revision: 6611
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6611
Log:
AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer
Author: stepan
Date: Tue May 24 00:48:13 2011
New Revision: 6612
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6612
Log:
We don't have pausing versions of single-IO instructions.
Hence remove the wrong comment.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608
Log:
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
Signed-off-by: Jonathan Kollasch
Author: oxygene
Date: Sun May 22 00:18:59 2011
New Revision: 6607
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6607
Log:
Add regression test for build directory handling to make lint target
A couple of scenarios that were fixed in the last few revisions are
tested to ensure that
Author: Sduplichan
Date: Fri May 20 19:50:14 2011
New Revision: 6601
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6601
Log:
Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Scott Duplichan sc...@notabs.org
Author: oxygene
Date: Sat May 21 00:14:07 2011
New Revision: 6602
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6602
Log:
Fix ccache behaviour if more than one ccache in PATH
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
Author: oxygene
Date: Sat May 21 00:17:58 2011
New Revision: 6604
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6604
Log:
Fix building with relative path to object directory outside the source tree
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
Author: oxygene
Date: Sat May 21 01:08:12 2011
New Revision: 6605
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6605
Log:
Handle both cases, obj being absolute and relative
gnu make's handling of filenames is less than optimal. It simply
compares strings, so foo/../bar is different
Author: oxygene
Date: Sat May 21 01:31:41 2011
New Revision: 6606
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6606
Log:
Handle absolute source file paths
We used to fail there because we unconditionally prefixed the relative
directory where it was referenced.
Tested in various
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6605 to
the coreboot repository. This caused the following
changes:
Change Log:
Handle both cases, obj being absolute and relative
gnu make's handling of filenames is less than
Author: Sduplichan
Date: Fri May 20 02:06:09 2011
New Revision: 6600
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6600
Log:
Move the ACPI FACP table to the front of the RSDT list. This is done to work
around a Windows XP or Server 2003 setup failure where an error message such
as:
Author: oxygene
Date: Mon May 16 17:32:28 2011
New Revision: 6599
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6599
Log:
Move crossgcc rules to coreboot specific Makefile
Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.
Author: mjones
Date: Sun May 15 23:01:42 2011
New Revision: 6570
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6570
Log:
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code
handles it.
Author: mjones
Date: Sun May 15 23:06:30 2011
New Revision: 6571
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6571
Log:
Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:07:43 2011
New Revision: 6572
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6572
Log:
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones
Author: mjones
Date: Sun May 15 23:10:20 2011
New Revision: 6573
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6573
Log:
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfff to fecf.
3) Add AMD recommended non-posted mapping for
Author: mjones
Date: Sun May 15 23:11:41 2011
New Revision: 6574
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6574
Log:
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:13:00 2011
New Revision: 6575
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6575
Log:
Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:18:59 2011
New Revision: 6576
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6576
Log:
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:19:54 2011
New Revision: 6577
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6577
Log:
Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:26:04 2011
New Revision: 6578
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6578
Log:
Move mmconf base from e000 to f800 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Author: mjones
Date: Sun May 15 23:38:08 2011
New Revision: 6579
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6579
Log:
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
Author: mjones
Date: Sun May 15 23:41:00 2011
New Revision: 6580
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6580
Log:
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:45:46 2011
New Revision: 6581
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6581
Log:
Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones
Author: mjones
Date: Sun May 15 23:48:22 2011
New Revision: 6582
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6582
Log:
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:51:31 2011
New Revision: 6583
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6583
Log:
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:54:04 2011
New Revision: 6584
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6584
Log:
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:56:03 2011
New Revision: 6585
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6585
Log:
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Sun May 15 23:59:19 2011
New Revision: 6586
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6586
Log:
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Author: mjones
Date: Mon May 16 00:00:23 2011
New Revision: 6587
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6587
Log:
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Mon May 16 00:02:27 2011
New Revision: 6588
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6588
Log:
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones
Author: mjones
Date: Mon May 16 00:03:45 2011
New Revision: 6589
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6589
Log:
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Mon May 16 00:05:00 2011
New Revision: 6590
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6590
Log:
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Author: mjones
Date: Mon May 16 00:06:09 2011
New Revision: 6591
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6591
Log:
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Mon May 16 00:07:56 2011
New Revision: 6592
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6592
Log:
Update gpp port configuration.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Mon May 16 00:09:09 2011
New Revision: 6593
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6593
Log:
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Author: mjones
Date: Mon May 16 00:10:15 2011
New Revision: 6594
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6594
Log:
Cosmetic cleanup.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: stuge
Date: Mon May 16 00:40:40 2011
New Revision: 6595
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6595
Log:
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Author: mjones
Date: Mon May 16 01:13:54 2011
New Revision: 6596
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6596
Log:
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones marcj...@gmail.com
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: stuge
Date: Mon May 16 02:05:50 2011
New Revision: 6597
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6597
Log:
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Author: stuge
Date: Mon May 16 03:35:03 2011
New Revision: 6598
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6598
Log:
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory.
Author: oxygene
Date: Fri May 13 08:25:16 2011
New Revision: 6569
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6569
Log:
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Signed-off-by: Josef Kellermann se...@arcor.de
Acked-by: Patrick Georgi patr...@georgi-clan.de
Author: oxygene
Date: Thu May 12 08:53:52 2011
New Revision: 6568
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6568
Log:
Remove uart_init() in Siemens sitemp-g1p1
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.
Author: oxygene
Date: Wed May 11 09:44:27 2011
New Revision: 6566
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6566
Log:
Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with
that), but
unfortunately there are some
Author: oxygene
Date: Tue May 10 23:42:52 2011
New Revision: 6563
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6563
Log:
Fix compilation error due to non-unix style line endings in cmos.layout file
while generating option_table.h.
Windows, Mac and *nix type line endings are now
Author: oxygene
Date: Tue May 10 23:47:57 2011
New Revision: 6564
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6564
Log:
This replaces the fixed shift values in the apic timer init with macros.
Signed-off-by: Vikram Narayanan vikram...@gmail.com
Acked-by: Patrick Georgi
Author: oxygene
Date: Tue May 10 23:53:13 2011
New Revision: 6565
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6565
Log:
Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)
Author: mjones
Date: Mon May 9 22:53:38 2011
New Revision: 6562
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6562
Log:
Adds RS740 HT and internal graphics PCI ids.
Signed-off-by: Ivaylo Valkov iva...@e-valkov.org
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: kerry
Date: Sat May 7 10:33:14 2011
New Revision: 6557
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6557
Log:
put the amdlib and agesa constant to .rodata segment.
so amdlib.c would not complain Do not use global variables in romstage
Signed-off-by: Kerry She
Author: kerry
Date: Sat May 7 10:37:38 2011
New Revision: 6558
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6558
Log:
1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is
the sse built-in function
2. move the Amd Lib functions using sse build-in functions
Author: kerry
Date: Sat May 7 10:43:40 2011
New Revision: 6559
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6559
Log:
SB800 CIMX code can share the AGESA V5 lib code,
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and
Author: kerry
Date: Sat May 7 10:51:32 2011
New Revision: 6560
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6560
Log:
RS780 DDI Lanes configure support,
and remove RS780 get_cpu_rev().
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Marc Jones marcj...@gmail.com
Modified:
Author: mjones
Date: Thu May 5 18:45:36 2011
New Revision: 6555
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6555
Log:
Remove AMD Agesa requirement for standard include files
This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the
Author: mjones
Date: Thu May 5 18:49:11 2011
New Revision: 6556
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6556
Log:
Adds VOID to empty parameter lists to get rid of some build warnings.
This change modifies a collection of files by adding the VOID parameter
to empty parameter
Author: svens
Date: Tue May 3 09:55:30 2011
New Revision: 6553
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6553
Log:
i82801gx: enable SPI prefetching
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Sven Schnelle sv...@stackframe.org
Added:
Author: svens
Date: Tue May 3 09:55:43 2011
New Revision: 6554
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
Log:
Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Sven Schnelle sv...@stackframe.org
Modified:
Author: svens
Date: Mon May 2 21:53:04 2011
New Revision: 6552
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6552
Log:
Add option 'compress ramstage'
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to
Author: sduplichan
Date: Sat Apr 30 02:17:23 2011
New Revision: 6550
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6550
Log:
Added:
trunk/README.txt
trunk/conf/
trunk/conf/authz
trunk/conf/passwd
trunk/conf/svnserve.conf
trunk/db/
trunk/db/current
Author: sduplichan
Date: Sat Apr 30 02:22:04 2011
New Revision: 6551
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6551
Log:
Sorry, my mistake.
Deleted:
trunk/README.txt
trunk/conf/
trunk/db/
trunk/format
trunk/hooks/
trunk/locks/
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Author: svens
Date: Thu Apr 28 11:29:06 2011
New Revision: 6549
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6549
Log:
Thinkpad: Enable Battery events
Enable the following events for battery objects on
Thinkpad X60/T60:
24: BAT0 critical
25: BAT1 critical
4A: BAT0 present
4B: BAT0
Author: svens
Date: Wed Apr 27 21:47:28 2011
New Revision: 6545
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6545
Log:
Lenovo H8: add h8_ultrabay_device_present()
returns 1 if a CDROM/HDD device is plugging in the
ultrabay. Return 0 if there's a battery or superio
extensions plugged
Author: svens
Date: Wed Apr 27 21:47:42 2011
New Revision: 6546
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6546
Log:
Lenovo PMH7: add pmh7_ultrabay_power_enable()
Can be used to enable/disable Ultrabay power on Thinkpads
who control that with the PMH7. (i.e. T60)
Signed-off-by:
Author: svens
Date: Wed Apr 27 21:47:49 2011
New Revision: 6547
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6547
Log:
T60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Author: svens
Date: Wed Apr 27 21:48:05 2011
New Revision: 6548
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6548
Log:
X60: enable Ultrabay if device is plugged in
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Author: stepan
Date: Wed Apr 27 01:47:04 2011
New Revision: 6544
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6544
Log:
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
Author: ruik
Date: Sat Apr 23 00:26:04 2011
New Revision: 6541
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6541
Log:
Fix of fix copy and paste errors in ne2k.c (r6512 by stepan)
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Rudolf Marek r.ma...@assembler.cz
Modified:
Author: stepan
Date: Sat Apr 23 01:10:35 2011
New Revision: 6542
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6542
Log:
cosmetic changes to superiotool's nuvoton code
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Author: stepan
Date: Sat Apr 23 01:12:40 2011
New Revision: 6543
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6543
Log:
Add (partly) support for Nuvoton NCT6776F
Signed-off-by: Stefan Reinauer reina...@google.com
Acked-by: Peter Stuge pe...@stuge.se
Modified:
Author: stepan
Date: Thu Apr 21 22:24:43 2011
New Revision: 6535
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6535
Log:
some ifdef -- if fixes
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
Author: stepan
Date: Thu Apr 21 22:45:45 2011
New Revision: 6536
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6536
Log:
more ifdef - if fixes
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
Author: stepan
Date: Thu Apr 21 23:26:58 2011
New Revision: 6537
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6537
Log:
more ifdef - if fixes.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
Author: stepan
Date: Fri Apr 22 03:45:11 2011
New Revision: 6538
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6538
Log:
The UART divider should be calculated based on the base frequency
and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauer
Author: stepan
Date: Fri Apr 22 04:17:26 2011
New Revision: 6539
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6539
Log:
Get rid of all but one (I/O mapped) UART init functions.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer
Author: stepan
Date: Fri Apr 22 04:32:03 2011
New Revision: 6540
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6540
Log:
fix typo ttys0_index - b_index
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Modified:
Author: svens
Date: Wed Apr 20 10:57:53 2011
New Revision: 6524
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6524
Log:
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Added:
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