Dear coreboot folks,
Am 19.02.24 um 22:24 schrieb mina--- via coreboot:
[…]
### [Nico] Revoking Gerrit privileges as punishment.
I would like to discuss two matters about this. Not sure about the order.
* My own case: I was removed from the core developers and reviewers groups
20
Dear coreboot folks,
On the Dell Latitude 5430 Chromebook (google/brya/var/crota) there is a
delay of 160 ms during startup in the Linux kernel [1]:
[0.00] microcode: microcode updated early to revision
0x430, date = 2023-06-07
[0.00] Linux version
Issue #516 has been updated by Paul Menzel.
Status changed from New to Resolved
Affected hardware set to google/brya
Affected versions 4.18 added
Reka, thank you for pointing to commit 1d49d3e40b1b (mb/google/brya: Don't add
MPTS to both DSDT and SSDT).
Is there a way on ChromeOS
Dear coreboot folks, especially users,
Uploads to the board status repository [1] have ceased quite a bit this
year. As most community members only have access to a few devices, these
logs are tremendously useful to support users, and to analyze bugs and
regressions. So, just a quick
Issue #516 has been reported by Paul Menzel.
Bug #516: brya/var/crota: `ACPI BIOS Error (bug): Failure creating named object
[\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)`
https://ticket.coreboot.org/issues/516
* Author: Paul Menzel
[Cc: +Mediatek SOC maintainers]
Dear Jared,
Thank you for your message. I am sorry, nobody replied yet.
Am 04.07.23 um 17:24 schrieb Jared Baur:
I am looking for some advice for configuring coreboot with a uImage
fit payload for an mt8183 chromebook (Kukui Fennel)? I have said
fitimage,
Dear Carl-Daniel,
Am 25.07.23 um 18:54 schrieb Carl-Daniel Hailfinger:
is there any currently commercially available switch or router hardware
(10Gbit/s or more) running coreboot and preferably also Linux?
I'm currently trying to build a PoC network where all components have
mostly FOSS
Issue #476 has been updated by Paul Menzel.
Related links updated
persmule proposes [lib: Hook the FB setting function for Linux to payload
loading routine](https://review.coreboot.org/c/coreboot/+/76428).
One comment from #coreb...@irc.libera.chat: AFAICS, we have avoided
payload-specific
Dear coreboot folks,
*Networking* is also a topic for the ASG! conference.
All Systems Go! 2023 Call for Proposals
The Call for Participation (CFP) for All Systems Go! 2023 is now
open! Please submit your proposals for consideration.
The CFP will close on July 7th, 2023. A response will be
Issue #499 has been updated by Paul Menzel.
Thank you for your report.
As you explicitly mention EDK2 (TianoCore), did you test another payload like
SeaBIOS or GRUB?
Just to avoid confusion, you can get the logs from the CBMEM console using
`cbmem -c` from `util/cbmem/`, or `/sys/firmware
Dear Martin,
Thank you very much for taking the time to answer.
Am 19.06.23 um 22:31 schrieb Martin Roth:
Duplicated code between mainboards isn't a big issue in my opinion.
It allows the boards to be customized without worrying about other
companies' mainboards. We've tried to make
Issue #480 has been reported by Paul Menzel.
Bug #480: amd/common/acpi/gpio_bank_lib.asl: IASL remarks: Creation of named
objects within a method is highly inefficient, use globals or method local
variables instead
https://ticket.coreboot.org/issues
Issue #478 has been updated by Paul Menzel.
Subject changed from X200 booting takes a long time to X200 booting Linux takes
a long time with TSC (`clocksource=hpet` works)
Related links updated
Bug #478: X200 booting Linux takes a long time with TSC
Dear Cagatay,
Welcome to coreboot!
Am 28.03.23 um 15:49 schrieb cagatay bagci via coreboot:
We have a custom CFL board that resembles CFL RVP-11. I compiled the
code and flashed it and it started booting without problem. However
after global reset, it stucks at S5 and S5 signal asserts low.
Issue #463 has been updated by Paul Menzel.
Related links updated
Bug #463: nvramtool: coreboot table not found on Starbook Mark VI
https://ticket.coreboot.org/issues/463#change-1432
* Author: Felix Niederwanger
* Status: Resolved
* Priority: Normal
Issue #314 has been updated by Paul Menzel.
@akjuxr3, do you know of a solution to prevent the creation of spam accounts?
Support #314: Please disable 'administrator approval' on ticket.coreboot.org
https://ticket.coreboot.org/issues/314#change-1412
Issue #456 has been updated by Paul Menzel.
Related links updated
Bug #456: coreboot 4.19 tarballs have bad timestamps
https://ticket.coreboot.org/issues/456#change-1406
* Author: Thierry Laurion
* Status: Feedback
* Priority: High
* Category
Dear Ritul,
Am 06.02.23 um 19:00 schrieb ritul guru:
I am trying to boot to Ubuntu OS on NVMe SSD, NVMe device does get detected
but with SeaBIOS payload, observing
timeout on nvme_wait,
Appreciate any hint to debug this issue.
Logs:
All threads complete.
Searching bootorder for:
Dear Łukasz,
Am 03.02.23 um 10:24 schrieb Łukasz Jeleń:
i've tried to turn on logging on serial console with:
serial --port=0xA0019000 --speed=115200 --word=8 --parity=no --stop=1
terminal_input --append serial
terminal_output --append serial
added to grub.cfg, but it does not work.
The
Dear coreboot folks,
Am 29.12.22 um 14:05 schrieb Paul Menzel:
A colleague made me aware of the presentation *The OSF on Supermicro's
platform* [1] by the Supermicro employees Hancock Chang and Simon Chou¹
at the OCP Global Summit 2022 this October. This is great news. I would
have loved
Issue #449 has been updated by Paul Menzel.
Related links updated
Bug #449: ThinkPad T440p fail to start, continous beeping & LED blinking
https://ticket.coreboot.org/issues/449#change-1374
* Author: Crazy Fox
* Status: In Progress
* Priority: No
Dear Ron,
Am 08.01.23 um 20:16 schrieb ron minnich:
But in some cases static libs are no longer provided at all. Would be nice
to know if that's the case for libuuid.
The static library is part of `uuid-dev` [1]:
/usr/include/uuid/uuid.h
/usr/lib/x86_64-linux-gnu/libuuid.a
Issue #446 has been updated by Paul Menzel.
> built coreboot as usual against the Optiplex 9010 SFF platform in menuconfig
Does the “as usual” mean it worked for you in the past?
You could try to get early log message over the serial console or the flash
console (`CONSOLE_SPI_FL
Issue #445 has been updated by Paul Menzel.
Thank you for providing these files. As it’s a PCIe card, please also attach
the output of `lspci -nn`, `lspci -tv` and `sudo lspci -vvvxx` – preferably
with (working) Libreboot and (problematic) coreboot
Issue #445 has been updated by Paul Menzel.
Please attach the `.config` and the coreboot logs (`cbmem -1`) and Linux logs
(`dmesg`).
Bug #445: Thinkpad X200 wifi issue
https://ticket.coreboot.org/issues/445#change-1334
* Author: Masc Masc
* Status: New
Dear Martin,
Am 23.12.22 um 01:00 schrieb Martin Roth via coreboot:
Also, I think I tracked down the commit that that tree was based on:
5d0601767f vendorcode/amd/agesa/fam10: Build as a static library (2014-12-08)
Method:
[…]
Looking at what's contained in the repo on github, I'd
Issue #429 has been updated by Paul Menzel.
Description updated
Bug #429: I2C CR50 TPM fails to initialize
https://ticket.coreboot.org/issues/429#change-1192
* Author: Matt DeVillier
* Status: New
* Priority: High
* Target version: none
* Start date
Dear David,
Thank you for the message.
Am 07.10.22 um 07:46 schrieb David Hendricks:
As mentioned in this week's leadership meeting, membership in the Open
Source Firmware Foundation (OSFF) has been under consideration for
some time and we feel that we should move ahead. We plan to join by
Issue #414 has been updated by Paul Menzel.
[Everyone, when replying please remember to remove the full citation and to use
interleaved style, when replying to issue reports, as otherwise the Redmine Web
interface becomes convoluted very quickly.]
Thank you for uploading the logs
Issue #412 has been updated by Paul Menzel.
Please attach the coreboot console messages from a normal boot, and from
resuming from suspend to RAM.
In GNU/Linux you should be able to do it using `cbmem -1`, or, if available,
loading the module *memconsole-coreboot* with `sudo modprobe
Dear Pedro,
Am 06.08.22 um 18:45 schrieb Pedro Erencia:
I was going to try coreboot on an ASROCK FM2A88X Extreme4+ (
https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration
of the supported ASUS A88XM-E (
https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the
Issue #392 has been updated by Paul Menzel.
Nice test. Please bisect with
$ git bisect start 4.16 4.15 -- src/drivers/intel/gma/acpi
and build and test each commit that is shown. (This only works, if the
regression really is in `src/drivers/intel/gma/acpi` – otherwise, just use
Dear Mike,
Am 23.06.22 um 09:49 schrieb Mike Banon:
If I use a default config for i440fx/piix4, building a 16MB ROM works
fine, but 32MB or 64MB doesn't work anymore:
...
CC postcar/southbridge/intel/common/rtc.o
LINK cbfs/fallback/postcar.debug
OBJCOPY
Issue #392 has been updated by Paul Menzel.
> 1. Image of BSOD attached. No additional information.
Strange that there is no more specific error code.
> 2. How can i create coreboot.log of both images?
If your Linux kernel is recent enough (maybe from backports), a
Issue #392 has been updated by Paul Menzel.
Subject changed from Coreboot 4.16 & 4.17 - SeaBIOS Windows 10 BSOD "ACPI
Error" to coreboot 4.16 & 4.17 - SeaBIOS Windows 10 BSOD "ACPI Error"
1. Please attach a photo of the BSOD, or copy all messages from it.
1. Pl
Issue #392 has been updated by Paul Menzel.
Subject changed from Coreboot 4.16 & 4.17 - SeaBios Windows 10 BSOD "ACPI
Error" to Coreboot 4.16 & 4.17 - SeaBIOS Windows 10 BSOD "ACPI Error"
Bug #392: Coreboot 4.16 & 4.17
Issue #327 has been updated by Paul Menzel.
@Mat, on what board did you test?
@Pawel, please do not post unrelated questions to this issue here. This issue
(#327) is not about a regression as far as I know.
Bug #327: MBOX3, OperationRegion (OPRG
Dear Suma,
Am 11.06.22 um 00:16 schrieb Sumo:
My denverton system is crashing after the FSM memory init, probably when
jumping to POSTCAR. The following lines are shown before the crash:
[DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged
[DEBUG] Loading module at 0x7f7ce000
Dear coreboot folks,
Please find a attached the call for papers for the *System Boot and
Security Microconference* at the *Linux Plumbers Conference* in Dublin,
September 12–14, 2022.
Kind regards,
Paul--- Begin Message ---
Hi,
It is our pleasure to inform you that System Boot and
Dear coreboot folks,
Am 20.04.22 um 22:49 schrieb coreboot org:
# 2022-04-20 - coreboot Leadership
[…]
* Patrick will look at adding the security mailing list to the page at
[http://mail.coreboot.org](http://mail.coreboot.org)
Patrick already did that during the meeting [1].
Dear Dubravko,
Am 07.04.22 um 13:22 schrieb Dubravko Moravski | Exor Embedded S.r.l.:
I work for a company that makes a board containing an Elkhart Lake
CPU and we use Coreboot to boot it.
Welcome to coreboot! It’s great to hear, that you use it. A minor note
in the beginning, that
Dear Felix,
Am 31.03.22 um 22:55 schrieb Felix Singer:
to me it seems like the Intel Quark SoC has been unmaintained and
unused for a long time now.
Can you be more specific please?
So I'm proposing to deprecate the support
for it with coreboot release 4.17 [1], in order to drop the
Dear Alten,
Am 09.03.22 um 08:59 schrieb Alten_Zheng--- via coreboot:
Hi,I am Alten.A bios enginner. Sorry,I have a question, what can I to
ask about intel platform question or I need to sent the mail.
Welcome to coreboot. Yes, to ask a question, please send it to this
mailing list with a
Dear coreboot folks,
*gcc-12* snapshot packages are available in Debian sid/unstable, and
build testing coreboot with that shows new array out of bounds warnings.
For qemu/i440fx:
```
$ gcc-12 --version
gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master
Dear Jeff,
Am 12.01.22 um 15:49 schrieb Jeff Daly:
Ok, so what I've figured out is that it seems gerrit doesn't like it
when the code gets refactored. I have several commits that are
showing merge conflicts but the files that have conflicts are because
a lot of code changes between them as
Dear Guenter, dear Dmitry,
Am 21.12.21 um 17:47 schrieb Guenter Roeck:
On Mon, Dec 20, 2021 at 1:49 PM Dmitry Torokhov wrote:
On Mon, Dec 20, 2021 at 1:07 PM Paul Menzel wrote:
From: Furquan Shaikh
Google Chromebooks are often built with devices sourced from different
vendors
From: Furquan Shaikh
Dear Linux folks,
Google Chromebooks are often built with devices sourced from different
vendors. These need to be probed. To deal with this, the firmware – in
this case coreboot – tags such optional devices accordingly – I think
this is commit fbf2c79b
Dear Julius,
Am 06.12.21 um 23:42 schrieb Julius Werner:
If I remember correctly, coreboot’s goal to only do minimal hardware
initialization originally meant, that the payload/OS does PCI
initialization.
FWIW, coreboot does do device initialization for things that are only
needed by the
Dear Moisés,
Am 06.12.21 um 17:21 schrieb Moisés Simón:
I was using got version yesterday.
Please always give the git commit hash, so it’s unambiguous.
But today I have tested with 4.15
and same problem. I can test with an early version even do a git
bisect if needed.
Do you have a
Dear Moisés,
Am 06.12.21 um 15:28 schrieb Moisés Simón:
Im trying to install coreboot on ga-b75m-d3h. I always get a black
screen (no beeping). I have included vgabios.bin, tried VGA text mod
, libgfxinit... Still no screen output. I have installed coreboot on
thinkpads before. Not suere what
Dear coreboot folks,
Currently, work is underway to add PCI support to ARM platforms [1][2].
If I remember correctly, coreboot’s goal to only do minimal hardware
initialization originally meant, that the payload/OS does PCI
initialization. Only due to shortcomings in the Linux kernel many
Dear coreboot folks,
Am 25.11.21 um 17:43 schrieb Patrick Georgi:
On 25.11.21 17:04, Mike Banon wrote:
[…]
[ forking threat, and follow-up comment ]
Please let’s not escalate this. (Type your answer, save it in the draft
folder, sleep over it, and then think if you want to send it.)
I
Dear Jonathan,
Am 05.11.21 um 20:05 schrieb Jonathan Zhang:
We now have the first commercially available coreboot solution for
servers based on Intel Xeon-SP processor (specifically CooperLake
Scalable Processor).
These are great news. (As always a nit: Cooper Lake-SP ;-))
WW OCP
Dear Martin,
Am 08.11.21 um 19:38 schrieb Martin Roth:
Nov 7, 2021, 04:13 by nic...@gmx.de:
On 07.11.21 00:11, Martin Roth wrote:
CB:55367 was pushed on June 9th. It's 5 months later. Intel
hasn't been able to get it merged yet. Sure, we're not outright
saying they can't get it in, but
Dear Martin,
Am 05.11.21 um 18:15 schrieb Martin Roth:
Nov 4, 2021, 05:24 by pmen...@molgen.mpg.de:
On 20.10.21 14:24, Nico Huber wrote:
My proposal: How about we set up some guidelines how to proceed
when adding support for a new platform that requires any blobs?
My vague idea is as
Dear Nico,
On 20.10.21 14:24, Nico Huber wrote:
a recent yet-another-blob occurrence reminded me that I wanted to
write about the matter for a long time.
Every few months, it seems (if not, more often), a new blob is
introduced to coreboot. Alas, this is often hidden to the last
minute,
Dear Ilker,
Am 04.10.21 um 22:28 schrieb Ilker C:
I have this computer since 11 years and working with triple boot from SSD
and HDD. Also I have PCI graphics card Radeon 512 KB. I overclocked the
CPU to 2Ghz to run Linux Mint and Win 10.
I had a problem with windows 10 due to the PCI
Dear Sumo,
Am 16.08.21 um 18:38 schrieb Sumo:
The NVMe is not detected when serial console logs are disabled, I mean by
setting both Coreboot log_level=Error (or less) and FSP
PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then
further on the device is not listed in the
Dear Keith,
Am 16.08.21 um 12:39 schrieb Keith Emery:
I went one further and just deleted the whole working directory,
re-cloned coreboot and built using that exact configuration. All to
little avail.
Please do not leave the other questions/requests unanswered.
How do I go about finding
Dear Keith,
Am 16.08.21 um 09:16 schrieb Keith Emery:
coreboot-4.14-1405-gad08265740-dirty Sun Aug 15 07:12:41 UTC 2021
The dirty flag suggests, you have local changes. Please paste the output
of `git status` and `git diff`.
Also, please attach `defconfig` generated by `make
Dear Alex,
Am 31.07.21 um 08:55 schrieb Alexander Zhang:
Does anyone know if coreboot supports the ASRock H110M-DVS R3.0
mainboard? The documentation doesn't mention the revision number but the
links are all for the R2.0 board and I can only find R3.0 boards for sale.
What did you find out
Dear coreboot folks,
Patrick prepared the GCC 11.2 for the coreboot toolchain (crossgcc) [1].
It’d be great if everybody gave it a go, and reviewed the change-sets.
If somebody has a system (scripts) to compare the build artifacts of the
current GCC 8.3.0 builds with GCC 11.2, it’d be
Dear Zahra,
Am 24.06.21 um 05:45 schrieb zahra rahimkhani:
I am trying to install windows 8 on coreboot (4.11 branch) + seabios.
The installation stops with the following error message:
Your PC needs to restart.
Please hold down the power button.
Error Code: 0x005c
Parameters:
Dear Angel,
Am 11.06.21 um 12:05 schrieb Angel Pons:
On Fri, Jun 11, 2021 at 9:19 AM Nico Huber wrote:
On 11.06.21 00:55, Sven Semmler wrote:
On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install,
I see these error messages when turning on the PC:
mce: [Hardware Error]:
Dear coreboot folks,
Arthur provided change-set *sb/amd/hudson: Skip setting up LPC decode
for base < 0x20* [1] fixing a hang when doing `outb(0, DMA1_RESET_REG)`
on the Asus F2A85-M PRO with Nuvoton NCT6779D:
In some board ports SuperIO chips in the devicetree are not properly
set up with
Dear se7enge,
Am 05.06.21 um 19:52 schrieb se7enge via coreboot:
I am about to embark on a mission to install coreboot on an ASUS
F2A85-M PRO (w/ AMD A10-6800k) desktop machine. Admittedly, I don't
have much experience in this field and am not extremely technical;
but I am willing to learn
Dear coreboot folks,
There is no common length modifier for u32 for “32-bit and 64-bit”.
Currently, I am running into problems building
`src/cpu/x86/smm/smm_module_loader.c:415:42` with
`x86_64-linux-gnu-gcc-10 -m32` [1].
printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", __func__,
Dear Branden,
Am 26.05.21 um 04:25 schrieb Branden Waldner:
On 5/25/21, Paul Menzel wrote:
Am 22.05.21 um 20:03 schrieb Branden Waldner:
On 5/21/21, Arthur Heymans wrote:
Thanks for sharing your findings. The flash is 256K big, which is quite
small these days.
When building coreboot
Dear coreboot folks,
Am 26.05.21 um 08:38 schrieb Felix Singer:
[…]
Currently, on libera there are 46 people and on OFTC 2 people (me included).
So I would say let's move to libera.
Agreed. Let’s do what most members in #coreboot users already did.
Kind regards,
Paul
Dear Branden,
Am 22.05.21 um 20:03 schrieb Branden Waldner:
On 5/21/21, Arthur Heymans wrote:
Thanks for sharing your findings. The flash is 256K big, which is quite
small these days.
When building coreboot with default settings but without a payload I find
that there is 69K empty space
Dear coreboot folks,
Some Google Chromebooks come with a Google Wilco EC (EC_GOOGLE_WILCO)
instead of Google Chrome EC. coreboot implements the interface for the
Google Wilco EC.
Unfortunately, I was unable to find more details on the firmware.
Phoronix claims is “open-source firmware”
Dear coreboot folks,
In a few days I am going to get my hands on a Dell Latitude 5400
Chromebook Enterprise (google/sarien) [1][2], and my goal is to install
upstream coreboot on it.
According to *Developer Information for Chrome OS Devices* [1], Case
Closed Debugging (CCD) [3] is not
Dear Branden,
Am 21.05.21 um 05:36 schrieb Branden Waldner:
When testing the latest coreboot code before the 4.14 release, I found
I couldn't build a working image with the default (or what I usually
use) config for the asus/p2b. I figured out that it failed to build
with an error of not
Dear Piotr,
Am 10.05.21 um 13:51 schrieb Piotr Król:
On 5/10/21 1:45 PM, Paul Menzel wrote:
Am 10.05.21 um 10:51 schrieb Piotr Król:
On 5/8/21 9:24 AM, Paul Menzel wrote:
Am 28.04.21 um 00:38 schrieb Piotr Król:
(...)
This is one part of the problem, other is specifications
Dear Piotr,
Am 10.05.21 um 10:51 schrieb Piotr Król:
On 5/8/21 9:24 AM, Paul Menzel wrote:
Am 28.04.21 um 00:38 schrieb Piotr Król:
(...)
This is one part of the problem, other is specifications compatibility
where ACPI is one that breaks things often. coreboot moves with ACPI
compiler
Dear Piotr,
Thank you for bringing up these issues.
Am 28.04.21 um 00:38 schrieb Piotr Król:
On 4/21/21 8:33 PM, Patrick Georgi via coreboot wrote:
In our leadership meeting[1] we discussed how we should deal with
tree-wide changes (ranging from "new file header" to "some API is gone
Dear Gert,
Am 28.03.21 um 09:26 schrieb Gert Vanhaerents:
Hi Coreboot,
Welcome to coreboot.
(Please note, coreboot is spelled all lowercase.)
We are from a computer store and we sell computers and laptops with
Linux or Windows or dual boot. For Linux we are many asked for laptops
with
Dear Mike,
Thank you for your answer.
Am 04.03.21 um 18:15 schrieb Mike Banon:
Hi Paul, as for me I could successfully run KolibriOS in QEMU/i440fx
4MB with coreboot and SeaBIOS. Here's my sequence of actions:
git clone https://review.coreboot.org/coreboot/
cd ./coreboot/
make crossgcc-i386
Dear Julius,
Am 04.03.21 um 23:20 schrieb Julius Werner:
https://qa.coreboot.org/job/coreboot-boot-test/ sends off ToT builds to
9esec's Lava system where they are run on some virtual and real devices.
See for example the comments to
https://review.coreboot.org/c/coreboot/+/51189 where Lava
Dear coreboot folks,
I am failing to run KolibriOS [1] in QEMU with coreboot.
```
$ wget -4 --quiet https://builds.kolibrios.org/eng/latest-img.7z
--2021-03-03 15:38:28-- https://builds.kolibrios.org/eng/latest-img.7z
Auflösen des Hostnamens builds.kolibrios.org (builds.kolibrios.org)…
Dear techmindams04,
Am 05.02.21 um 14:11 schrieb techmindam...@gmail.com:
I have generated a payload from edk2 2017. When i booting with
payload i got struck after the below message. The keyboard is not
detecting so i can't press any key. Mouse got powered up. Even i
exchanged the usb ports
Dear Ale,
Welcome to coreboot.
Am 22.12.20 um 01:31 schrieb Ale:
I have a kgpe d16 motherboard with coreboot and seabios, and 2
opteron 6282 SE processor with 64 gb of RAM: all the modules are 16
Gb hynix HMT42GR7AFR4C - RD and all are inserted into the orange
slots. The problem is, if I
Dear Ranga,
Am 28.12.20 um 12:45 schrieb Rao G:
On the Baytrail platform with ALC262 Realtek Codec, HDA Audio is enumerated
as PCI device 00 1b 00,
the verb table is being programmed on HDABAR + command offset.
Using uefi Payload which has PchInit -> DetectAndInitializeAzalia, there
are no
Dear Marshall, dear Felix, dear coreboot folks,
As documented in *AMD Family 17h in coreboot* [1][2], the AMD Secure
Processor [3], formerly known as Platform Security Processor [4], now
discovers, enables and trains DRAM [5].
Ron compared it to the QEMU Q35 target in his OSFC 2020 talk
Dear Wim, dear Daniel,
First, thank you for including all parties in the discussion.
Am 04.12.20 um 13:52 schrieb Wim Vervoorn:
I agree with you. Using an existing standard is better than inventing
a new one in this case. I think using the coreboot logging is a good
idea as there is indeed a
Dear coreboot folks,
It looks like not directly related to TianoCore, but at the Open Source
Firmware Conference 2020 starting on December 1st, the talk *SeaBIOS as
CSM on physical hardware* is going to be presented [1].
Kind regards,
Paul
[1]: https://cfp.osfc.io/osfc2020/talk/YWWRVG/
Dear Andy,
Am 27.11.20 um 12:47 schrieb Andy Pont:
With the stock BIOS in the board I am working on one of the nodes for
the ALC256 CODEC is:
What board is this and what chipset?
Node 0x21 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out
Control: name="Headphone Playback Switch", index=0,
Dear coreboot folks,
Am 10.11.20 um 16:23 schrieb werner@siemens.com:
We could introduce a Kconfig switch per driver and let the driver
handle the bit. Everything else could be removed. This would make it
easier to track the usages. It would be nice if we could agree on a
naming scheme so
Dear Nico,
Am 22.10.20 um 22:37 schrieb Nico Huber:
On 19.10.20 19:06, Paul Menzel wrote:
Looking at the Asus A88XM-E files, it turns out there is a macro
`BLDCFG_FCH_GPP_PORT2_PRESENT` to configure this behavior. Defining this
to `TRUE`, the bridge and ethernet device are detected [4
Dear coreboot, GRUB, and SeaBIOS folks,
In #coreb...@irc.freenode.net somebody mentioned the Universal Payload
Project [1].
The goal of this project is to define an interface between a first
stage platform initialization bootloader and a second stage payload.
As there also is a
Dear Peter, dear Michał,
Am 16.10.20 um 17:05 schrieb Paul Menzel:
Am 16.10.20 um 15:22 schrieb Michal Zygowski:
..
PCI: 00:15.0 init
PCI: 00:15.0 init finished in 0 msecs
PCI: 00:15.1 init
PCI: 00:15.1 init finished in 0 msecs
PCI: 00:18.1 init
PCI: 00:18.1 init finished in 0 msecs
Note
Dear Peter, dear Michal,
Am 16.10.20 um 15:22 schrieb Michal Zygowski:
..
PCI: 00:15.0 init
PCI: 00:15.0 init finished in 0 msecs
PCI: 00:15.1 init
PCI: 00:15.1 init finished in 0 msecs
PCI: 00:18.1 init
PCI: 00:18.1 init finished in 0 msecs
Note that there is no init for 15.2 above. I
Dear coreboot folks,
To get PCI bridge 0:15.2 enabled for the network device on the Asus
F2A85-M PRO, I want to debug the PCIe General Purpose Ports lane
configuration of the FCH.
I’d like to print some variables in
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c
over the
Dear coreboot folks,
On grub-devel, the GRUB2 minisummit [1] was announced.
Two 45 minutes slots are still available. It’d be great if it could be
something coreboot related.
Kind regards,
Paul
[1]: https://twitter.com/3mdeb_com/status/1316057910816976899
Dear coreboot folks,
Trying to finish the Asus F2A85-M PRO coreboot port (AMD Family
15h/Hudson), the internal network device does not work with the state
from [1].
With the vendor firmware 6601, it is
04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd.
Dear Rudolf,
Am 03.10.20 um 20:39 schrieb Rudolf Marek:
Dne 03. 10. 20 v 16:16 Paul Menzel napsal(a):
I’ll try to figure out, what is wrong with the Super I/O settings
in the devicetree. Removing the devicetree Super I/O configuration
already gets rid of the hang, but causes other problems
Dear coreboot folks,
Am 02.10.20 um 10:34 schrieb Paul Menzel:
Am 02.10.20 um 00:50 schrieb Paul Menzel:
I am trying to finish the port for the Asus F2A85-M Pro (variant of
Asus F2A85-M). After getting the serial console working [1], it can be
seen, that accessing `DMA1_RESET_REG
Dear coreboot folks,
Am 02.10.20 um 00:50 schrieb Paul Menzel:
I am trying to finish the port for the Asus F2A85-M Pro (variant of Asus
F2A85-M). After getting the serial console working [1], it can be seen,
that accessing `DMA1_RESET_REG` in `isa_dma_init()` hangs the system [2
Dear coreboot,
I am trying to finish the port for the Asus F2A85-M Pro (variant of Asus
F2A85-M). After getting the serial console working [1], it can be seen,
that accessing `DMA1_RESET_REG` in `isa_dma_init()` hangs the system [2].
outb(0, DMA1_RESET_REG);
Commenting this out,
Dear coreboot folks,
Making a Kaby Lake-U variant port [1], building an image, I notice the
log say the microcode update files sizes in the FIT table are 0.
Platform is: sklkbl
File build/coreboot.pre is 16777216 bytes
IFDTOOLme.bin -> coreboot.pre
Platform is: sklkbl
File
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