[coreboot] Re: Baytrail issue to communicate with superios.

Hi Jose, Dne 05. 12. 23 v 11:06 Jose Trujillo via coreboot napsal(a): Good day Rudolf/All, OK so it does work. Yesterday I copy/pasted the subroutine and its definitions used to enable SERIRQ and set the mode (sc_enable_serial_irqs) and now I can see serial output but no input on ttyS0.

[coreboot] Re: Baytrail issue to communicate with superios.

Hi Jose, Dne 04. 12. 23 v 10:48 Jose Trujillo via coreboot napsal(a): Printed "B" on the other side of the RS-232 cable on the ttyS0 port. OK so it does work. Do you know if is possible to enable SERIRQ and set SCNT_CONTINUOUS in the actual baytrail code? Well sorry I don't know. It has

[coreboot] Re: Baytrail issue to communicate with superios.

Hi, Dne 01. 12. 23 v 16:04 Jose Trujillo via coreboot napsal(a): Using "superiotool" to scan for SIO devices finds Winbond W83627DHG and dumped all its registries but doesn't show Fintek f81803 because of lack of support, so, data exchange between the processor and the SIO chips via LPC port

[coreboot] Re: Coreboot Machine-Check Exception

Hi, On 09. 01. 23 6:09, Ahmet Fenerci via coreboot wrote: Lastly, I checked the "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 4: Model-Specific Registers" to solve problem, but I couldn't find the source of the problem. I have a few questions ; You need to modify

[coreboot] Re: Stuck on SB clock to SIO.

Hi, On 07. 10. 22 22:16, Pedro Erencia wrote: Hi everyone. I'm a bit stuck on this. As I've said before in other emails here, I'm trying to bring up an AsRock FM2A88X+ with coreboot. I've used as a model the code for the a88xm-e and accomplished my first goal, which was to have a working

[coreboot] Re: Invalid opcode exception(06) while loading network drivers in CamelBack Mountain CRB (Coreboot-4.11 + Uefipayload)

Hi, On 27. 08. 22 11:31, Noyal Johnson wrote: Hi, X64 Exception Type - 06 (#UD - Invalid Opcode) CPU Apic ID - !!! Cant find image information !!! Do you know what kind of instruction it is? Probably dumping "RIP" + some bytes around and then decoding it would help. I

[coreboot] Re: 2022-03-29 - coreboot UEFI working group meeting minutes

Kind regards Arthur On Tue, Apr 19, 2022 at 10:44 AM Rudolf Marek mailto:r.ma...@assembler.cz>> wrote: Dne 12. 04. 22 v 0:04 Peter Stuge napsal(a): > I propose that coreboot tables are a good alternative - fight me! :) Challenge accepted. They aren't because they are defined

[coreboot] Re: 2022-03-29 - coreboot UEFI working group meeting minutes

Dne 12. 04. 22 v 0:04 Peter Stuge napsal(a): I propose that coreboot tables are a good alternative - fight me! :) Challenge accepted. They aren't because they are defined with ABI/compiler: - 64-bit data type alignment is different in 32-bit ABI (4 bytes) and different in 64-bit ABI (8

[coreboot] Re: 2022-03-01 - coreboot UEFI working group meeting minutes

Hi, On 01. 03. 22 20:21, coreboot org wrote: * [Nate] Might need to save the efi memory map so that data isn’t lost when converting to an e820 memory map and back. Linux may rely on GRUB doing that - so look into GRUB. Looks like the the superset of various memory region types is defined

[coreboot] Re: Accessing extended capabilities PCI registers?

Hi, On 25. 11. 20 20:26, Rafael Send wrote: > Any ideas for what I could try here, or reasons why it might not (be expected > to) work? The extended PCI configuration space access requires a special memory region (up 256MiB) which translate accesses to the PCI configuration cycles. It is

[coreboot] Re: Asus F2A85-M Pro: Accessing DMA1_RESET_REG in `isa_dma_init()` hangs system

Hi, Dne 03. 10. 20 v 16:16 Paul Menzel napsal(a): > I’ll try to figure out, what is wrong with the Super I/O settings in the > devicetree. Removing the devicetree Super I/O configuration already gets rid > of the hang, but causes other problems. Help is appreciated. Please can you check how

[coreboot] Re: KGPE-d16 recent microcode (Adds IBPB) produces kernel panics

Dne 30. 07. 19 v 11:18 Kinky Nekoboi napsal(a): > loading the microcode via Linux Kernel works. > > including it via coreboot causes General Protection Faults. It fails on MSR write: 17.170377] RSP: 0018:9d003e10 EFLAGS: 00010046 [ 17.175699] RAX: 0001 RBX:

[coreboot] Re: Are AMD CPUs as researched as Intel ones (was Re: New Intel microcode release for migiating ZOMBIELOAD FALLOUT AND OTHERS)

Hi On 15. 05. 19 17:28, Nico Huber wrote: Hi Ivan, I'm curious. Did you do or know somebody who did as much research on AMD processors, as was necessary to find these vulnerabilities? If not, how can you make such comparisons? Here [1] is a official AMD paper on the speculation behavior in

[coreboot] Re: New API to clear DRAM at boot

Hi, Dne 26. 02. 19 v 22:58 Nico Huber napsal(a): > On 26.02.19 20:16, ron minnich wrote: >> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph >> wrote: >>> >>> Hi coreboot folks, >>> in order to support TEE like Intel TXT it is necessary to be able to >>> clear all DRAM at boot on request. >>> >>>

Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Hi, Dne 25. 10. 18 v 9:17 Zheng Bao napsal(a): > Any more ideas? Thanks. Maybe the bus topology is different in coreboot. It would explain why SATA works, because it is on bus 0. Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] [AMD family16h] What need to be done in coreboot to support the Virtual Wire mode

Hi, Dne 23. 10. 18 v 1:57 Marc Jones napsal(a): > Does VxWorks use the ACPI tables for IRQ routing? You might need that. Yes good question. Usually OS uses ACPI, or MPTable or what BIOS provided in the PCI device itself. It seems because you are asking for the virtual wire mode IOAPIC is not

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Hi, Sifive did great job [1] [2] and everything is now opensource including mask rom loader. "Today we’re finally able to rectify this issue by releasing the FU540-C000’s ZSBL and FSBL as an open source project, which can be found on GitHub like all of SiFive’s other open source projects."

Re: [coreboot] L1TF

Hi, On 15.8.2018 15:58, Shawn wrote: According to the vulnerability analysis, the SMM is affected by L1TF. Since SMM code base in coreboot is much smaller than OEM's firmware, IMOHO L1TF is not practical on coreboot. Any idea about is coreboot vulnerable to L1TF? You need an updated microcode,

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Hi all See [1] > terpstraWesley W. TerpstraVerified SiFive Account > 2d > > I saw a few posts on the internet, which misrepresented what I was > expressing. I never suggested reverse engineering our partner’s IP! > > SiFive is committed to supporting the open-source community. We are pleased

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Hi, Dne 25.6.2018 v 09:01 Jonathan Neuschäfer napsal(a): > If this is the Denali DDR controller, do you think it would be possible > to simply read the initial configuration out of the registers of a > booted system? (In any case, that's probably worth trying.) Perhaps it could work with the

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Hi, Lets do some speculation that some off the shelf DDR memory controller is used. Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from Cadence? It has also some "interrupt status" bits and such and "bstlen" which sounds same as the few regs named as the

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Hi Ron, Dne 24.6.2018 v 20:59 ron minnich napsal(a): > and ... there ends my interest in the hifive. A shame. Well perhaps because the DDR controller is third party IP, see [1] FAQ or here: > The Freedom U540 SoC is based on the Freedom Unleashed Platform, which has > been open sourced. The

Re: [coreboot] Problem with W83627DHG in Baytrail I (Possible IRQ conflict or overlapped SOC legacy COM1)

Hi, In general I would check ELCR (I/O port register 0x4d0) to check if it is correctly programmed to EDGE/LEVEL (it should be edge) Also, how the Linux is supposed to detect the I/O port irq? I think you need some PNP device in ACPI to let linux infer the IRQ. I would also try to disable the

Re: [coreboot] AMD IMC open source firmware replacement

Dne 30.5.2018 v 16:06 Mike Banon napsal(a): > Hi Rudolf, > > Regarding this part: > " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. " > what command do I need to use to check this? Try: sudo setpci -s 14.3 40.b Despite command name, it will print the value. Thanks Rudolf --

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi again, Dne 23.5.2018 v 21:52 Rudolf Marek napsal(a): > For some reason this firmware update deletes microcode for Trinity CPUs, I > tried to contact the person who commit this > without any luck. As I have previously written the github page has even newer > microcode. Th

Re: [coreboot] AMD IMC open source firmware replacement

Hi Mike, My firmware was just a proof of concept. It was never anything else. I was just able to run some program and that was all. Please make sure your IMC is active using info on wiki page. I suspect usually it wasnt used as laptop EC. Thanks Rudolf Dne 25.5.2018 v 14:31 Mike Banon

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi all, Dne 22.5.2018 v 07:03 taii...@gmx.com napsal(a): > AMD has at long last coughed up the stuff to the linux-firmware people > > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/diff/amd-ucode/microcode_amd_fam15h.bin?id=77101513943ef198e2050667c87abf19e6cbb1d8 >

Re: [coreboot] Re : Re: When does AMD release the fam15 spectre microcode updates?

Hi Florentin, Dne 25.4.2018 v 18:42 eche...@free.fr napsal(a): > Hello Rudolf, > First thank your for finding these blobs and the hack to use them, and for > testing and validating them. > But please could you tell us what was the setup for your tests : > - what was your hardware : cpu + mobo

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi, Dne 17.4.2018 v 12:09 awokd via coreboot napsal(a): > At what byte locations in the header is the equivalence table? I was > looking for this... Hm I'm not aware where is it documented, or if there is some tool to manipulate it/dump the structure. Maybe it could be added to some existing

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi, I found new microcode here [1], I used cpu00610F01_ver0600111F_2018-03-05_AC55EB96.bin as a microcode for my Trinity family15h CPU. I hacked together a new microcode header which contains the equivalence table etc to be able to load this microcode into the CPU from Linux. dd

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi, There is slight update from AMD [1], relevant part for you: *AMD Microcode Updates for GPZ Variant 2/Spectre* In addition, microcode updates with our recommended mitigations addressing Variant 2 (Spectre) have been released to our customers and ecosystem partners for AMD processors

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi, Dne 29.3.2018 v 20:39 taii...@gmx.com napsal(a): >> Plus make sure you enable "LFENCE is dispatch serializing" - perhaps >> coreboot can do that :) it is simple >> MSR write on fam 10h 12h+ the fam 11h and 0fh dont have this MSR but LFENCE >> is dispatch serilizing. > Hmm do you have more

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

Hi, What do you want to protect? If you want to protect the kernel, retpolines are OK on AMD. And you don't need any microcode update. Your CPU needs to have SMEP, otherwise you would need to clear RSB on CPL change (the paper on mentined page says that you need to do that always, but at least

Re: [coreboot] AMG G-series - Steppe eagle - PCI IRQ Routing to 8259 PIC

Hi Abhishek, Please can you check if you programmed the ELCR registers 0x4d0/0x4d1 to level for PCI registers? In other words, you should set bits to 1 to corresponding IRQ to be level triggered. Eg. for IRQ 5, you need to write 1 to bit5 to 8bit I/O port 0x4d0 For IRQ 9, you need to program bit

[coreboot] FYI: Reverse Engineering x86 Processor Microcode

Hi all, I think some of you might already noticed a nice paper: Microcode is an abstraction layer on top of the physical components of a CPU and present in most generalpurpose CPUs today. In addition to facilitate complex and vast instruction sets, it also provides an update mechanism that

Re: [coreboot] Howto enable AMD Cool'n'Quiet support

Hi, Sorry for the delay.> CPU ID 0x8001: fc0 So your CPU is revision "DH" which is pre "F". > But I have also seen that CONFIG_K8_REV_F_SUPPORT is not set in .config nope this is for some other CPUs. If you look to coreboot/src/cpu/amd/model_fxx/powernow_acpi.c, your CPU 0xfc0 has an

Re: [coreboot] Howto enable AMD Cool'n'Quiet support

Hi, I checked coreboot.rom-file and my vendor BIOS for that but can't find it. The coreboot provides the _PSS ACPI objects and not that PSB table. I guess you miss the _PSS objects for some reason. Did I miss to enable something in make menuconfig? Can someone give me a hint how to find

Re: [coreboot] Overheating on f2a85-m

Hi, > temporarily you could just wire your fan so that it will always work on the > max speed instead of taking the fan control commands from the motherboard Yes it can be switched to max RPM of fan like this: ruik ruik # echo 1 > /sys/class/hwmon/hwmon1/device/pwm1_enable ruik ruik # echo

Re: [coreboot] Overheating on f2a85-m

Hi again, Sorry, I pasted wrong dump. Before I installed right /etc/sensors3.conf radeon-pci-0008 Adapter: PCI adapter temp1:+35.0°C (crit = +120.0°C, hyst = +90.0°C) it8603-isa-0290 Adapter: ISA adapter Vcore:+1.27 V (min = +1.12 V, max = +2.96 V) ALARM in1: +1.66

Re: [coreboot] Overheating on f2a85-m

Hi Piotr, Are you sure that it is overheating? I would suspect RAM issues if you see some crashes. Is your CPU Trinity or Richland? If you modprobe it87 and you have some more recent kernel, you should see some temps reading: #sensors radeon-pci-0008 Adapter: PCI adapter temp1:+36.0°C

Re: [coreboot] Does the Core2Quad Mobile Q9100 require microcode updates?

Hi Timothy, Many thanks for pointing this out! We should put this somewhere to Wiki, in VERY LARGE letters as over the years I'm also very sensitive to all the people not liking to do their microcode update. I always failed to explain that microcode is not a program (despite the "code" in the

Re: [coreboot] coreboot assembly at 33c3

Hi I think I seen this. I hope it is accurate. https://events.ccc.de/congress/2016/wiki/Assembly:Coreboot Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] DMA protection? [AMD-Vi]

Hi all, Let me jump in. From the OS point of view the BME should be set for: 1) PCI bridges 2) for PCI class of IOAPIC devices (otherwise OS will not get any interrupt!) This PCI IOAPIC is for example on more high-end Xeons 3) sometimes it needs to be set on internal chipset devices. I

Re: [coreboot] Searching for datasheets concerning AMD SB950 southbridge chipset

Hi Marty, What is the northbridge? Is it also 9xx line? https://www.coreboot.org/Datasheets#AMD_990FX.2F990X.2F970 The southbridge should be the same as SB800 series, it should be SB850, only a name changed. The page above has a link to SB950 errata sheet. Hope it helps, Rudolf -- coreboot

Re: [coreboot] Why is subsystemid required to find a uPD7020200

Hi, As far I know it is because some drivers can detect workarounds based on subsystem IDs or under Windoze the drivers are often locked to particular subsystemID - 0x17aa is levovo. What OS do you use? Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] X120e AGESA hangs

Hi, You can use Bolton datasheets, should be same/similar. http://support.amd.com/TechDocs/51192_Bolton_FCH_RRG.pdf The said register access is forcing to use overriden EFUSE values, so I would say you have to check how their are programmed. Maybe you are trying to enable the EC without EC

Re: [coreboot] AMD platform: IO-APIC => Local APIC delivery modes

Hi again, > It would be interesting to test 0x00...300 and 0xff...400 just for > completeness. The 0x00...300 does the same (NMI delivered on all CPUs) and the other one does nothing. > That would be great. I am really curious about the official clarification on > the issue. Maybe there is a

Re: [coreboot] AMD platform: IO-APIC => Local APIC delivery modes

Hi Andriy, Thanks for the very detailed emails. It was great I could help. > I set Delivery Mode in the redirection table to the HyperTransport defined NMI > message type, 0_011, and it worked! Great, so there is a bug! Do you have some USB image I can try on more recent AMD system (with Hudson

Re: [coreboot] AMD platform: IO-APIC => Local APIC delivery modes

Hi again >> You can perhaps generate NMI using MSI/MSI-X or HPET (i tried with this) I did the HPET NMI generator on Intel PCH, it works fine. I just fill the MSI addr/data in a way that it was delivering NMI to certain CPU - physical delivery to a CPU with a certain ID. If this does not work

[coreboot] FYI: ACPI ASL 2.0

Hi all, Just FYI [1], maybe you already know. There is an alternate syntax available for ACPI ASL sources. It just converts Polish notation of ASL to something less geeky like C operators. It says that the tool to convert the sources is in development (to ratain comments). I think it would make

Re: [coreboot] Help find datasheet on amd R780L

Hi Alexey, It is this one: http://support.amd.com/TechDocs/43451.pdf Have fun, Rudolf -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Help find datasheet on amd R780L

Hi, Please provide the PCI id for device 0:0.0 Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] UEFI project ideas

Hi all, I noticed that seabios/libpayload could have interresting use cases and I want to share/discuss them. 1) Have a SeaBIOS be a UEFI application. This would benefit on UEFI platforms without CSM. 2) Provide a minimum UEFI environment. As I noticed u-boot started to have such support. In

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

Hi all, Most of 32-bit kernels (Unix/OS/whatever) usually have PAE support, so in fact they can cope with 36 bits of memory. The CPU PAE support started around Pentium. Windows XP+ has support for this. I think one can go with 2GB MMIO hole. The PCIe > 4GB is a question, I don't think

Re: [coreboot] ASRock E350M1: MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs

Hi all, > Could you please confirm that disabling the other two MSR tests for CS and > EIP is also the right thing to do? Yes I think this is OK. The SYSENTER MSRs are used by the OS and there is nothing which BIOS needs to setup. Same case is the SYSCALL MSR, GS/FS base and KERNEL GS base and

Re: [coreboot] ASRock E350M1: MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs

Hi all, This MSR is used when SYSENTER instruction is used by OS/application. The ESP MSR usually points to to the kernel stack of current thread, so if two different threads execute on different CPUs it will be different. False positive, and they should fix it. Thanks Rudolf -- coreboot

Re: [coreboot] how to route IRQ4 (COM1) on LPC bus for bayleybay_fsp

Hi What does it mean not available? Maybe you can check if you programmed ELCR register to edge for IRQ4. You can't share the IRQ4 with PCI IRQ I think thats why it does not work. You need to route the the PIRQA to something else, like IRQ3. Thanks Rudolf -- coreboot mailing list:

Re: [coreboot] Where is the first instrucion?

Hi, I guess your question is more general than the coreboot related right? If you have a firmware image dump of the flash (not the file you download from board vendor) then yes, first location to be executed is the instruction located 16 bytes before end of the image. In coreboot see in build/

Re: [coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems incomplete?

Hi In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is 0x12/0x11 while having booted the vendor binary and 0xff/0xff when having booted coreboot. Well this register is used only by OS when MPTABLE/ACPI PCI routing

Re: [coreboot] [Bug?] 3 different bytes in VGAbios after upgrade to coreboot

? (latest version of atomDis is already 4 years old...) I think there was some effort to make VGA BIOS from scratch. I think the guys used a script to rewrite it to C. I don't remember anymore. Thats all I know, Thanks Rudolf On 3 June 2015 at 20:27, Rudolf Marek r.ma...@assembler.cz wrote: Hi

Re: [coreboot] [Bug?] 3 different bytes in VGAbios after upgrade to coreboot

Hi all, First byte after IBM is usually a checksum. So in fact only two bytes differ. Now you may ask what it is... and it is a IOBASE :) typedef struct _ATOM_ROM_HEADER { ATOM_COMMON_TABLE_HEADER sHeader; UCHAR uaFirmWareSignature[4];/*Signature to distinguish between Atombios and

Re: [coreboot] Soft-Reset when enabling resources on Sun Ultra 40 M2

Hi, Sorry just a quick note, I need to go now. Usually it happens when resources assigned are wrong (like overlapping local APIC or the area ffe which is used to deliver IRQs. CHeck resource allocation. I assume your problem happens when you enable the bridge decoding. Thanks Rudolf

Re: [coreboot] AMD technical contact? / CAR issue

Hi Sevan, Well for this problem, I would like to see someone who is designated to help. I thought we had someone, but it looks like there is none. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] AMD technical contact? / CAR issue

Hi all, You a short update, 1) I still dont know whom to ask for help :/ 2) I analyzed the CAR teardown routine from vendor BIOS and from coreboot. There are some changes jnb - jmp and similar changes in AP teardown logic. The gcccar.inc in the binaryPI is perhaps ported from coreboot so the

Re: [coreboot] coreboot code of conduct

Hi all Just out of curiosity why do we need this? Was there some problem now or in the past? I just read the c c of c and I got this impression that we must be really bad that we need regulation arbitration. If nothing like this ever happened I would like to see some statement that this c

[coreboot] AMD technical contact?

Hi all, Who is the current AMD technical contact? I would like to know whom to ask for the help with the S3 CAR issue of fam15h. The CAR teardown routine has wbinvd instead of invd and memory is currupted with CAR contents during resume from suspend. Replacing WBINVD with INVD does not work,

Re: [coreboot] coreboot Prague meeting - details

09:50 Rudolf Marek napsal(a): photos from CESNET available here: https://filesender.cesnet.cz/?vid=21041c18-626a-b3e8-a2fe-1c38d083 Ruik -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] disable from: rewrite?

Hi all, Is there a mailman option on our ml to stop rewriting the From header of the email? It is quite retarded... Thanks Coreboot coreboot@coreboot.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot Prague meeting - details

photos from CESNET available here: https://filesender.cesnet.cz/?vid=21041c18-626a-b3e8-a2fe-1c38d083 Ruik -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot Prague meeting - details

Hi Hotel reception has non-stop. You can go to hotel first. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot hackaton/meeting in Prague - october 2014 - official date set

Hi all, I have some more people which signed up in the doodle. I need an email to send them details. If someone knows their email, please let me know. Cris Sommerland Philipp Deppenwiese Kai Michaelis Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] coreboot hackaton/meeting in Prague - october 2014 - official date set

Hi all, I would like to remind you our Prague hackaton meeting in October (16-19). I managed to get patronage from dean of the Faculty of Information Technology, Czech Technical University and also patronage from CESNET (Czech education and science network) To properly size the event room (so

[coreboot] FYI: latest ACPICA acpidump is broken

Hi, ruiktest ~ # /tmp/acpidump Could not get ACPI tables, AE_BAD_HEADER It seems there is a bug in ACPICA, coreboot is using revision 0 (ACPI 1.0) if there is no XSDT. But ACPICA expect always ACPI 2.0 style which have a len record. This is bit more complicated, coreboot creates a header with

Re: [coreboot] coreboot hackaton/meeting in Prague - october 2014 - official date set

Hi all, I updated the dates to the proposed dates 16,17,18,19 of October. This are now the fixed dates and won't change ever again. The doodle link remains the same. I updated the list except for Paul Menzel which I dont know if he could attend. Please if you want to come, sign in in the

Re: [coreboot] Help for Coreboot project

Hi Антон I think this could be used to develop something like native radeon video init. Perhaps similar approach was used by ron co develop native intel video init. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] F2A85-M: Chassis Fan Not Working

Hi I think this is the problem: change the following line in the devicetree.cb register hwm_fan2_ctl_pwm = 0x80 To 0x00 For some reason automatic settings for fan2 does not work... or is badly set up. Idwer: He uses the extra fan, not only the CPU fan. Please let us know if this helps,

Re: [coreboot] F2A85-M: Chassis Fan Not Working

. The change should make it manual mode (which has some non-zero pwm by default, so fan should spin) Thanks Rudolf ron On Sun, Jul 6, 2014 at 1:47 PM, Rudolf Marek r.ma...@assembler.cz mailto:r.ma...@assembler.cz wrote: Hi I think this is the problem: change the following line

Re: [coreboot] coreboot hackaton/meeting in Prague - september 2014 - date shift?

Hi all, What about 16 17 18 19 of October then? It is already in the university semester so there could be trouble with dormitory accommodation, but I think no trouble with some room @university. I would like to shift the date only once, if there is anyone with objections (especially those

Re: [coreboot] coreboot hackaton/meeting in Prague - september 2014

Hi David Thanks for the offer. I think we can go to university I have pre-arranged it there. The google office hint was that you can most likely work from there and thus stay longer here if you want to explore Prague for more days. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] F2A85-M: Chassis Fan Not Working

Hi, I implemented the initialization of hardware monitor ldn inside the ite chip. What do you mean not working stopped spinning? Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] coreboot hackaton/meeting in Prague - september 2014

Hi all, First of all sorry that it took so long to get back to this. I have in plan to organize a coreboot meeting in the Prague on 19,20,21 of September. I created the doodle here: http://doodle.com/h6yar2mtxarvhv3x I put there also Thursday if we want to meet earlier. The programme is to

Re: [coreboot] AMD A76M chipset?

Hi all, I'm CCing Bruce, maybe he knows. According to random googled page: The A76M FCH is an upgraded A70M FCH, or better yet A76M = Bolton M3 and A70M = Hudson M3. Does anyone know if there are public docs for the A76M (possibly under another name), and how feasible it is to drive it with

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

Hi all, 1) we should provide at least the MP-Table. There is a still lot of OS without ACPI support (various homebrew OS, RTOS etc) which don't want to carry the ACPICA just to get idea how to route IRQs... 2) if we want to setup the PCI for PIC we need to do: a) setup the PCI router (just

Re: [coreboot] ASUS F2A85-M (Pro)

Hi Kete Yes it looks like the ASUS F2A85-M is already phased out. It s a pity because I always fix everything when it is already quite late. I checked the PRO variant and it has other SuperIO chip and other ASIC chips for the advanced overclocking. The board is very different from the

[coreboot] eventlong backtrace support

Hi all, I'm still suffering with following errors ONLY when using 4 core Trinity CPU on the F2A85-M: EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 =

Re: [coreboot] Flash access on ASUS F2A85 variants

Hi Stefan, I could not find any details but the error message one receives: ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access. Found ITE Super I/O, ID 0x8603 on port 0x2e Found chipset AMD FCH with PCI ID 1022:780e. Enabling flash write... SPI base address is at

Re: [coreboot] Flash access on ASUS F2A85 variants

Hi Stefan, I just tried with v6402 which is open: 00:14.3 ISA bridge: Advanced Micro Devices [AMD] Hudson LPC Bridge (rev 11) 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85 30: 00 00 00

Re: [coreboot] S3 Resume on AMD Trinity APU

Hi, It works fine with DVI ans SUB. No need to re-run anything at least in the Linux. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] I've turned on paging as a test

Hi all, 1) As for NULL checkes I did something similar years ago: http://www.coreboot.org/pipermail/coreboot/2011-July/065792.html Here is a PoC of NULL pointer dereference checking in coreboot x86. It is surprisingly easy to implement. It uses strange expand down segments, making a data

Re: [coreboot] F2A85-M coreboot not working

Hi all, I'm back. Any news on this issue? Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

Hi all, I checked the BKDG on AMD website and there is not much register differences between those CPUs: 42300 Rev 3.10 - June 04, 2013 BKDG for AMD Family 15h Models 10h-1Fh Processors: 1.5.4 Changes For Revision RL-A1 • Changes that may result in BIOS modifications. • Added 2.5.9.1

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

Perfect thank you for this whole procedure. This is what I obtain: My rom (with my vga bios): coreboot-4.0-5394-gba6b07e Thu Jan 30 19:48:58 CET 2014 starting... BSP Family_Model: 00610f31 cpu_init_detectedx = agesawrapper_amdinitreset OK. Please can you enable AGESA debug stuff. It

Re: [coreboot] Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0

On 25.1.2014 12:01, Oliver Schinagl wrote: Nobody interested at all? Well not true :) I thought immediately oh nice I always wanted to design that. I was not in the FOSDEM this year, but if usual suspect have them, I will ask them if they could ship it to me! Anyway thanks for a great

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On 31.1.2014 13:53, HacKurx wrote: No way. You will need to use serial port. Just plug the header to mainboard and use some USB 2 serial from other computer (together with null modem cable) if you need more info please let me know. Do you have any links, diagram or picture for this method?

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

On 30.1.2014 11:03, HacKurx wrote: Is it Richland or Trinity? Seems it is Richland. I haven't tried with Richland yet. Yes indeed it's Richland. It would be helpful if you could include log from serial console. Maybe you hit some other problem. How without serial port? No way. You will

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

Hi, _F2A85-M REV 1.02 _AMD A8-6600K APU (Radeon HD 8570D vga = 1002,990e) _Corsair Value Select 4 Go DDR3 1333 MHz CL9 (CMV4GX3M1A1333C9) Is it Richland or Trinity? Seems it is Richland. I haven't tried with Richland yet. I proceeded to build a standard coreboot image using seabios as a

Re: [coreboot] ATTN: ruik, others: f2a85-m frequently crashes/freezes under high load. do you have it working?

Hi again, So far I had no luck reproducing it. Can you provide output of following command please: sudo setpci -s 14.0 8.b It should print number like 11, 12, 13 or 14. This is in fact your SB revision. I need it to check the errata sheet. Also please provide the clock source information

[coreboot] q to AMD folks - version of CIMX of fam15tn

Hi all, Please can anyone with access to AGESA check what version of AGESA and CIMX (FCH module) was used for coreboot release? I want to check some erratas and AMD 48671 document http://support.amd.com/TechDocs/48671.pdf Refers to CIMX versions, however there is no define with CIMX

Re: [coreboot] ATTN: ruik, others: f2a85-m frequently crashes/freezes under high load. do you have it working?

Hi Andrew, ruik, do you have a working setup with a f2a85-m motherboard at the moment (i.e. .config file, graphics card, distro/kernel version being used?) if nothing is working for you right now, how can we narrow this down? Yes it seems it is working fine. You can check

Re: [coreboot] coreboot on amd A85 can't work

Hi 陈军根, Please put to cc the mailing list. I can't find spdAddressLookup in dimmSpd.c(coreboot v4),but I find Ahh yes it seems to move to generic wrapper code. You will need to modify devicetree.cb where is the table and then it is generated as static.c ROMSTAGE_CONST struct

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